CN101257297A

CN101257297A - transistor switch

Info

Publication number: CN101257297A
Application number: CNA2007101648717A
Authority: CN
Inventors: K·科尼利森斯; M·斯特亚尔特
Original assignee: Infineon Technologies AG
Current assignee: Infineon Technologies AG
Priority date: 2006-12-08
Filing date: 2007-12-07
Publication date: 2008-09-03
Anticipated expiration: 2027-12-07
Also published as: DE102007055419B4; US7492207B2; US20080136495A1; DE102007055419A1; CN101257297B

Abstract

The invention discloses a circuit comprising a transistor switch having a first terminal receiving an input voltage, a second terminal outputting an output voltage, and a gate terminal; a determination circuit coupled to the first terminal and the second terminal of the transistor switch , to determine a lower or higher voltage between the input voltage and the output voltage; a voltage generator, coupled to the determination circuit, to generate a sum voltage or a difference voltage using the lower or higher voltage; and a control circuit, coupled to the voltage generator and A gate terminal of the transistor switch to which a sum voltage or a difference voltage is applied during a first time interval.

Description

transistor switch

技术领域 technical field

本发明通常涉及晶体管开关并尤其涉及自举场效应晶体管开关。The present invention relates generally to transistor switches and more particularly to bootstrap field effect transistor switches.

背景技术 Background technique

例如当采用CMOS(互补金属氧化物半导体(Complementary Metal OxideSemiconductor))技术时，场效应晶体管可用作开关。于是场效应晶体管的源极和漏极端子构成开关的输入和输出端子，而场效应晶体管的栅极端子是开关的控制端子。然而，场效应晶体管具有非理想性，所述非理想性例如会导致开关的开态电阻(on-resistance)根据所施加的电压变动。而且当开关变换状态时可发生跃迁效应。Field-effect transistors can be used as switches, for example when using CMOS (Complementary Metal Oxide Semiconductor) technology. The source and drain terminals of the field effect transistor then form the input and output terminals of the switch, while the gate terminal of the field effect transistor is the control terminal of the switch. However, field effect transistors have non-idealities that, for example, cause the on-resistance of the switch to vary depending on the applied voltage. Also transition effects can occur when the switch changes state.

场效应晶体管的问题是与电压相关的开态电阻。用作开关的场效应晶体管具有非零开态电阻R_on，其可概略地近似为：The problem with field effect transistors is the voltage-dependent on-resistance. A field effect transistor used as a switch has a non-zero on-state resistance R _on which can be roughly approximated as:

${R R}_{on on} = = \frac{11}{KP KP \cdot \cdot \frac{W W}{L L} \cdot &Center Dot; (({V V}_{G G} - - {V V}_{T T} - - \frac{{V V}_{S S} + + {V V}_{D D.}}{22}))} - - - - - - ((11))$

其中KP是电荷载流子迁移率μ和氧化物电容C_ox的乘积，W和L分别是沟道区域的宽度和长度，以及V_S、V_D、V_G和V_T分别是源极电压、漏极电压、栅极电压和阈值电压。根据方程(1)，开态电阻R_on是源极电压V_S的函数，开态电阻R_on取决于输入电压V_in。where KP is the product of charge carrier mobility μ and oxide capacitance C _ox , W and L are the width and length of the channel region, respectively, and V _S , V _D , V _G and V _T are the source voltage, Drain voltage, gate voltage, and threshold voltage. According to equation (1), the on-state resistance R _on is a function of the source voltage V _S , and the on-state resistance R _on depends on the input voltage V _in .

场效应晶体管的另一问题是阈值电压V_T对体源(bulk-source)电压V_BS的相关性。该效应可近似为：Another problem with field effect transistors is the dependence of the threshold voltage V _T on the bulk-source voltage V _BS . This effect can be approximated as:

${V V}_{T T} = = {V V}_{T T 00} &PlusMinus; &PlusMinus; γ γ \cdot &Center Dot; ((\sqrt{22 \cdot &Center Dot; | | {φ φ}_{F f} | | - - {V V}_{BS BS}} - - \sqrt{22 \cdot &Center Dot; | | {φ φ}_{F f} | |})) - - - - - - ((22))$

其中γ是取决于所用工艺的技术常数且φ_F是费米能级(Fermi level)。where γ is a technical constant depending on the process used and φ _F is the Fermi level.

因为方程(2)是源极电压V_S函数，所以阈值电压V_T取决于输入电压V_in。根据方程(1)，这还影响开关的开态电阻R_on。Since equation (2) is a function of the source voltage V _S , the threshold voltage V _T depends on the input voltage _Vin . According to equation (1), this also affects the on-resistance R _on of the switch.

场效应晶体管的另一非理想性是电荷注入。电荷注入是当开关关断时将会使开关的输入和输出电压失真的跃迁效应。当场效应晶体管关断时，在沟道中已积累的电荷必须消失。根据这些端子的总电容，该电荷将在源极和漏极侧之间分开。对开关的源极电压V_S的效应ΔV由方程(3)近似。参数A取决于场效应晶体管的源极和漏极端子的总电容。Another imperfection of field effect transistors is charge injection. Charge injection is a transition effect that distorts the input and output voltages of the switch when the switch is turned off. When the FET is turned off, the charge that has accumulated in the channel must disappear. Depending on the total capacitance of these terminals, this charge will be split between the source and drain sides. The effect ΔV on the source voltage _VS of the switch is approximated by equation (3). Parameter A depends on the total capacitance of the source and drain terminals of the field effect transistor.

$ΔV ΔV = = A A \cdot &Center Dot; \frac{{C C}_{OX OX} \cdot &Center Dot; W W \cdot &Center Dot; L L \cdot &Center Dot; (({V V}_{G G} - - {V V}_{S S} - - {V V}_{T T}))}{{C C}_{GS GS} + + {C C}_{BS BS} + + {C C}_{sample sample}} - - - - - - ((33))$

其中当用在采样和保持结构中C_OX、C_GS、C_BS和C_sample分别是氧化物容量(capacity)、栅源极容量、体源极容量和开关的负载电容，且0＜A＜1。When used in the sample and hold structure, C _OX , C _GS , C _BS and C _sample are the oxide capacity, gate-source capacity, body-source capacity and load capacity of the switch respectively, and 0<A<1 .

当开关关断时使开关的源极和漏极电压失真的另一跃迁效应是时钟馈通。晶体管开关的寄生栅源极电容C_GS与源极的负载电容一起在时钟信号和输出端子之间形成分压器。这导致驱动开关的控制信号的馈通。该效应可近似为：Another transition effect that distorts the source and drain voltages of a switch when the switch is turned off is clock feedthrough. The parasitic gate-source capacitance _CGS of the transistor switch, together with the load capacitance at the source, forms a voltage divider between the clock signal and the output terminal. This results in a feedthrough of the control signal driving the switch. This effect can be approximated as:

$ΔV ΔV = = \frac{{C C}_{GS GS}}{{C C}_{GS GS} + + {C C}_{BS BS} + + {C C}_{sample sample}} \cdot &Center Dot; (({V V}_{G G,, off off} - - {V V}_{G G,, on on})) - - - - - - ((44))$

其中V_G，off和V_G，on分别是当开关关断和接通时的栅极电压。where VG _,off and _VG,on are the gate voltages when the switch is off and on, respectively.

晶体管开关的非线性开态电阻R_on(见方程(1))的公知解决方案是自举(bootstrapping)。在采样阶段期间，自举使开关的栅源极电压V_GS恒定，导致信号不依赖于开态电阻R_on。例如通过例如当开关接通时在源极和栅极端子之间施加恒定电压、例如供应电压V_dd来实现自举。A known solution to the nonlinear _on -resistance Ron (see equation (1)) of a transistor switch is bootstrapping. During the sampling phase, the bootstrap keeps the gate-source voltage V _GS of the switch constant, resulting in a signal independent of the on-resistance R _on . Bootstrap is achieved eg by applying a constant voltage, eg supply voltage _Vdd , between the source and gate terminals eg when the switch is on.

自举技术的缺点在于升高栅极电压V_G到超过源极电压V_S的特定值，这可能导致可靠性的问题。A disadvantage of the bootstrap technique is that it boosts the gate voltage _VG to a certain value above the source voltage _VS , which may cause reliability problems.

发明内容 Contents of the invention

为了提供对本发明的一些方面的基本理解，下面提供本发明的简要概述。该概述不是本发明的广泛综述。不是意欲识别本发明的主要和关键要素也不是意欲描述本发明的范围。而是，其首要目的仅是以简化的形式呈现本发明的一个或多个构思来作为稍后呈现的更详细描述的序言。In order to provide a basic understanding of some aspects of the invention, a brief summary of the invention is provided below. This summary is not an extensive overview of the invention. It is intended to neither identify key or critical elements of the invention nor delineate the scope of the invention. Rather, its primary purpose is to present one or more concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later.

根据本发明的一个实施例，电路包括场效应晶体管开关、确定电路、电压生成器和控制电路。晶体管开关具有第一端子用以接收输入电压、第二端子用以输出输出电压以及栅极端子。如果晶体管开关是n型晶体管，则确定电路确定输入电压和输出电压之间的较低电压，且电压生成器通过向较低电压添加第一预定电压来生成和电压。如果晶体管是p型晶体管，则确定电路确定输入电压和输出电压之间的较高电压，且电压生成器通过从较高电压减去第一预定电压来生成差电压。在第一时间间隔期间，控制电路向晶体管开关的栅极端子施加和电压或差电压。According to one embodiment of the present invention, the circuit includes a field effect transistor switch, a determination circuit, a voltage generator and a control circuit. The transistor switch has a first terminal for receiving an input voltage, a second terminal for outputting an output voltage, and a gate terminal. If the transistor switch is an n-type transistor, the determination circuit determines a lower voltage between the input voltage and the output voltage, and the voltage generator generates a sum voltage by adding a first predetermined voltage to the lower voltage. If the transistor is a p-type transistor, the determination circuit determines a higher voltage between the input voltage and the output voltage, and the voltage generator generates a difference voltage by subtracting the first predetermined voltage from the higher voltage. During a first time interval, the control circuit applies a sum voltage or a difference voltage to the gate terminal of the transistor switch.

根据本发明的另一实施例，电路包括场效应晶体管开关、确定电路和控制电路。晶体管开关具有第一端子用以接收输入电压、第二端子用以输出输出电压和体端子。如果晶体管开关是n型晶体管，确定电路确定输入电压和输出电压之间的较低电压，且在第一时间间隔期间，控制电路向晶体管开关的体端子施加较低电压或和电压，所述和电压是预定电压和较低电压之和。如果晶体管开关是p型晶体管，确定电路确定输入电压和输出电压之间的较高电压，且在第一时间间隔期间，控制电路向晶体管开关的体端子施加较高电压或和电压，所述和电压是预定电压和较高电压之和。According to another embodiment of the present invention, the circuit includes a field effect transistor switch, a determination circuit and a control circuit. The transistor switch has a first terminal for receiving an input voltage, a second terminal for outputting an output voltage, and a bulk terminal. If the transistor switch is an n-type transistor, the determination circuit determines the lower voltage between the input voltage and the output voltage, and during the first time interval the control circuit applies the lower voltage or the sum voltage to the bulk terminal of the transistor switch, the sum The voltage is the sum of the predetermined voltage and the lower voltage. If the transistor switch is a p-type transistor, the determination circuit determines the higher voltage between the input voltage and the output voltage, and during the first time interval the control circuit applies the higher voltage or the sum voltage to the bulk terminal of the transistor switch, the sum The voltage is the sum of the predetermined voltage and the higher voltage.

根据本发明的另一实施例，电路包括场效应晶体管开关、电压生成器和控制电路。晶体管开关具有第一端子用以接收输入电压、第二端子用以输出输出电压以及栅极端子。电压生成器通过向输入或输出电压添加预定电压生成和电压以及通过从输入或输出电压减去预定电压生成差电压。控制电路在第一时间间隔期间向晶体管开关的栅极端子施加和电压以及在第二时间间隔期间向晶体管开关的栅极端子施加差电压。According to another embodiment of the invention, a circuit includes a field effect transistor switch, a voltage generator and a control circuit. The transistor switch has a first terminal for receiving an input voltage, a second terminal for outputting an output voltage, and a gate terminal. The voltage generator generates a sum voltage by adding a predetermined voltage to the input or output voltage and generates a difference voltage by subtracting the predetermined voltage from the input or output voltage. The control circuit applies a sum voltage to the gate terminal of the transistor switch during a first time interval and applies a difference voltage to the gate terminal of the transistor switch during a second time interval.

根据本发明的另一实施例，模拟数字转换器包括上述电路之一。According to another embodiment of the present invention, the analog-to-digital converter includes one of the above circuits.

附图说明 Description of drawings

为了完成前述和相关的目标，下面的描述和附图详细阐述了本发明的例示性的方面和实施。这些仅示出可使用本发明的一个或多个方面的众多方式中的几种。当结合附图考虑时，从下面的本发明详细描述中，本发明的其他方面、优点和新颖特征将变得明显。To the accomplishment of the foregoing and related ends, the following description and drawings set forth in detail illustrative aspects and implementations of the invention. These are just a few of the many ways in which one or more aspects of the invention may be used. Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the accompanying drawings.

图1示意性示出第一实例电路100。FIG. 1 schematically shows a first example circuit 100 .

图2示意性示出第二实例电路200。FIG. 2 schematically shows a second example circuit 200 .

图3示意性示出第三实例电路300。FIG. 3 schematically shows a third example circuit 300 .

图4示意性示出确定电路301的示范性实施。FIG. 4 schematically shows an exemplary implementation of the determination circuit 301 .

图5示意性示出第四实例电路500。FIG. 5 schematically shows a fourth example circuit 500 .

图6示意性示出第五实例电路600。FIG. 6 schematically shows a fifth example circuit 600 .

图7示意性示出第六实例电路700。FIG. 7 schematically shows a sixth example circuit 700 .

图8示意性示出第七实例电路800。FIG. 8 schematically shows a seventh example circuit 800 .

具体实施方式 Detailed ways

参考附图描述本发明的以下实施例，其中相同的参考数字通常通篇用于指示相同的元件，且其中各种结构不必要按比例画出。在如下的描述中，为了解释的目的，为了提供对本发明实施例的一个或多个方面的彻底理解，阐述多个具体细节。然而，对本领域技术人员来说，可用这些具体细节的更少的程度实践本发明实施例的一个或多个方面，是显而易见的。在其他情况中，为了有助于描述本发明实施例的一个或多个方面，以框图形式示出已知结构和器件。因此不应在限制性意义上理解下面的描述，且本发明的范围通过所附的权利要求来限定。The following embodiments of the present invention are described with reference to the drawings, wherein like reference numerals are generally used to refer to like elements throughout, and wherein various structures are not necessarily drawn to scale. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more aspects of the embodiments of the invention. It will be apparent, however, to one skilled in the art that one or more aspects of the embodiments of the invention may be practiced with a lesser degree of these specific details. In other instances, well-known structures and devices are shown in block diagram form in order to facilitate describing one or more aspects of the embodiments of the invention. The following description should therefore not be read in a limiting sense, and the scope of the invention is defined by the appended claims.

参考图1，示出电路100的框图，其作为本发明的第一方面的示范性实施例。电路100包括晶体管MSA、确定电路101、电压生成器102和控制电路103。Referring to FIG. 1 , there is shown a block diagram of a circuit 100 as an exemplary embodiment of the first aspect of the invention. The circuit 100 includes a transistor MSA, a determination circuit 101 , a voltage generator 102 and a control circuit 103 .

当开关接通、即晶体管MSA的沟道导通时，晶体管MSA起场效应晶体管开关的作用且在其第一端子接收输入电压V_in并在其第二端子提供输出电压V_out。晶体管MSA的沟道可以是n掺杂的或p掺杂的。When the switch is on, ie the channel of transistor MSA is conducting, transistor MSA acts as a field effect transistor switch and receives an input voltage V _in at its first terminal and provides an output voltage V _out at its second terminal. The channel of transistor MSA can be n-doped or p-doped.

例如，晶体管MSA可形成离散时间模拟采样电路的部分，所述离散时间模拟采样电路为了将模拟信号转换成数字值而对输入电压V_in进行采样。For example, transistor MSA may form part of a discrete-time analog sampling circuit that samples the input voltage _Vin for the purpose of converting an analog signal into a digital value.

确定电路101具有两个输入端子，两个输入端子中的一个连接到晶体管MSA的第一端子且另一输入端子连接到晶体管MSA的第二端子。确定电路101的输出端子连接到电压生成器102的输入端子，该电压生成器的输出端子被接线到控制电路103的输入端子。控制电路103的输出端子驱动晶体管MSA的栅极端子。The determination circuit 101 has two input terminals, one of which is connected to the first terminal of the transistor MSA and the other input terminal is connected to the second terminal of the transistor MSA. An output terminal of the determination circuit 101 is connected to an input terminal of a voltage generator 102 whose output terminal is wired to an input terminal of a control circuit 103 . The output terminal of the control circuit 103 drives the gate terminal of the transistor MSA.

如果晶体管MSA是n型晶体管，则确定电路101的功能是确定输入电压V_in和输出电压V_out哪个较低。例如，当开关闭合、即当晶体管MSA从不导通状态切换到导通状态的时刻进行该测量。在输入电压V_in和输出电压V_out之间的较低电压被传输到电压生成器102，该电压生成器向较低电压V_low添加预定电压。预定电压是在晶体管MSA导通时不变化的固定电压。例如，预定电压可以是为电路100提供电源的供应电压V_dd，或可以是来自供应电压V_dd的固定电压，其中固定电压小于供应电压V_dd。较低电压V_low和预定电压的和电压V_sum、即例如(V_low+V_dd)被提供给控制电路103。控制电路103在第一时间间隔期间给晶体管MSA的栅极端子施加和电压V_sum。在第二时间间隔期间，例如地电势V_ss可被施加到晶体管MSA的栅极端子。If the transistor MSA is an n-type transistor, the function of the determination circuit 101 is to determine which of the input voltage V _in and the output voltage V _out is lower. For example, the measurement is taken at the moment when the switch is closed, ie when transistor MSA switches from a non-conducting state to a conducting state. The lower voltage between the input voltage V _in and the output voltage V _out is transmitted to a voltage generator 102 which adds a predetermined voltage to the lower voltage V _low . The predetermined voltage is a fixed voltage that does not vary when the transistor MSA is turned on. For example, the predetermined voltage may be a supply voltage V _dd that provides power to the circuit 100 , or may be a fixed voltage from the supply voltage V _dd , wherein the fixed voltage is less than the supply voltage V _dd . The lower voltage V _low and the sum voltage V _sum of the predetermined voltage, ie (V _low +V _dd ), for example, are supplied to the control circuit 103 . The control circuit 103 applies the sum voltage V _sum to the gate terminal of the transistor MSA during the first time interval. During the second time interval eg ground potential V _ss may be applied to the gate terminal of transistor MSA.

例如，在第一时间间隔期间，晶体管MSA处于“接通(on)”状态。把和电压V_sum施加到栅极端子且从漏极至源极建立低开态电阻。当电路100用作模数转换器的一部分时，在第一时间间隔期间对模拟输入信号采样。在第二时间间隔期间，晶体管MSA的栅极端子接地以便晶体管MSA处于“截止(off)”状态。For example, during a first time interval, transistor MSA is in an "on" state. A sum voltage V _sum is applied to the gate terminal and a low on-resistance is established from drain to source. When circuit 100 is used as part of an analog-to-digital converter, the analog input signal is sampled during a first time interval. During the second time interval, the gate terminal of transistor MSA is grounded so that transistor MSA is in an "off" state.

如果晶体管MSA是p型晶体管，确定电路101、电压生成器102和控制电路103的功能稍微不同于当晶体管MSA是n型晶体管时的功能。对于p掺杂的晶体管沟道，确定电路101确定输入电压V_in和输出电压V_out哪个较高。例如，当开关闭合时、即当晶体管MSA从不导通状态切换到导通状态时进行该测量。在输入电压V_in和输出电压V_out之间的较高电压V_high被传输到电压生成器102，该电压生成器从较高电压V_high减去预定电压、例如供应电压V_dd。预定电压是在晶体管MSA导通时不变化的固定电压。较高电压V_high和预定电压的差电压、即例如(V_high-V_dd)被提供给控制电路103。控制电路103在第一时间间隔期间向晶体管MSA的栅极端子施加差电压V_difference。在第二时间间隔期间，例如供应电压V_dd可被施加到晶体管MSA的栅极端子。If transistor MSA is a p-type transistor, the functions of determination circuit 101 , voltage generator 102 and control circuit 103 are slightly different from those when transistor MSA is an n-type transistor. For a p-doped transistor channel, the determination circuit 101 determines which of the input voltage V _in and the output voltage V _out is higher. For example, the measurement is taken when the switch is closed, ie when transistor MSA switches from a non-conducting state to a conducting state. A higher voltage V _high between the input voltage V _in and the output voltage V _out is transmitted to a voltage generator 102 which subtracts a predetermined voltage, for example a supply voltage V _dd , from the higher voltage V _high . The predetermined voltage is a fixed voltage that does not vary when the transistor MSA is turned on. A difference voltage between the higher voltage V _high and the predetermined voltage, ie (V _high −V _dd ), for example, is supplied to the control circuit 103 . The control circuit 103 applies the difference voltage _Vdifference to the gate terminal of the transistor MSA during the first time interval. During the second time interval, eg a supply voltage V _dd may be applied to the gate terminal of transistor MSA.

晶体管MSA的栅极端子可被设置在源极和漏极电压的最小值(或在p型晶体管MSA的情况下最大值)，随预定的固定电压、例如供应电压V_dd增加(或减少)。该最小(或最大)电压在开关闭合时被确定。在开关闭合期间，栅极电压保持跟随该电压。通过选择最小(或最大)电压侧，在栅极和源极电压之间以及在栅极和漏极电压之间的差将不超过供应电压V_dd。这可有助于解决上述的可靠性问题。The gate terminal of transistor MSA may be set at a minimum (or maximum in case of p-type transistor MSA) source and drain voltage, increasing (or decreasing) with a predetermined fixed voltage, eg supply voltage _Vdd . This minimum (or maximum) voltage is determined when the switch is closed. During switch closure, the gate voltage keeps following this voltage. By choosing the minimum (or maximum) voltage side, the difference between the gate and source voltage and between the gate and drain voltage will not exceed the supply voltage V _dd . This can help address the reliability issues described above.

参考图2，电路200的框图。电路200包括晶体管MSA、确定电路201和电压生成器202。电路200还可包括控制电路203用以驱动晶体管200的栅极端子。Referring to FIG. 2 , a block diagram of circuit 200 . The circuit 200 includes a transistor MSA, a determination circuit 201 and a voltage generator 202 . The circuit 200 may also include a control circuit 203 for driving the gate terminal of the transistor 200 .

如在电路100中，当开关接通、即晶体管MSA的沟道导通时，晶体管MSA起场效应晶体管开关的作用且在其第一端子接收输入电压V_in并在其第二端子提供输出电压V_out。晶体管MSA的沟道可以是n掺杂的或p掺杂的。As in circuit 100, when the switch is on, i.e. the channel of transistor MSA is conducting, transistor MSA acts as a field effect transistor switch and receives the input voltage _Vin at its first terminal and provides the output voltage at its second terminal V _out . The channel of transistor MSA can be n-doped or p-doped.

确定电路201具有两个输入端子，两个输入端子中的一个连接到晶体管MSA的第一端子且另一输入端子连接到晶体管MSA的第二端子。确定电路201的输出端子连接到控制电路202的输入端子。控制电路202的输出端子被接线到晶体管MSA的体端子。The determination circuit 201 has two input terminals, one of which is connected to the first terminal of the transistor MSA and the other input terminal is connected to the second terminal of the transistor MSA. The output terminal of the determination circuit 201 is connected to the input terminal of the control circuit 202 . The output terminal of control circuit 202 is wired to the bulk terminal of transistor MSA.

当晶体管MSA是n型晶体管时，确定电路201的作用是确定输入电压V_in和输出电压V_out哪个较低。例如，当开关闭合、即当晶体管MSA从不导通状态切换到导通状态的时刻进行该测量。在输入电压V_in和输出电压V_out之间的较低电压V_low被传输到控制电路202，该控制电路在第一时间间隔期间向晶体管MSA的体端子施加较低电压V_low。可选择地，在第一时间间隔期间，控制电路202可向较低电压V_low添加预定的固定电压并可向体端子施加该和电压。在第二时间间隔期间，例如地电势V_ss可被施加到晶体管MSA的体端子。例如，在第一和第二时间间隔期间，晶体管MSA分别处于“接通”和“截止”状态。When the transistor MSA is an n-type transistor, the function of the determination circuit 201 is to determine which is lower, the input voltage V _in or the output voltage V _out . For example, the measurement is taken at the moment when the switch is closed, ie when transistor MSA switches from a non-conducting state to a conducting state. The lower voltage V _low between the input voltage _Vin and the output voltage V _out is transmitted to the control circuit 202 which applies the lower voltage V _low to the bulk terminal of the transistor MSA during the first time interval. Alternatively, during the first time interval, the control circuit 202 may add a predetermined fixed voltage to the lower voltage V _low and may apply the sum voltage to the bulk terminal. During the second time interval, eg ground potential V _ss may be applied to the bulk terminal of transistor MSA. For example, during the first and second time intervals, transistor MSA is in the "on" and "off" states, respectively.

当晶体管MSA是p型晶体管时，确定电路201确定输入电压V_in和输出电压V_out哪个较高。在第一时间间隔期间，该较高电压V_high或预定电压和较高电压V_high的和电压被施加到晶体管MSA的体端子。在第二时间间隔期间，例如供应电压V_dd可被施加到晶体管MSA的体端子。When the transistor MSA is a p-type transistor, the determination circuit 201 determines which of the input voltage V _in and the output voltage V _out is higher. During the first time interval, the higher voltage V _high or the sum voltage of the predetermined voltage and the higher voltage V _high is applied to the bulk terminal of transistor MSA. During the second time interval, eg a supply voltage V _dd may be applied to the bulk terminal of transistor MSA.

晶体管MSA可包括三阱(triple-well)晶体管。三阱晶体管包括形成在衬底中的第一阱。第二阱形成在第一阱中。例如是源极或漏极的一个或多个第三阱形成在第二阱中。The transistor MSA may include a triple-well transistor. A triple well transistor includes a first well formed in a substrate. A second well is formed in the first well. One or more third wells, such as sources or drains, are formed in the second well.

由于利用所选择的最小(最大)电压驱动体端子，所以体源极电压V_BS可以是固定的。因此，可能不发生阈值电压V_T的变化(见方程(2))。Since the body terminal is driven with the selected minimum (maximum) voltage, the body-source voltage V _BS may be fixed. Therefore, a change in threshold voltage V _T may not occur (see equation (2)).

根据本发明的一个实施例，可结合以上示范性所述的本发明第一和第二方面。在图3中示出电路300的框图，其用作本发明第一和第二方面的结合的示范性实施例。在电路300中，场效应晶体管MSA的沟道是n掺杂的。确定在输入电压V_in和输出电压V_out之间的较低电压V_low的确定电路在图3中由301表示。而且，在图3中示出时钟信号φ和反向时钟信号φ。时钟信号φ控制晶体管开关MSA的切换状态。在第一时间间隔期间，时钟信号φ为高(反向时钟信号φ为低)且开关闭合意味着晶体管MSA的源极漏极路径导通。在第二时间间隔期间，时钟信号φ为低(反向时钟信号φ为高)且开关打开意味着源极漏极路径不导通。According to an embodiment of the invention, the first and second aspects of the invention described exemplarily above may be combined. In Fig. 3 is shown a block diagram of a circuit 300 which serves as an exemplary embodiment of a combination of the first and second aspects of the invention. In circuit 300, the channel of field effect transistor MSA is n-doped. A determination circuit for determining the lower voltage V _low between the input voltage _Vin and the output voltage V _out is denoted by 301 in FIG. 3 . Furthermore, a clock signal φ and an inverted clock signal φ are shown in FIG. 3 . The clock signal φ controls the switching state of the transistor switch MSA. During the first time interval, the clock signal φ is high (the inverted clock signal φ is low) and the switch is closed meaning that the source-drain path of transistor MSA is conducting. During the second time interval, the clock signal φ is low (the inverted clock signal φ is high) and the switch is open meaning that the source-drain path is not conducting.

当时钟信号φ为低时，晶体管MN1和MN2闭合，将电容器C1充电到供应电压V_dd。晶体管MN3和MN4也闭合，因此保持晶体管MSA的栅极端子为地电压V_ss，因此晶体管MSA不导通且开关打开。晶体管MP1将晶体管MP2的栅极端子保持在供应电压V_dd。因此晶体管MP2不导通且将电路节点302与晶体管MSA的栅极端子隔离。When the clock signal φ is low, transistors MN1 and MN2 are closed, charging capacitor C1 to the supply voltage _Vdd . Transistors MN3 and MN4 are also closed, thus keeping the gate terminal of transistor MSA at ground voltage V _ss , so transistor MSA is non-conductive and the switch is open. Transistor MP1 maintains the gate terminal of transistor MP2 at the supply voltage _Vdd . Transistor MP2 is therefore non-conductive and isolates circuit node 302 from the gate terminal of transistor MSA.

当时钟信号φ变为高电压时，晶体管MSA的源极漏极路径变成导通的且开关将闭合。时钟信号φ还触发确定电路301用以在输入电压V_in和输出电压V_out之间选择。因为晶体管MSA可以是n型晶体管，所以确定电路301决定输入电压V_in和输出电压V_out哪个较低且闭合适当的传输栅极TG1或TG2。该决定不变化直至时钟信号φ再次变低。晶体管MN1、MN2、MP1和MP4通过时钟信号φ的变化都打开。因此，电路节点303变为由确定电路301所选择的较低电压V_low。因为在第二时间间隔期间电容C1被充电至供应电压V_dd，所以电路节点302的电压上升为(V_low+V_dd)。晶体管MN5将降低晶体管MP2的栅极电压，闭合晶体管MP2。闭合晶体管MP2将导致晶体管MSA的栅极升高到(V_low+V_dd)。这将闭合晶体管MN6，这还有助于使晶体管MP2的栅极为较低电压V_low，使得在升压电容C1和晶体管MSA的栅极之间低电阻连接。因为晶体管MSA的栅极现在处于(V_low+V_dd)，所以开关闭合且因为其栅源极电压V_GS等于供应电压V_dd，所以开态电阻是依赖于信号的。When the clock signal φ goes to a high voltage, the source-drain path of transistor MSA becomes conductive and the switch will close. The clock signal φ also triggers the determination circuit 301 to select between the input voltage V _in and the output voltage V _out . Since transistor MSA may be an n-type transistor, the determination circuit 301 decides which of the input voltage V _in and the output voltage V _out is lower and closes the appropriate transfer gate TG1 or TG2 . This decision does not change until the clock signal φ goes low again. Transistors MN1, MN2, MP1 and MP4 are all turned on by changes in the clock signal φ. Consequently, circuit node 303 becomes the lower voltage V _low selected by determination circuit 301 . Since the capacitor C1 is charged to the supply voltage V _dd during the second time interval, the voltage at the circuit node 302 rises to (V _low +V _dd ). Transistor MN5 will lower the gate voltage of transistor MP2, closing transistor MP2. Closing transistor MP2 will cause the gate of transistor MSA to rise to (V _low +V _dd ). This closes transistor MN6, which also helps to bring the gate of transistor MP2 to a lower voltage _Vlow , making a low resistance connection between boost capacitor C1 and the gate of transistor MSA. Since the gate of transistor MSA is now at (V _low +V _dd ), the switch is closed and since its gate-source voltage V _GS is equal to the supply voltage V _dd , the on-state resistance is signal dependent.

在电路300中，MSA晶体管是三阱晶体管，且电路节点303连接到晶体管MSA的体端子。因此，当晶体管MSA导通时，其体电压V_B等于其源极电压V_S(即较低电压V_low)。这产生固定的体源极电压V_BS，其使得阈值电压V_T依赖于信号且取消了上述的体效应。在第二时间间隔期间，电路节点303被设置为地电势V_SS，因此体二极管的正向偏压是不可能的。In circuit 300, the MSA transistor is a triple well transistor, and circuit node 303 is connected to the bulk terminal of transistor MSA. Therefore, when transistor MSA is turned on, its bulk voltage V _B is equal to its source voltage V _S (ie, the lower voltage V _low ). This results in a fixed body-source voltage V _BS , which makes the threshold voltage V _T signal dependent and cancels the body effect described above. During the second time interval, circuit node 303 is set to ground potential V _SS , so forward biasing of the body diode is not possible.

晶体管MN2由时钟信号φ_bo驱动，该时钟信号是随供应电压V_dd增加的反向时钟信号φ。由于栅源极电压V_GS或栅漏极电压V_GD不超过额定供应电压V_dd，所以这可允许在没有可靠性问题的情况下设计电路300。Transistor MN2 is driven by a clock signal φ _bo , which is an inverted clock signal φ that increases with supply voltage V _dd . This may allow the circuit 300 to be designed without reliability issues since the gate-source voltage V _GS or the gate-drain voltage V _GD does not exceed the rated supply voltage V _dd .

根据方程(3)，电荷注入取决于栅源极电压V_GS、栅源极电容C_GS和体源极电容C_BS。如在电路300中，当开关闭合时，在第一时间间隔期间栅源极电压V_GS和体源极电压V_BS是固定的，寄生晶体管电容器也是固定的。因此由于电荷注入的电压跳跃依赖于输入电压V_in。例如，这允许在无需延迟时钟的情况下设计开关电容器系统。According to equation (3), the charge injection depends on the gate-source voltage V _GS , the gate-source capacitance C _GS and the body-source capacitance C _BS . As in circuit 300, when the switch is closed, the gate-source voltage _VGS and the body-source voltage _VBS are fixed during the first time interval, as are the parasitic transistor capacitors. The voltage jump due to charge injection is therefore dependent on the input voltage _Vin . This allows, for example, the design of switched capacitor systems without delaying the clock.

图4示出确定电路301的可能实施。以以下方式设计在图4中所示的确定电路301，即当时钟信号φ变高时确定较低电压V_low。而且，当反向时钟信号φ为高时，晶体管MN7和MN8保持确定电路301的输出端子outn和outp为地电势V_SS。这确保两个传输栅极TG1和TG2打开。交叉耦合晶体管MP3、MP4、MN9和MN10再生在确定电路301的输入端子inp和inn之间的电压差。FIG. 4 shows a possible implementation of the determination circuit 301 . The determination circuit 301 shown in FIG. 4 is designed in such a way that the lower voltage V _low is determined when the clock signal φ goes high. Also, when the inverted clock signal φ is high, the transistors MN7 and MN8 maintain the output terminals outn and outp of the determination circuit 301 at the ground potential V _SS . This ensures that the two transfer gates TG1 and TG2 are turned on. The cross-coupled transistors MP3 , MP4 , MN9 and MN10 regenerate the voltage difference between the input terminals inp and inn of the determination circuit 301 .

参考图5，示出电路500的框图，其用作本发明第三方面的示范性实施例。电路500包括晶体管MSA、电压生成器501和控制电路502。Referring to Figure 5, there is shown a block diagram of a circuit 500, which serves as an exemplary embodiment of the third aspect of the present invention. The circuit 500 includes a transistor MSA, a voltage generator 501 and a control circuit 502 .

晶体管MSA包括场效应晶体管开关且当开关接通、即晶体管MSA的沟道导通时在其第一端子接收输入电压V_in并在其第二端子提供输出电压V_out。晶体管MSA的沟道可以是n掺杂的或p掺杂的。Transistor MSA comprises a field effect transistor switch and receives an input voltage V _in at its first terminal and provides an output voltage V _out at its second terminal when the switch is on, ie the channel of transistor MSA is conducting. The channel of transistor MSA can be n-doped or p-doped.

例如，晶体管MSA可包括离散时间模拟采样电路的部分，其对输入电压V_in采样用以将模拟信号转换成数字值。For example, transistor MSA may comprise part of a discrete-time analog sampling circuit that samples the input voltage _Vin for converting the analog signal into a digital value.

电压生成器501包括输入端子，该输入端子连接到晶体管MSA的第一端子。电压生成器501的输出端子被接线到控制电路502的输入端子。控制电路502的输出端子连接到晶体管MSA的栅极端子。The voltage generator 501 comprises an input terminal connected to the first terminal of the transistor MSA. The output terminal of the voltage generator 501 is wired to the input terminal of the control circuit 502 . The output terminal of the control circuit 502 is connected to the gate terminal of the transistor MSA.

电压生成器501通过向输入电压V_in添加预定电压来生成和电压并通过从输入电压V_in减去预定电压来生成差电压。例如预定电压可以是供应电压V_dd。在这种情况下，电压生成器501产生和电压(V_in+V_dd)和差电压(V_in-V_dd)。控制电路502在第一时间间隔期间向晶体管MSA的栅极端子施加和电压且在第二时间间隔期间向晶体管MSA的栅极端子施加差电压。The voltage generator 501 generates a sum voltage by adding a predetermined voltage to the input voltage _Vin and generates a difference voltage by subtracting the predetermined voltage from the input voltage _Vin . For example the predetermined voltage may be the supply voltage V _dd . In this case, the voltage generator 501 generates a sum voltage (V _in +V _dd ) and a difference voltage (V _in −V _dd ). Control circuit 502 applies the sum voltage to the gate terminal of transistor MSA during a first time interval and applies the difference voltage to the gate terminal of transistor MSA during a second time interval.

如果晶体管MSA的沟道是n掺杂的，则晶体管MSA在第一时间间隔期间导通并在第二时间间隔期间不导通。如果晶体管MSA的沟道是p掺杂的，则晶体管MSA在第一时间间隔期间不导通并在第二时间间隔期间导通。If the channel of transistor MSA is n-doped, transistor MSA is conducting during the first time interval and is not conducting during the second time interval. If the channel of transistor MSA is p-doped, transistor MSA is not conducting during the first time interval and is conducting during the second time interval.

当在第一时间间隔和第二时间间隔期间比较晶体管MSA的栅极电压时，存在等于两倍预定电压(例如2·V_dd)的栅极电压差。因为该电压差不依赖于输入电压V_in，所以方程(4)也不依赖于输入电压V_in(由于V_G，off-V_G，on＝2·V_dd)。因此电路500的时钟馈通导致不依赖于输入电压V_in的电压跳跃。When comparing the gate voltage of transistor MSA during the first time interval and the second time interval, there is a gate voltage difference equal to twice the predetermined voltage (eg 2·V _dd ). Since this voltage difference does not depend on the input voltage _Vin , equation (4) also does not depend on the input voltage _Vin (since V _G,off - V _G,on = 2·V _dd ). The clock feedthrough of circuit 500 thus results in a voltage jump that is independent of the input voltage _Vin .

在图6中，示出电路600的框图，其是在图5中示出的电路500的变型。电路600的电压生成器601连接到晶体管MSA的输出端子，而不是连接到晶体管MSA的输入端子。电压生成器601的功能是通过向输出电压V_out添加预定电压来生成和电压以及通过从输出电压V_out减去预定电压来生成差电压。例如，预定电压可以是供应电压V_dd。在这种情况下，电压生成器601产生和电压(V_out+V_dd)和差电压(V_out-V_dd)。耦合到电压生成器601的控制电路602在第一时间间隔期间向晶体管MSA的栅极端子施加和电压并在第二时间间隔期间向晶体管MSA的栅极端子施加差电压。In FIG. 6 , a block diagram of a circuit 600 is shown, which is a variant of the circuit 500 shown in FIG. 5 . The voltage generator 601 of the circuit 600 is connected to the output terminal of the transistor MSA, rather than to the input terminal of the transistor MSA. The function of the voltage generator 601 is to generate a sum voltage by adding a predetermined voltage to the output voltage V _out and to generate a difference voltage by subtracting the predetermined voltage from the output voltage V _out . For example, the predetermined voltage may be a supply voltage V _dd . In this case, the voltage generator 601 generates a sum voltage (V _out +V _dd ) and a difference voltage (V _out −V _dd ). Control circuit 602 coupled to voltage generator 601 applies a sum voltage to the gate terminal of transistor MSA during a first time interval and a difference voltage to the gate terminal of transistor MSA during a second time interval.

在图7中，示出电路700的框图，其是电路500和600的组合。在电路700中，晶体管MSA的输入端子和输出端子都连接到电压生成器701。电压生成器701可以通过向输入电压V_in或输出电压V_out添加预定电压来生成和电压以及可以通过从输入电压V_in或输出电压V_out减去预定电压来生成差电压。控制电路702耦合到电压生成器701和晶体管MSA的栅极端子，在第一和第二时间间隔期间向晶体管MSA的栅极施加所生成的和与差电压。在预定电压是供应电压V_dd的情况下，下面的组合是可能的：In FIG. 7 , a block diagram of circuit 700 is shown, which is a combination of circuits 500 and 600 . In the circuit 700 , both the input terminal and the output terminal of the transistor MSA are connected to a voltage generator 701 . The voltage generator 701 may generate a sum voltage by adding a predetermined voltage to the input voltage _Vin or the output voltage V _out and may generate a difference voltage by subtracting the predetermined voltage from the input voltage _Vin or the output voltage V _out . The control circuit 702 is coupled to the voltage generator 701 and to the gate terminal of the transistor MSA, applying the generated sum and difference voltages to the gate of the transistor MSA during the first and second time intervals. In case the predetermined voltage is the supply voltage _Vdd , the following combinations are possible:

组合1：第一时间间隔：V_in+V_dd；第二时间间隔：V_in-V_dd。Combination 1: first time interval: V _in +V _dd ; second time interval: V _in −V _dd .

组合2：第一时间间隔：V_in+V_dd；第二时间间隔：V_out-V_dd。Combination 2: first time interval: V _in +V _dd ; second time interval: V _out −V _dd .

组合3：第一时间间隔：V_out+V_dd；第二时间间隔：V_in-V_dd。Combination 3: first time interval: V _out +V _dd ; second time interval: V _in −V _dd .

组合4：第一时间间隔：V_out+V_dd；第二时间间隔：V_out-V_dd。Combination 4: first time interval: V _out +V _dd ; second time interval: V _out −V _dd .

可以规定，控制电路702在以上为每个时间间隔所列出的四种组合中选择适当的组合，其中供应电压V_dd可由任何预定的电压代替。例如，由于下述原因，第二组合优于第一组合。晶体管MSA的栅漏极电容C_GD可导致向输出端子的栅极信号馈通。这样，当在第二时间间隔期间使用升高的输入电压V_in时，输入信号将被馈通到输出电压V_out(减少到C_GD/(C_GD+C_sample))。当使用输出电压V_out的降低了的形式时，这种效应可能消失。It may be provided that the control circuit 702 selects an appropriate combination among the four combinations listed above for each time interval, wherein the supply voltage V _dd may be replaced by any predetermined voltage. For example, the second combination is superior to the first combination for the reasons described below. The gate-to-drain capacitance C _GD of transistor MSA may cause a gate signal feedthrough to the output terminal. Thus, when using the increased input voltage V _in during the second time interval, the input signal will be fed through to the output voltage V _out (reduced to C _GD /(C _GD +C _sample )). This effect may disappear when using a reduced version of the output voltage _Vout .

在图8中，示出电路800的框图，其用作本发明第三方面的另一示范性实施例。在电路800中，晶体管MSA的沟道是n掺杂的。如图3所示，时钟信号φ和反向时钟信号φ确定开关的状态。在第一时间间隔期间，时钟信号φ为高(反向时钟信号φ为低)且开关闭合意味着晶体管MSA的源漏极路径导通。在第二时间间隔期间，时钟信号φ为低(反向时钟信号φ为高)且开关打开意味着晶体管MSA的源漏极路径不导通。In Fig. 8, a block diagram of a circuit 800 is shown, which serves as a further exemplary embodiment of the third aspect of the invention. In circuit 800, the channel of transistor MSA is n-doped. As shown in Figure 3, the clock signal φ and the inverted clock signal φ determine the state of the switch. During the first time interval, the clock signal φ is high (the inverted clock signal φ is low) and the switch is closed meaning that the source-drain path of transistor MSA is conducting. During the second time interval, clock signal φ is low (inverted clock signal φ is high) and the switch is open meaning that the source-drain path of transistor MSA is non-conductive.

在第二时间间隔期间，晶体管Mt4和Mt5闭合且将电容器C2充电到供应电压V_dd。晶体管Mb1将输入电压V_in传递给电容器C3用以将电容器C3充电到-V_dd。晶体管Mb6闭合晶体管Mb2，降低晶体管Mb3的漏极到(V_in-V_dd)。因此，晶体管Mb2闭合，使晶体管MSA的栅极为(V_in-V_dd)，这打开开关。During the second time interval, transistors Mt4 and Mt5 are closed and charge capacitor C2 to supply voltage _Vdd . The transistor Mb1 transfers the input voltage V _in to the capacitor C3 for charging the capacitor C3 to -V _dd . Transistor Mb6 closes transistor Mb2, lowering the drain of transistor Mb3 to (V _in −V _dd ). Thus, transistor Mb2 closes, leaving the gate of transistor MSA at (V _in −V _dd ), which opens the switch.

在第一时间间隔期间，运行被翻转。现在电容器C3被重新充电到-V_dd，而晶体管Mt1和Mt6闭合，闭合晶体管Mt2。这使电容器C2的底部节点为(V_in+V_dd)。晶体管Mt2传输该电压并闭合晶体管Mt3。这使晶体管MSA的栅极为(V_in+V_dd)，这闭合开关。During the first time interval, the run is reversed. Capacitor C3 is now recharged to _-Vdd , and transistors Mt1 and Mt6 are closed, closing transistor Mt2. This makes the bottom node of capacitor C2 to be (V _in +V _dd ). Transistor Mt2 delivers this voltage and closes transistor Mt3. This puts the gate of transistor MSA at (V _in +V _dd ), which closes the switch.

因此，在第一和第二时间间隔期间晶体管MSA的栅极电压差是2·V_dd且不依赖于输入电压V_in。因此时钟馈通的效应不依赖于输入电压V_in。Therefore, the gate voltage difference of transistor MSA during the first and second time interval is 2·V _dd and is independent of the input voltage V _in . The effect of clock feedthrough is therefore not dependent on the input voltage _Vin .

使用晶体管Mt3和Mb3用以确保晶体管Mt2和Mb2的栅漏极电压V_GD不超过供应电压V_dd。Transistors Mt3 and Mb3 are used to ensure that the gate-drain voltage V _GD of transistors Mt2 and Mb2 does not exceed the supply voltage V _dd .

由时钟信号φ_bo驱动晶体管Mt5，该时钟信号是随供应电压V_dd升高的反向时钟信号φ。晶体管Mb5由时钟信号φ_ab驱动，该时钟信号是随供应电压V_dd降低的反向时钟信号φ。Transistor Mt5 is driven by a clock signal _φbo , which is an inverted clock signal φ that rises with supply voltage _Vdd . Transistor Mb5 is driven by a clock signal _φab , which is an inverted clock signal φ that decreases with supply voltage _Vdd .

根据本发明的一个实施例，电路100、200、300、500、600、700或800的晶体管是金属氧化物半导体(MOS)晶体管并且以CMOS技术实现。According to one embodiment of the invention, the transistors of the circuit 100, 200, 300, 500, 600, 700 or 800 are metal oxide semiconductor (MOS) transistors and are implemented in CMOS technology.

本发明的所有三个方面能以任何方式予以组合，在图1至8中示了所述三个方面的示范性实施例。例如，第一和第三方面可通过在第一时间间隔期间利用电压(V_low+V_dd)并且在第二时间间隔期间利用电压(V_low-V_dd)来驱动n型晶体管MSA被组合。在p型晶体管MSA的情况下，在第一时间间隔期间将施加电压(V_high-V_dd)并且在第二时间间隔期间施加电压(V_high+V_dd)。All three aspects of the invention, exemplary embodiments of which are shown in FIGS. 1 to 8 , can be combined in any way. For example, the first and third aspects may be combined by driving the n-type transistor MSA with a voltage (V _low +V _dd ) during a first time interval and with a voltage (V _low −V _dd ) during a second time interval. In the case of p-type transistor MSA, the voltage (V _high -V _dd ) will be applied during the first time interval and the voltage (V _high +V _dd ) will be applied during the second time interval.

另外，虽然可以仅针对几种实施中的一个公开了本发明实施例的特定特征或方面，但是如所希望的，这种特征或方面可以与其他实施的一个或多个其他特征和方面结合并且对任何给定或特定应用是有利的。而且，在一定程度上，在详述的说明书或权利要求书中使用术语“包括”、“具有”、“带有”或其变型，这些术语用来表示以与术语“包含”相似的方式来包括。术语“被耦合”和“被连接”可与派生词一起使用。应该理解的是，这些术语可被用来表明两个元件共同运行或彼此交互作用，无论它们是处于直接物理或电接触，还是它们并非彼此直接接触。而且，应该理解的是，本发明的实施例可以在离散电路、部分集成电路或完全集成电路或编程装置中实现。同样，术语“示范性”仅表示作为例子，而不是最好的或最佳的。还应该理解的是，为了简化和易于理解，这里描述的特征和/或元件利相对于彼此特定的尺寸来示出，并且实际尺寸实质上可不同于这里示出的尺寸。In addition, although a particular feature or aspect of an embodiment of the invention may be disclosed with respect to only one of several implementations, such a feature or aspect can be combined with one or more other features and aspects of other implementations and is advantageous for any given or particular application. Moreover, to the extent that the terms "comprise", "have", "with" or variations thereof are used in the detailed description or claims, these terms are intended to mean include. The terms "coupled" and "connected" may be used with derivatives. It should be understood that these terms may be used to indicate that two elements co-operate or interact with each other, whether they are in direct physical or electrical contact, or they are not in direct contact with each other. Furthermore, it should be understood that embodiments of the invention may be implemented in discrete circuits, partially or fully integrated circuits or programmed means. Also, the term "exemplary" means an example only, not the best or best. It should also be understood that for simplicity and ease of understanding, features and/or elements described herein may be shown with specific dimensions relative to each other and that actual dimensions may differ substantially from those shown herein.

Claims

1, a kind of circuit comprises:

N type switch with field-effect transistors comprises the first terminal that receives input voltage, second terminal and the gate terminal of output output voltage;

Determine circuit, be coupled to the first terminal and second terminal of transistor switch, determine the low voltage between input voltage and the output voltage;

Voltage generator is coupled to definite circuit, generates and voltage by add first predetermined voltage to low voltage; And

Control circuit is coupled to the gate terminal of voltage generator and transistor switch, and the gate terminal in the interim very first time to transistor switch applies and voltage.

2, the circuit of claim 1, wherein transistor switch is in interim very first time closure.

3, the circuit of claim 1, wherein first predetermined voltage is from supply voltage.

4, the circuit of claim 1, wherein second predetermined voltage is applied to the gate terminal of transistor switch during second time interval.

5, the circuit of claim 4, wherein transistor switch was opened during second time interval.

6, the circuit of claim 4, wherein when transistor switch comprised n type field-effect transistor, second predetermined voltage comprises earth potential and when transistor switch comprised p type field-effect transistor, second predetermined voltage comprised supply voltage.

7, the circuit of claim 1 further comprises capacitor, and described capacitor is charged to first predetermined voltage during second time interval.

8, the circuit of claim 7, wherein low voltage is applied to the first terminal of capacitor, and in the interim very first time, second terminal of capacitor is coupled to the gate terminal of transistor switch.

9, the circuit of claim 1, wherein transistor switch comprises the body terminal, and the interim very first time low voltage be applied to the body terminal.

10, a kind of circuit comprises:

P type switch with field-effect transistors comprises the first terminal that receives input voltage, second terminal and the gate terminal of output output voltage;

Determine circuit, be coupled to the first terminal and second terminal of transistor switch, determine the high voltage between input voltage and the output voltage;

Voltage generator is coupled to definite circuit, generates potential difference by deduct first predetermined voltage from high voltage; And

Control circuit is coupled to the gate terminal of voltage generator and transistor switch, applies potential difference in the interim very first time to the gate terminal of transistor switch.

11, the circuit of claim 10, wherein transistor switch comprises the body terminal, and the interim very first time high voltage be applied to the body terminal.

12, a kind of circuit comprises:

N type switch with field-effect transistors comprises the first terminal that receives input voltage, second terminal and the body terminal of output output voltage;

Determine circuit, be coupled to the first terminal and second terminal of transistor switch, determine the low voltage between input voltage and the output voltage; And

Control circuit is coupled to the body terminal of determining circuit and transistor switch, the interim very first time to the body terminal of transistor switch apply low voltage or and voltage, described and voltage is predetermined voltage and low voltage sum.

13, the circuit of claim 12, wherein transistor switch is in interim very first time closure.

14, the circuit of claim 12, wherein first predetermined voltage is from supply voltage.

15, the circuit of claim 12, wherein second predetermined voltage is applied to the body terminal of transistor switch during second time interval.

16, the circuit of claim 15, wherein transistor switch was opened during second time interval.

17, the circuit of claim 15, wherein when transistor switch comprised n type field-effect transistor, second predetermined voltage comprises earth potential and when transistor switch comprised p type field-effect transistor, second predetermined voltage comprised supply voltage.

18, the circuit of claim 12, wherein transistor switch comprises the triple-well transistor.

19, a kind of circuit comprises:

P type switch with field-effect transistors comprises the first terminal that receives input voltage, second terminal and the body terminal of output output voltage;

Determine circuit, be coupled to the first terminal and second terminal of transistor switch, determine the high voltage between input voltage and the output voltage; With

Control circuit is coupled to the body terminal of determining circuit and transistor switch, the interim very first time to the body terminal of transistor switch apply high voltage or and voltage, described and voltage is predetermined voltage and high voltage sum.

20, a kind of circuit comprises:

Switch with field-effect transistors comprises the first terminal that receives input voltage, second terminal and the gate terminal of output output voltage;

Voltage generator is coupled to the first terminal or second terminal of transistor switch, generates with voltage and by deducting predetermined voltage from input voltage or output voltage and generates potential difference by add predetermined voltage to input voltage or output voltage; And

Control circuit is coupled to the gate terminal of voltage generator and transistor switch, the interim very first time to the gate terminal of transistor switch apply with voltage and during second time interval gate terminal to transistor switch apply potential difference.

21, the circuit of claim 20, wherein when transistor switch comprises n transistor npn npn switch, transistor switch closes in the interim very first time and opens during being incorporated in for second time interval.

22, the circuit of claim 20, wherein when transistor switch comprised p transistor npn npn switch, transistor switch was opened and closure during second time interval in the interim very first time.

23, the circuit of claim 20, wherein predetermined voltage is from supply voltage.

24, the circuit of claim 20 further comprises first capacitor, and described first capacitor is charged to predetermined voltage during second time interval.

25, the circuit of claim 24, wherein input voltage or output voltage are applied to the first terminal of first capacitor, and interim first very first time capacitor second terminal be coupled to the gate terminal of transistor switch.

26, the circuit of claim 20 further comprises second capacitor, and described second capacitor is charged to negative predetermined voltage in the interim very first time.

27, the circuit of claim 26, wherein input voltage or output voltage are applied to the first terminal of second capacitor, and second terminal of second capacitor is coupled to the gate terminal of transistor switch during second time interval.

28, a kind of analog to digital converter comprises a kind of circuit, and described circuit comprises:

Voltage generator is coupled to definite circuit, generates and voltage by adding predetermined voltage to low voltage; And

29, a kind of method comprises:

N type switch with field-effect transistors is provided, and described n type switch with field-effect transistors comprises the first terminal, second terminal and gate terminal, wherein input voltage is applied to the first terminal and output voltage is exported at output voltage;

Determine the low voltage between input voltage and the output voltage;

Generate and voltage by add first predetermined voltage to low voltage; And

Gate terminal in from the interim very first time to transistor switch applies and voltage.

30, a kind of method comprises:

P type switch with field-effect transistors is provided, and described p type switch with field-effect transistors comprises the first terminal, second terminal and gate terminal, wherein input voltage is applied to the first terminal and output voltage is exported at output voltage;

Determine the high voltage between input voltage and the output voltage;

Generate potential difference by deduct first predetermined voltage from high voltage; And

Apply potential difference in the interim very first time to the gate terminal of transistor switch.

31, a kind of method comprises:

N type switch with field-effect transistors is provided, and described n type switch with field-effect transistors comprises the first terminal, second terminal and body terminal, wherein input voltage is applied to the first terminal and output voltage is exported at output voltage;

Determine the low voltage between input voltage and the output voltage; And

The interim very first time to the body terminal of transistor switch apply low voltage or and voltage, described and voltage is predetermined voltage and low voltage sum.

32, a kind of method comprises:

P type switch with field-effect transistors is provided, and described p type switch with field-effect transistors comprises the first terminal, second terminal and body terminal, wherein input voltage is applied to the first terminal and output voltage is exported at output voltage;

Determine the high voltage between input voltage and the output voltage; And

The interim very first time to the body terminal of transistor switch apply high voltage or and voltage, described and voltage is predetermined voltage and high voltage sum.

33, a kind of method comprises:

Switch with field-effect transistors is provided, and described switch with field-effect transistors comprises the first terminal, second terminal and gate terminal, wherein input voltage is applied to the first terminal and output voltage is exported at output voltage;

By adding predetermined voltage and generate with voltage and by deducting predetermined voltage and generate potential difference from inputing or outputing voltage to inputing or outputing voltage; And

The interim very first time to transistorized gate terminal apply with voltage and during second time interval gate terminal to transistor switch apply potential difference.

34, a kind of equipment comprises:

N type switch with field-effect transistors comprises the first terminal, second terminal and gate terminal, wherein input voltage is applied to the first terminal and output voltage is exported this equipment at output voltage;

Be used for determining the device of the low voltage between input voltage and the output voltage;

Be used for generating device with voltage by add first predetermined voltage to low voltage; And

Be used for applying device with voltage to the gate terminal of transistor switch in the interim very first time.

35, a kind of equipment comprises:

P type switch with field-effect transistors comprises the first terminal, second terminal and gate terminal, wherein input voltage is applied to the first terminal and output voltage is exported at output voltage;

Be used for determining the device of the high voltage between input voltage and the output voltage;

Be used for by deduct the device that first predetermined voltage generates potential difference from high voltage; And

Be used for applying to the gate terminal of transistor switch the device of potential difference in the interim very first time.

36, a kind of equipment comprises:

N type switch with field-effect transistors comprises the first terminal, second terminal and body terminal, wherein input voltage is applied to the first terminal and output voltage is exported at output voltage;

Be used for determining the device of the low voltage between input voltage and the output voltage; And

Be used for the interim very first time to the body terminal of transistor switch apply low voltage or and the device of voltage, described and voltage is predetermined voltage and low voltage sum.

37, a kind of equipment comprises:

P type switch with field-effect transistors comprises the first terminal, second terminal and body terminal, wherein input voltage is applied to the first terminal and output voltage is exported at output voltage;

Be used for determining the device of the high voltage between input voltage and the output voltage; And

Be used for the interim very first time to the body terminal of transistor switch apply high voltage or and the device of voltage, described and voltage is predetermined voltage and high voltage sum.

38, a kind of equipment comprises:

Switch with field-effect transistors comprises the first terminal, second terminal and gate terminal, wherein input voltage is applied to the first terminal and output voltage is exported at output voltage;

Be used for by generating with voltage and by deducting the device that predetermined voltage generates potential difference from inputing or outputing voltage to inputing or outputing voltage interpolation predetermined voltage; And

Be used for applying and voltage and the device that during second time interval, applies potential difference to the gate terminal of transistor switch to the gate terminal of transistor switch in the interim very first time.