CN101252111B - Chip packaging structure and manufacturing method thereof - Google Patents

Abstract

A chip package structure and a method for manufacturing the same are provided. The chip packaging structure comprises a packaging piece and a plurality of outer guide blocks. The packaging piece comprises a wiring layer, a chip, a plurality of inner guide blocks and a sealing colloid. The wiring layer is provided with a first surface and a second surface, and the chip is arranged on the first surface. The inner guide block is provided with a first end and a second end, and the first end is arranged on the first surface. The sealing colloid is arranged on the first surface and used for covering the chip and partially sealing the inner guide block, so that the first end and the second end of the inner guide block are exposed outside the sealing colloid. The outer guide block is arranged on the second surface of the wiring layer of the packaging piece and is electrically connected with the inner guide block.

Description

Chip package structure and manufacturing method thereof

【Technical field】

The present invention relates to a packaging structure and its manufacturing method, and in particular to a chip packaging structure and its manufacturing method.

【Background technique】

In recent years, electronic devices have been vigorously used in daily life, and the industry is all committed to developing miniature and multi-functional electronic products to meet market demands. Wafer Level Chip Scale Package (WLCSP) is a commonly used packaging structure for semiconductor components of electronic products.

Please refer to FIG. 1 , which shows a schematic diagram of a conventional chip package. The package 10 includes a wiring layer 20 , an encapsulant 30 , an insulating layer 40 , a chip 50 , a plurality of inner wires 70 and a plurality of solder balls 90 . The encapsulant 30 encloses the insulating layer 40 , the chip 50 and the inner wire 70 therein. The encapsulant 30 is disposed on one side of the wiring layer 20 , and the solder ball 90 is disposed on the other side of the wiring layer 20 . The insulating layer 40 is located between the wiring layer 20 and the chip 50 . One end of the inner wire 70 is disposed on the chip 50 , and the other end of the inner wire 70 is connected to the wiring layer 20 . The chip 50 is electrically connected to the solder ball 90 through the wiring layer 20 through the inner wire 70 .

The package 10 is limited by the shape condition of the inner wire 70 , so that a thickness H30 of the encapsulant 30 is much larger than a thickness H50 of the chip 50 . Therefore, the volume of the package 10 is increased, thereby limiting the miniaturization of the electronic device. In addition, in a multifunctional electronic device, it is necessary to combine multiple chips. Therefore, providing a package with increased packaging density and its manufacturing method is one of the research directions of the industry.

【Content of invention】

The invention relates to a chip packaging structure and a manufacturing method thereof. The inner guide block and its corresponding outer guide block are designed to reduce the required thickness of the encapsulant of the package, thereby increasing the density of the package structure.

According to one aspect of the present invention, a chip packaging structure is provided, including a package and a plurality of outer lead blocks. The package includes a wiring layer, a chip, multiple inner guide blocks and encapsulant. The wiring layer has a first surface and a second surface, and the chip is arranged on the first surface of the wiring layer. The inner guide block has a first end and a second end, and the first end is disposed on the first surface of the wiring layer. The encapsulant is disposed on the first surface of the wiring layer to cover the chip and partially enclose the inner lead block, so that the first end and the second end of the inner lead block are exposed outside the encapsulant. The outer lead block is disposed on the second surface of the wiring layer of the package, and is electrically connected with the inner lead block.

According to another aspect of the present invention, a method for manufacturing a chip packaging structure is provided. The manufacturing method includes the following steps: firstly, a carrier with an adhesive layer is provided. Furthermore, a plurality of inner guide blocks and at least one chip are arranged on the adhesive layer, wherein the inner guide block has a first end and a second end, and the first end is arranged on the adhesive layer. Next, form an encapsulant on the adhesive layer to cover the chip and the inner guide block. Then, the adhesive layer is removed to expose the first end of the inner lead block, an active surface of the chip and a bottom surface of the encapsulant. In addition, a wiring layer is formed on the bottom surface of the sealing compound, so that the first end of the inner lead block and the active surface of the chip are arranged on a first surface of the wiring layer, and the wiring layer is electrically connected to form a package. The components include a chip, an inner guide block corresponding to the chip, a wiring layer and a sealant. Finally, a plurality of outer lead blocks are arranged on a second surface of the wiring layer.

In order to make the above content of the present invention more obvious and understandable, the following preferred embodiments are specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

【Description of drawings】

FIG. 1 (Prior Art) shows a schematic diagram of a conventional chip package.

FIG. 2 is a schematic diagram of a chip packaging structure according to a first embodiment of the present invention.

3A to 3M are schematic diagrams illustrating a manufacturing method of the chip package structure in FIG. 2 .

FIG. 4 is a flowchart of a manufacturing method of the chip package structure in FIG. 2 .

FIG. 5 is a schematic diagram of stacking two identical packages.

FIG. 6 is a schematic diagram of two different package stacks.

7A to 7L are schematic diagrams illustrating a method for manufacturing a chip package structure according to a second embodiment of the present invention.

【Detailed ways】

first embodiment

Please refer to FIG. 2 , which shows a schematic diagram of a chip packaging structure according to a first embodiment of the present invention. The chip package structure includes a first package 100 and a plurality of first outer leads 130 . The first package 100 includes a wiring layer 110 , a chip 150 , a plurality of inner leads 170 and an encapsulant 190 .

The wiring layer 110 has a first surface 111 and a second surface 113 . The chip 150 is disposed on the first surface 111 of the wiring layer 110 . The inner guide block 170 has a first end 171 and a second end 273 , and the first end 171 is disposed on the first surface 111 of the wiring layer 110 . The encapsulant 190 is disposed on the first surface 111 of the wiring layer 110 to cover the chip 150 and partially encapsulate the inner lead block 170 , so that the first end 171 and the second end 273 of the inner lead block 170 are exposed outside the encapsulant 190 . The first outer lead block 130 is disposed on the second surface 113 of the wiring layer 110 of the first package 100 and is electrically connected to the inner lead block 170 .

In addition, the first package 100 further includes another wiring layer 210 disposed on the molding compound 190 and covering the second end 273 of the inner lead block 170 . By setting the inner guide block 170 slightly larger than the thickness of the chip 150 , the required thickness of the encapsulant 190 is reduced, thereby reducing the volume of the first package 100 .

Please refer to FIGS. 3A to 3M and FIG. 4 , FIGS. 3A to 3M are diagrams illustrating a manufacturing method of the chip packaging structure of FIG. 2 , and FIG. 4 is a flow chart of the manufacturing method of the chip packaging structure of FIG. 2 .

Step 401 , as shown in FIG. 3A , provides a carrier 120 with an adhesive layer 121 . The carrier 120 may be a metal carrier, the surfaces 123 and 125 of the adhesive layer 121 are both adhesive, and the surface 123 of the adhesive layer 121 is pasted on the carrier 120 .

In step 402 and FIG. 3B , a plurality of inner guide blocks 170 and at least one chip are disposed on the surface 125 of the adhesive layer 121 . In this embodiment, the chips 150 and 151 are taken as an example, and the chip 150 and the chip 151 have substantially the same structure. The inner guide block 170 has a first end 171 and a second end 173 , and the first end 171 of the inner guide block 170 and the chips 150 , 151 are fixed on the adhesive layer 121 by bonding.

Preferably as shown in Figure 3C, a mold 220 is provided in step 403, for example, a plunger head (plunger) presses the inner guide block 170 toward a direction D of the adhesive layer 121, so that the first part of the inner guide block 170 The end 171 is embedded and fixed to the adhesive layer 121 , but the mold 220 is not in contact with the chips 150 , 151 . By pressing the inner guide block 170 into the adhesive layer 121, it can be ensured that the inner guide block 170 will not change its position due to the procedure described later.

In step 404 , as shown in FIG. 3D , a liquid sealing material 140 is coated on the adhesive layer 121 . The liquid sealing material 140 can flow on the adhesive layer 121 .

In step 405 and FIG. 3E , another mold 222 is provided to pressurize and heat the liquid encapsulant 140 (shown in FIG. 3D ), and make it solidify into the encapsulant 190 . The encapsulant 190 covers the chips 150 , 151 and the inner lead block 170 . The thickness H190 of the encapsulant 190 is substantially slightly larger than the thickness H150 of the chips 150 , 151 , so that the encapsulant 190 covers the chips 150 , 151 and partially encapsulates the inner lead block 170 . The first end 171 of the inner guide block 170 is exposed to the outside of the molding body 190 due to the insertion into the adhesive layer 121 , and the second end 173 of the inner guide block 170 is enclosed in the molding body 190 .

Afterwards, as shown in step 406 and FIG. 3F , post-mold curing is performed on the adhesive layer 121 , and the adhesive layer 121 and the sealing layer 190 are moved along a direction D1 to separate the adhesive layer 121 from the carrier 120 . Then, as shown in FIG. 3G , the encapsulant 190 is separated from the adhesive layer 121 to expose the first end 171 of the inner guide block 170, an active surface 150' of the chips 150, 151 and a bottom surface 190' of the encapsulant 190.

Step 407, as shown in Figures 3H and 3I, provides yet another grinding jig 224 to grind a top surface 191 of the encapsulant 190 until it contacts the second end 173 of the inner guide block 170, and further grinds to expose the inner guide block 170 A second end 273 with a larger area is formed to increase the stability of the subsequent electrical connection. After grinding, the thickness H191 of the encapsulant is still substantially greater than the thickness H150 of the chips 150 , 151 .

In step 408 and FIG. 3J , the encapsulant 190 is turned over so that the bottom surface 190 ′ and the active surfaces 150 ′ of the chips 150 and 151 face upward, and the wiring layer 110 is formed on the bottom surface 190 ′ of the encapsulant 190 so that the inner guide block The first end 171 of 170 and the active surface 150 ′ of the chips 150 and 151 are disposed on the first surface 111 of the wiring layer 110 and are electrically connected to the wiring layer 110 . The first end 171 of the inner lead block 170 is electrically connected to the chips 150 , 151 through the wiring layer 110 .

The wiring layer 110 includes an Under Bump Metal (UBM) 110a, a Re-Distribution Layer (RDL) 110b and a polymer layer 110c. The underlying metal 110a is in contact with the inner lead block 170 to electrically connect the redistribution layer 110b. The inner lead block 170 is also electrically connected to the chips 150 and 151 through the redistribution layer 110b. The polymer layer 110c is used for electrical isolation to avoid A short circuit has occurred. The rewiring layer 110b can be formed by sputtering, and the polymer layer 110c can be formed on the rewiring layer 110b by coating.

In step 409 and FIG. 3K , the encapsulant 190 is turned over so that the polished top surface 193 faces upward, and another wiring layer 210 is formed on the top surface 193 of the encapsulant 190 . The wiring layer 210 is electrically connected to the inner lead block 170 by being connected to the second end 273 of the inner lead block 170 . The wiring layer 210 is formed in the same way as the wiring layer 110 , so it will not be described in detail.

Next, in FIG. 3L and step 410 , the encapsulant 190 is turned over and the first outer lead block 130 is disposed on the second surface 113 of the wiring layer 110 . The first outer lead block 130 is in contact with the underlying metal 110 a or the redistribution layer 110 b, so that the first outer lead block 130 is electrically connected to the chips 150 and 151 through the inner lead block 170 and the wiring layer 110 .

After that, in FIG. 3M and step 411, the molding body 190 is turned over and the molding body 190 and the wiring layers 110, 210 are cut to form a plurality of first packages 100, 100'. The first package 100 includes a chip 150, an inner lead block 170 corresponding to the chip 150, wiring layers 110, 210, an encapsulant 190, and a first outer lead block 130. The first package 100' includes a chip 151, an inner block corresponding to the chip 151. The guide block 170 , the wiring layers 110 , 210 , the encapsulant 190 and the first outer lead block 130 .

In the chip package structure formed by the above method, the chips 150, 151 corresponding to the first package 100, 100' are electrically connected to the active surface 150' through the inner lead block 170 and the wiring layer 110, and each has an outer lead block 130 that can be set on other electronic structures.

In addition, the chip package structure of the present invention can stack multiple packages. The stacked packages can be packages with the same structure or different structures.

Please refer to FIG. 5 , which shows a schematic diagram of stacking two identical packages. The first package 100 and the first package 100' have the same structure and the same size. Connect the first outer lead block 130 corresponding to the chip 151 to the wiring layer 210 of the first package 100, so that the first package 100 and the first package 100' are electrically connected through the first outer lead block 130 to form a stack type chip packaging structure. Furthermore, when the stacked package structure is two identical packages stacked, the upper first package 100 ′ can directly connect the first outer lead block 130 to the inner lead block 170 of the lower first package 100 , and further The wiring layer 210 for forming the first package structure 100 may be omitted.

Furthermore, please refer to FIG. 6 , which shows a schematic diagram of two different package stacks. The first package 100 and the second package 300 have different sizes and structures. A plurality of second outer lead blocks 330 and the second package 300 are disposed above the wiring layer 210 of the first package 100, so that the second package 300 passes through the second outer lead blocks 330 and the second inner lead block 170. Terminal 273 is electrically connected. Furthermore, the second package 300 further includes another chip 350 encapsulated by an encapsulant 390 . The chip 350 is electrically connected to the second outer lead block 330 , and the chip 150 and the chip 350 have substantially different structures. The second outer lead block 330 contacts the wiring layer 210 and is electrically connected to the second end 273 of the inner lead block 170 through the wiring layer 210 . The chips 150 and 350 of different structures in the first package 100 and the second package 300 can be electrically connected to form a stacked chip package structure.

The chip package structure described in this embodiment can be applied to a three-dimensional (3D) divergent (Fan-Out) wafer level chip scale package (Wafer Level Chip Scale Package, WLCSP). The inner guide block 170 , the first outer guide block 130 and the second outer guide block 330 may be a plurality of solder balls. The shape and size of the inner guide block 170 are not limited, and the thickness of the inner guide block 170 encapsulated by the encapsulant 190 is preferably slightly larger than the thickness H150 of the chip 150 . The first package 100 reduces the required thickness of the encapsulant 190 by providing the inner guide block 170 , thereby reducing the volume of the first package 100 . When the chip packaging structure stacks different packages, the second package 300 is formed on the encapsulant 190 through the wiring layer 210 of the first package 100 to electrically connect the two packages, so the second outer lead 330 does not It needs to be arranged corresponding to the inner guide block 170, and the second package 300 can be a package of any shape and size, which increases the applicability of the chip package structure.

second embodiment

Please refer to FIGS. 7A to 7L , which are schematic diagrams illustrating a manufacturing method of a chip package structure according to a second embodiment of the present invention.

In FIG. 7A, a metal carrier 720 is provided with an adhesive layer 721 thereon. Surfaces 723 and 725 of the adhesive layer 721 are adhesive, and the surface 723 of the adhesive layer 721 is attached to the metal carrier 720 .

As shown in FIG. 7B , a plurality of inner guide blocks 770 and at least one chip are disposed on the surface 725 of the adhesive layer 721 . Taking the chips 750 and 751 as examples, the chips 750 and 751 have substantially the same structure. The inner guide block 770 is respectively disposed on two sides of the chip 750 , 751 , the inner guide block 770 has a first end 771 and a second end 773 , and the first end 771 is disposed on the adhesive layer 721 .

After that, as shown in FIG. 7C , a plunger head 722 is provided to press the inner guide block 770 toward the direction D of the adhesive layer 721 , so that the first end 771 of the inner guide block 770 is embedded and fixed in the adhesive layer 721 . The plunger tip 722 does not contact the chips 750,751.

In FIG. 7D , a liquid sealing material 740 is coated on the adhesive layer 721 and a mold 724 is provided. The liquid sealing material 740 can flow on the adhesive layer 721 . The mold 724 has a further adhesive layer 727 .

After that, as shown in FIG. 7E , the mold 724 is used to squeeze and heat the liquid sealing material 740 (shown in FIG. 7D ), so that the second end 773 of the inner guide block 770 is embedded in the adhesive layer 727 . The first end 771 of the inner guide block 770 can also be embedded into the adhesive layer 721 at the same time. The liquid encapsulant 740 is extruded, heated and solidified to form an encapsulant 790 to cover the chips 750 , 751 and the inner guide block 770 . A thickness H790 of the encapsulant 790 is substantially slightly larger than a thickness H750 of the chips 750 and 751 , so that the encapsulant 790 covers the chips 750 and 751 and partially encapsulates the inner lead block 770 . The first end 771 and the second end 773 of the inner guide block 770 are exposed outside the molding compound 790 .

In FIG. 7F , post-stage heat treatment is performed on the adhesive layer 721 , and the adhesive layer 721 and the sealant layer 790 are moved along the direction D1 to separate the adhesive layer 721 from the metal carrier 720 . The adhesive layer 727 is removed together with the mold 724 to expose the second end 773 of the inner guide block 770 .

Next, in FIG. 7G , the adhesive layer 721 is removed to expose the first end 771 of the inner lead block 770, an active surface 750' of the chips 750, 751, and a bottom surface 790' of the encapsulant 790.

Afterwards, as shown in FIG. 7H , the encapsulant 790 is turned over so that the bottom surface 790 ′ and the active surfaces 750 ′ of the chips 750 and 751 face upward, and a wiring layer 710 is formed on the bottom surface 790 ′ of the encapsulant 790 so that the inner guide block The first end 771 of 770 and the chips 750 and 751 are disposed on a first surface 711 of the wiring layer 710 and are electrically connected to the wiring layer 710 . The inner lead blocks 770 on both sides of the chips 750 and 751 are electrically connected to the corresponding chips 750 and 751 respectively by connecting the first ends 771 to the wiring layer 110 .

In FIG. 7I , the encapsulant 790 is turned over so that a top surface 793 faces upward, and another wiring layer 715 is formed on the top surface 793 of the encapsulant 790 . The wiring layer 715 is electrically connected to the inner lead block 770 and the chips 750 , 751 by connecting with the second end 773 of the inner lead block 770 .

Next, as shown in FIG. 7J , the sealant layer 790 is turned over so that the wiring layer 710 faces upward, and a plurality of first outer lead blocks 730 are disposed on a second surface 713 of the wiring layer 710 . The first outer lead block 730 is electrically connected to the chips 750 and 751 through the inner lead block 770 and the wiring layer 710 .

After that, in FIG. 7K, the encapsulant 790 and the wiring layers 710, 715 are cut to form a plurality of first packages 950, 950'. The first package 950 includes a chip 750 and an inner lead block and a first outer lead block corresponding to the chip 750 . The first package 950' includes a chip 751 and an inner lead block corresponding to the chip 751 and a first outer lead block.

As shown in FIG. 7L, the first package 950' is disposed on the first package 950 to form a stacked chip package structure.

In the chip packaging structure described in this embodiment, the second end 773 of the inner guide block 770 is embedded in the adhesive layer 727 . After the adhesive layer 727 is removed, the first end 771 and the second end 773 of the inner guide block 770 are exposed to the outside of the sealing body 790 . Therefore, the chip package structure can form the wiring layers 710 and 715 without grinding, which saves grinding materials and simplifies the manufacturing method of the chip package structure.

Although the manufacturing method of the chip package structure in the above-mentioned embodiments of the present invention is described by forming two packages at a time, those with ordinary knowledge can know that the number of packages is not used to limit the present invention. The manufacturing method of the chip package structure of the present invention can form one package, three packages, ten packages or even more.

The chip package structure and manufacturing method disclosed in the above embodiments of the present invention not only reduce the required thickness of each package, but also allow different types of packages to be stacked on each other through the wiring layer. Therefore, its volume can be reduced by five to six times compared with the packaging structure of a multi-chip module (MCM). The chip packaging structure disclosed in the preferred embodiments of the present invention can be applied to flash (Flash) random access memory (Random-Access Memory, RAM), static random access memory (Static Random-Access Memory, SRAM), Dynamic Random-Access Memory (DRAM), Processor (Processor), Application Specific Integrated Circuit (ASIC) or Controller (Controller). In addition, it can test each package one by one before stacking, and can detect the characteristics of each package earlier.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

Claims (20)

1. chip-packaging structure comprises:

One first packaging part comprises:

One first wiring layer has a first surface and a second surface;

One chip is arranged at this first surface of this first wiring layer;

Guide block in a plurality of has one first end and one second end, and this first end is arranged at this first surface of this first wiring layer; And

One adhesive body is arranged at this first surface of this first wiring layer, in order to cover this chip and partly enclose described in guide block, make described in this first end and this second end of guide block be exposed to outside this adhesive body; And

The a plurality of first outer guide block is arranged at this second surface of this first wiring layer of this first packaging part, and with described in guide block electrically connect.

2. chip-packaging structure according to claim 1 is characterized in that, more comprises:

The a plurality of second outer guide block is disposed on this first packaging part; And

One second packaging part is disposed on this first packaging part, and this second packaging part electrically connects by this second end of the described second outer guide block and described interior guide block.

3. chip-packaging structure according to claim 2 is characterized in that, the described second outer guide block correspondence is connected in described interior guide block.

4. chip-packaging structure according to claim 2 is characterized in that, this first packaging part more comprises one second wiring layer, is arranged on this adhesive body, and the wherein said second outer guide block electrically connects by this second end of this second wiring layer and described interior guide block.

5. chip-packaging structure according to claim 4, it is characterized in that, this second wiring layer has a first surface and a second surface, this second end of guide block is arranged at this second surface of this second wiring layer in described, and the described second outer guide block is arranged at this first surface of this second wiring layer.

6. chip-packaging structure according to claim 1 is characterized in that, this second end of described interior guide block flushes in this adhesive body.

7. chip-packaging structure according to claim 1 is characterized in that, this second end of described interior guide block protrudes from this adhesive body.

8. chip-packaging structure according to claim 1 is characterized in that, this first end of described interior guide block protrudes from this adhesive body, and this first wiring layer covers this first end of each described interior guide block.

9. chip-packaging structure according to claim 1 is characterized in that the thickness of this adhesive body is more than or equal to the thickness of this chip.

10. the manufacture method of a chip-packaging structure comprises:

(a) provide a carrier, have an adhered layer on this carrier;

(b) a plurality of interior guide blocks of configuration and at least one chip are in this adhered layer, and wherein said interior guide block has one first end and one second end, and this first end is arranged at this adhered layer;

(c) form an adhesive body on this adhered layer, to cover this chip and described interior guide block;

(d) remove this adhered layer, to expose this first end, an active surface of this chip and a bottom surface of this adhesive body of described interior guide block;

(e) form one first wiring layer in this bottom surface of this adhesive body, so that this active surface of this first end of described interior guide block and this chip is arranged at a first surface of this first wiring layer, and electrically connect this first wiring layer, forming one first packaging part, this first packaging part comprise this chip, to should chip described in guide block, this first wiring layer and this adhesive body; And

(f) the configuration a plurality of first outer guide block is in a second surface of this first wiring layer.

11. manufacture method according to claim 10 is characterized in that, more comprises:

(g) configuration a plurality of second outer guide block and one second packaging part make this second packaging part electrically connect by this second end of the described second outer guide block and described interior guide block in the top of this first packaging part.

12. manufacture method according to claim 11 is characterized in that, more comprises:

Form the end face of one second wiring layer in this adhesive body, this second wiring layer is electrically connected to described interior guide block, and wherein in this step (g), the described second outer guide block electrically connects by this second end of this second wiring layer and described interior guide block.

13. manufacture method according to claim 10 is characterized in that, more comprises:

Form one second wiring layer in one of this adhesive body end face, this second wiring layer is electrically connected to described interior guide block.

14. manufacture method according to claim 10 is characterized in that, in this step (c) before, this method more comprises:

Towards the described interior guide block of the direction extruding of this adhered layer, make this first end of described interior guide block embed this adhered layer.

15. manufacture method according to claim 10 is characterized in that, in this step (d) afterwards, this method more comprises:

Grind an end face of this adhesive body, until expose described in this second end of guide block.

16. manufacture method according to claim 10 is characterized in that, this step (c) comprising:

(c1) coating one liquid adhesive material is in this adhered layer; And

(c2) solidifying this liquid state adhesive material is this adhesive body.

17. manufacture method according to claim 16 is characterized in that, this step (c2) comprising:

One mould is provided, and this mould has another adhered layer; And

Utilize this mould extruding and heat this liquid state adhesive material, make this second end of described interior guide block embed this another adhered layer.

18. manufacture method according to claim 17 is characterized in that, in this step (c2) afterwards, this method more comprises:

Remove this another adhered layer, to expose this second end of described interior guide block.

19. manufacture method according to claim 10 is characterized in that, in this step (f) afterwards, this method more comprises:

(h) cut this adhesive layer and this first wiring layer to form a plurality of these first packaging parts.

20. manufacture method according to claim 19 is characterized in that, this step (h) afterwards, this method more comprises:

Pile up described first packaging part, each described first packaging part electrically connects by the corresponding part described first outer guide block.

Images