CN101246670B - Serial data transmission method for display device and related device thereof - Google Patents

Abstract

In order to solve the problem of signal reflection of the transmission interface in the display and reduce the cost, the present invention provides a serial data transmission method for embedding data and non-data signals (such as clock, synchronization signal, etc.) into the data transmission line of the display device. The data transmission method comprises the following steps: acquiring a plurality of data transmission modes of the display device; defining a plurality of current combinations according to the data transmission modes and with a plurality of current magnitudes and a plurality of current directions, wherein each current combination corresponds to one data transmission mode; and outputting corresponding current combinations to the electronic device of the display device through a plurality of transmission lines according to the current data transmission mode.

Description

Serial data transmission method for display device and related device

technical field

The present invention relates to a data transmission method and its related device, especially to a serial data transmission method and its related device which can embed data and non-data signals in a data transmission line for a display device.

Background technique

Liquid crystal display (liquid crystal display) is a light and thin flat panel display device (flat panel display), which has the advantages of low radiation, small size and low energy consumption, and has gradually replaced the traditional cathode ray tube display (cathode ray tube display) display), and thus are widely used in information products such as notebook computers (notebook computers), personal digital assistants (personal digital assistants, PDAs), flat-screen TVs, or mobile phones. Common flat panel displays include thin film transistor (thin film transistor, TFT) liquid crystal display, low temperature polysilicon (low temperature poly silicon, LTPS) liquid crystal display, and organic light emitting diode (organic light emitting diode, OLED) display. The driving system of the display is composed of a timing controller, multiple source drivers and multiple gate drivers. The interface between the timing controller and the source driver is a bus type (bus type) to transmit clock signals, data signals, control signals and setting signals, etc., and its common connection interface includes transistor-transistor logic (transistor-transistor logic) , TTL) interface, low voltage differential signal (LVDS) interface, low swing differential signal (reduced swing differential signal, RSDS) and micro low voltage differential signal (mini low voltage differential signal, mini- LVDS) interface, etc.

Please refer to FIG. 1 and FIG. 2 . FIG. 1 and FIG. 2 are signal schematic diagrams of a low-swing differential signal interface of a conventional display. First, in FIG. 1 , the clock controller of the display generates a set of differential voltage signals DxN and DxP. The differential voltage signals DxN and DxP have a phase difference of 180° and the same slew rate, and swing up and down based on the common-mode voltage VCOM. Next, in Figure 2, the differential voltage signal DxP is subtracted from the differential voltage signal DxN to obtain the differential voltage signal DIF (DxP-DxN), which has a positive voltage swing VIH and a negative voltage swing VIL. have the same magnitude, which is the difference between the peak and valley of the differential voltage signals DxN and DxP.

Please refer to Fig. 3 and Fig. 4. Fig. 3 and Fig. 4 respectively show the signal line pairs D00P/N, D01P/N, D02P/N, D03P/N, D10P/N, Schematic diagram of currents in high and low states of signals of D11P/N, D12P/N, D13P/N, D20P/N, D21P/N, D22P/N and D23P/N. In FIG. 3 and FIG. 4 , the output terminal Tx represents the output terminal of the clock controller, and the receiving terminal Rx represents the receiving terminal of the source driver. The clock controller generates differential currents on the aforementioned 12 signal line pairs from the output terminal Tx, and the receiving terminal Rx of the source driver receives signals by sensing the current direction on each signal line pair. For example, in FIG. 3, the current flowing from the signal line D01P to D01N represents the signal high state, or '1'; in FIG. 4, the current flowing from the signal line D01N to D01P represents the signal low state, or '0'. Therefore, each signal line pair of the low-swing differential signal interface can only represent a signal of one bit.

Please refer to FIG. 5 . FIG. 5 is a timing diagram of a signal interface of a low-swing differential signal interface of a known display. The timing of the signal from top to bottom is: clock signal S _CLK , left shift signal S _SHL , polarity signal S _POL , differential signal line pair D00P/N, D01P/N, D02P/N, D03P/N, D10P/N , D11P/N, D12P/N, D13P/N, D20P/N, D21P/N, D22P/N and D23P/N low-swing differential signals, data latch start signal S _DIO , data output synchronization signal S _LD and voltage output signal S _OUTPUT . After the left and right shift control signal S _SHL , polarity signal S _POL , data latch start signal S _DIO and data output synchronization signal S _LD and other control signals are given to the source driver, the source driver can perform related settings, and then pass the low The swing differential signal receives data, and the working principle of its interface timing is roughly as follows. When the negative edge of the clock signal S _CLK latches (Latch) the high state of the data latch start signal S _DIO (point A), after two negative edges of the clock signal S _CLK (point B), the low swing The differential signal starts to transmit the data signal, and is sampled simultaneously by the rising and falling edges of the clock signal S _CLK (dual edge sampling; points B and C). The source driver then uses the data output synchronization signal S _LD to synchronize the output time of the data and transmit the information to the panel (point D). As can be seen from the above, known displays transmit control and setting signals through a transistor-transistor logic (TTL) interface (left and right shift control signal S _SHL , polarity signal S _POL , data latch start signal S _DIO and data output synchronization signal S _LD ) to the source driver, and transmit the data signal to the source driver through the low-swing differential signal interface.

Therefore, in the known display, the data signal, control signal, setting signal and clock signal are transmitted through two different signal interfaces (low-swing differential signal interface and transistor-transistor logic interface), which may easily cause the signals to be out of sync. (signal skewing) makes it difficult to adjust time parameters such as setup time or hold time. Therefore, known displays cannot increase their data rate or clock rate in high speed and high resolution applications. In addition, because the known low-swing differential signal interface only uses current direction to distinguish data, and its signal lines are only used to transmit data signals and clock signals. As the color depth of each pixel on the screen increases, more signal lines are required. In addition, it is known that different signals in the display are transmitted through individual signal lines, resulting in the wiring of the circuit board and the number of layer changes. increase, taking up a lot of space on the printed circuit board. On the other hand, since it is known that the display transmits the clock signal and the data signal respectively through different signal lines, in order to make the source driver work normally, the clock controller needs to use setting signals to set different pins in the source driver, for example Left and right shift pins, data inversion pins, low power control pins, charge sharing/recycling start pins, etc. Therefore, the number of pins of the source driver will be too many, resulting in reduced pin pitch, which will reduce the yield rate of the bonding process and increase the production cost of the LCD.

Contents of the invention

Therefore, the present invention provides a serial data transmission method for a display device and related devices.

The present invention discloses a serial data transmission method for a display device, including: obtaining multiple data transmission modes of the display device; Various combinations of current magnitudes and directions transmitted define a plurality of current combinations, each current combination corresponds to a data transmission mode, wherein the current magnitude and direction are selected from a plurality of current magnitudes and a plurality of current directions; and according to In the current data transmission mode, corresponding currents are output through the plurality of differential signal line pairs to be combined to the electronic device of the display device.

The invention also discloses an interface device for a display device, which includes a plurality of differential signal line pairs, a storage unit, a judgment unit, and a current output unit. The storage unit is used to store multiple current combinations, the multiple current combinations are defined by multiple combinations of the magnitude and direction of the currents respectively transmitted on the multiple sets of differential signal line pairs, each current combination corresponds to the A data transmission mode among the multiple data transmission modes of the display device, wherein the magnitude and direction of the current are selected from multiple current magnitudes and multiple current directions. The judging unit is coupled to the storage unit, and is used for selecting a current combination from the plurality of current combinations stored in the storage unit according to the current data transmission mode. The current output unit, coupled to the judging unit, is used for outputting the combined current to the electronic device of the display device through the plurality of differential signal line pairs.

Description of drawings

FIG. 1 and FIG. 2 are signal schematic diagrams of a low-swing differential signal interface of a conventional display.

FIG. 3 and FIG. 4 are schematic current diagrams of signal high state and low state of a signal line pair of a low-swing differential signal interface of a conventional display.

FIG. 5 is a schematic diagram of a timing sequence of a signal interface of a low-swing differential signal interface of a conventional display.

FIG. 6 is a flowchart of a serial data transmission process for a display device according to the present invention.

7 to 9 are schematic diagrams of signal characteristics of a differential signal interface with variable current according to an embodiment of the present invention.

FIG. 10 to FIG. 17 are schematic diagrams of the pairing of the current combination and the data transmission mode according to the embodiment of the present invention according to FIG. 4 .

FIG. 18 is a schematic diagram of an interface sequence of a display device according to an embodiment of the present invention.

FIG. 19 is a schematic diagram of a serial interface timing according to an embodiment of the present invention.

FIG. 20 is a schematic diagram of an interface device for a timing controller of a display device according to an embodiment of the present invention.

[Description of main component labels]

DxN, DxP, DATAxN, DATAxP, DIF, DIF _NEW , DIF0 _NEW , differential voltage signal

DIF1 _NEW

VIH, VIL, VIH _NEW , VIL _NEW voltage swing

D00P/N, D01P/N, D02P/N, D03P/N, D10P/N, differential voltage signal line pair

D11P/N, D12P/N, D13P/N, D20P/N, D21P/N,

D22P/N, D23P/N, DATA0P/N, DATA1P/N

92 Timing Controller 94 Source Driver

90 Display device 910 Storage unit

920 Judgment unit 930 Current output unit

Tx Output Terminal Rx Receiver

900 interface device

SYNC, LD, CONTROL, DIO, DATA, OUTPUT, DATA1, data transmission mode

DATA2, DATA3, DATA4, DATA5, DATA6, DATA7,

DATA8

S _CLK , S _SYNC , S _POL , S _SHL , S _DIO , S _LD , S _OUTPUT , S _DATA0 , S _DATA1 signals

60 Process

602, 604, 606, 608, 610 Steps

Detailed ways

Please refer to FIG. 6 , which is a flowchart of a serial data transmission process 60 for a display device according to the present invention. Process 60 comprises the following steps:

Step 602: start.

Step 604: Obtain multiple data transmission modes of the display device.

Step 606: According to the multiple data transmission modes, define multiple current combinations with multiple current magnitudes and multiple current directions, and each current combination corresponds to a data transmission mode.

Step 608: According to the current data transmission mode, output corresponding current combinations to the electronic device of the display device through multiple transmission lines.

Step 610: end.

According to the process 60, in order to transmit data and control signals to the electronic device, the present invention corresponds to each data transmission mode according to the number and type of data transmission modes of the display device, and each current combination It is defined by different current magnitudes and current directions.

The present invention can be applied to the transmission mode between any two devices in the display device, but for the sake of convenience, the following embodiments of the present invention will be described with the data transmission mode between the timing controller and the source driver in the display , wherein between the timing controller and the source driver, the embodiment of the present invention uses differential signal lines to transmit signals. Therefore, by transmitting different current combinations, the timing controller can transmit signals corresponding to different data transmission modes to the source driver, such as synchronous mode for transmitting reset and synchronization signals, data mode for transmitting data signals, and so on. In this case, when it is necessary to transmit a signal to the source driver, the process 60 can generate a corresponding current combination according to the data transmission mode selected by the timing controller, and output it to the source through multiple transmission lines (such as a differential line pair) pole drive.

It should be noted that the present invention provides different current magnitudes and directions on the transmission line. The direction can be defined by itself, and various current combinations can be formed based on the current magnitude and direction. The current combination method is not limited to specific regulations. For example, it can be A data transmission mode can be defined by two currents with different magnitudes and directions both forward, or three different current magnitudes with two forward directions and one reverse direction, etc. For example, if two currents with current sizes I ₁ and I ₂ are used and I+ and I- represent the forward and reverse directions of the current direction, and a pair of differential line pairs DATAxP and DATAxN are used to output the current, then four The current combinations are (1) DATAxP: I ₁ +, DATAxN: I ₁ -; (2) DATAxP: I ₁ -, DATAxN: I ₁ +; (3) DATAxP: I ₂ +, DATAxN: I ₂ - ; (4) DATAxP: I ₂ -, DATAxN: I ₂ +; The four current combinations can respectively correspond to two data transmission modes to transmit the required signals, wherein (1), (2) and (3), (4) It can represent the high and low states of the signal respectively. As another example, if the aforementioned current magnitudes I ₁ , I ₂ and current directions I+, I- are applied to two sets of differential line pairs DATA0P, DATA0N and DATA1P, DATA1N, sixteen kinds of current combinations can be formed, respectively: :

(1) DATA0P: I ₁ +, DATA0N: I ₁ -, DATA1P: I ₂ +, DATA1N: I ₂ -;

(2) DATA0P: I ₁ +, DATA0N: I ₁ -, DATA1P: I ₂ -, DATA1N: I ₂ +;

(3) DATA0P: I ₁ -, DATA0N: I ₁ +, DATA1P: I ₂ +, DATA1N: I ₂ -;

(4) DATA0P: I ₁ -, DATA0N: I ₁ +, DATA1P: I ₂ -, DATA1N: I ₂ +;

(5) DATA0P: I ₂ +, DATA0N: I ₂ -, DATA1P: I ₁ +, DATA1N: I ₁ -;

(6) DATA0P: I ₂ +, DATA0N: I ₂ -, DATA1P: I ₁ -, DATA1N: I ₁ +;

(7) DATA0P: I ₂ -, DATA0N: I ₂ +, DATA1P: I ₁ +, DATA1N: I ₁ -;

(8) DATA0P: I ₂ -, DATA0N: I ₂ +, DATA1P: I ₁ -, DATA1N: I ₁ +;

(9) DATA0P: I ₁ +, DATA1N: I ₁ -, DATA1P: I ₂ +, DATA0N: I ₂ -;

(10) DATA0P: I ₁ +, DATA1N: I ₁ -, DATA1P: I ₂ -, DATA0N: I ₂ +;

(11) DATA0P: I ₁ -, DATA1N: I ₁ +, DATA1P: I ₂ +, DATA0N: I ₂ -;

(12) DATA0P: I ₁ -, DATA1N: I ₁ +, DATA1P: I ₂ -, DATA0N: I ₂ +;

(13) DATA0P: I ₂ +, DATA1N: I ₂ -, DATA1P: I ₁ +, DATA0N: I ₁ -;

(14) DATA0P: I ₂ +, DATA1N: I ₂ -, DATA1P: I ₁ -, DATA0N: I ₁ +;

(15) DATA0P: I ₂ -, DATA1N: I ₂ +, DATA1P: I ₁ +, DATA0N: I ₁ -;

(16) DATA0P: I ₂ -, DATA1N: I ₂ +, DATA1P: I ₁ -, DATA0N: I ₁ +;

Therefore, in the present invention, the types and numbers of the transmission lines, the selection of the magnitude and direction of the current are not limited to specific ranges, and those skilled in the art can make changes as needed.

As mentioned above, known low-swing differential signal interfaces only use current direction to define signals, and can only be used to transmit image data. When the amount of data is large, more transmission lines are required to transmit signals. In contrast, the process 60 of the present invention simultaneously uses the magnitude and direction of the current to define multiple current combinations, so as to transmit corresponding signals to the source driver according to the corresponding data transmission mode. In this way, the present invention can use the same The transmission line of the group transmits a variety of different signals, such as data signals, control signals, etc., which greatly reduces the area and complexity of wiring on the printed circuit board.

According to the process 60, the embodiment of the present invention uses a differential signal interface with variable current to implement the current combination and data transmission mode in step 606. Please refer to FIG. 7 to FIG. 9 . FIG. 7 to FIG. 9 are signal schematic diagrams of a differential signal interface with variable current according to an embodiment of the present invention. FIG. 7 is similar to FIG. 1 , and the voltages of the differential voltage signals DATAxN and DATAxP can be adjusted to change the positive voltage swing VIH _NEW and the negative voltage swing VIL _NEW . For example, the timing controller in the display can adjust the magnitude and direction of the current of a group of differential line pairs DATAxN and DATAxP, so that the current will cause different voltages on the internal termination resistors, so as to change the positive voltage swing VIH _NEW and the negative voltage swing Frame VIL _NEW . Therefore, if the positive voltage swing VIH _NEW and the negative voltage swing VIL _NEW vary by different multiples, it means that the real-time sequence controller provides the differential line pair with current changes of equal multiples. In FIG. 8 and FIG. 9 , the differential voltage signal DIF _NEW (DATAxP-DATAxN) can represent double, triple and double DC voltage values (1*M, 3*M, 2*M). Therefore, the present invention can utilize different DC voltage values and current directions of the differential voltage signal to define multiple current combinations corresponding to multiple data transmission modes.

Please refer to FIG. 10 to FIG. 17 . FIG. 10 to FIG. 17 are schematic diagrams of data transmission modes and current combinations according to embodiments of the present invention. The data transmission modes DATA1 to DATA8 in FIGS. 10 to 17 respectively correspond to a current combination. In the embodiment of the present invention, the timing controller uses two sets of differential signal lines DATA0P/N and DATA1P/N to output current to the source driver. The source driver obtains two differential voltage signals DIF0 _NEW and DIF1 _NEW by sensing the voltage formed on the terminal resistor by the differential signal lines DATA0P/N and DATA1P/N. Taking the data transmission mode DATA1 in FIG. 10 as an example, the timing controller generates a positive differential voltage signal of three times the DC voltage value +3*M on the differential signal line DATA0P/N, and a differential voltage signal on the differential signal line DATA1P/N N generates a differential voltage signal with a double DC voltage value of ±1*M, so the data transmission mode DATA1 corresponds to the current combination of (DIF0 _NEW :+3*M, DIF1 _NEW :±1*M), where the difference The current direction on the dynamic voltage signal DIF1 _NEW can be used to distinguish the positive and negative edges of the clock signal. Similarly, the data transmission modes DATA2~DATA4 respectively correspond to current combinations: (DIF0 _NEW :-3*M, DIF1 _NEW :±1*M), (DIF0 _NEW :+1*M, DIF1 _NEW :±3*M) And (DIF0 _NEW : -1*M, DIF1 _NEW : ±3*M). In addition, taking the data transmission mode DATA5 in FIG. 13 as an example, the timing controller generates a differential voltage signal of three times the DC voltage value 3*M on the differential signal lines DATA0P and DATA1N, and generates a differential voltage signal on the differential signal lines DATA0N and DATA1P Generate a differential voltage signal with a DC voltage value of 1*M, so the data transmission mode DATA5 corresponds to (DIF0 _NEW :+2*M, DIF1 _NEW :+2*M) or (DIF0 _NEW :-2*M , DIF1 _NEW :-2*M) current combination, wherein the current direction on the differential voltage signal DIF1 _NEW can be used to distinguish the positive and negative edges of the clock signal. Similarly, the data transmission mode DATA6 corresponds to the current combination of (DIF0 _NEW :+2*M, DIF1 _NEW :-2*M) or (DIF0 _NEW :-2*M, DIF1 _NEW :+2*M). Among them, the positive and negative signs represent the positive and negative directions of the defined current.

The current combinations shown in FIG. 10 to FIG. 17 correspond to eight data transmission modes. Those skilled in the art can respectively define the types of signals transmitted by the data transmission modes DATA1-DATA8 according to the required data transmission modes. For example, data transmission modes DATA1~DATA6 can be defined, which are control mode (CONTROL), latch mode (DIO), data mode (DATA), voltage output mode (OUTPUT), synchronization mode (SYNC) and data output synchronization mode (LD). The synchronous mode is used to transmit the synchronous signal to reset the source driver and the circuit of the synchronous start source driver; the data output synchronous mode is used to transmit the data output synchronous signal to synchronize the output timing of the image data; the control mode is used to transmit the control signal to provide multiple setting signals to the source driver; the latch mode is used to transmit the latch signal to enable the source driver to perform data latching; the data mode is used to transmit the data signal to transmit the image data to the source driver; and, the voltage output mode is used to transmit the voltage output signal to drive the source driver to output the image data. In this case, the control signal, setting signal and data signal in the display device are embedded in only two sets of differential signal lines at the same time, which not only saves the wiring on the printed board, but also facilitates the operation of data synchronization at high frequency.

It should be noted that those skilled in the art can make appropriate changes to increase, decrease or change the combination of currents according to requirements, so as to match the defined data transmission mode. For example, the data transmission modes DATA1-DATA4 correspond to the first group of data transmission modes, and DATA5-DATA8 correspond to the second group of data transmission modes. In addition, the operation content and operation time of each data transmission mode can be defined according to the needs. For example, the synchronous mode is not only used to transmit the synchronous signal, but also can transmit the synchronous signal and the data output synchronous signal at the same time, and the operating time of the mode only needs to be a multiple of the period of the clock signal in the system, and is not limited to a specific length of time.

Please refer to FIG. 18 . FIG. 18 is a schematic diagram of an interface sequence for a display device according to an embodiment of the present invention. It can be seen from Figure 18 that the timing of DIF0 _NEW and DIF1 _NEW can be divided into synchronous mode, control mode, latch mode, data mode, data output synchronous mode and voltage output mode. The operation time of all data transmission modes is the clock signal S multiple of the cycle time of _CLK . According to the timing of the timing controller and the source driver, the left and right shift control signal S _SHL and polarity signal S _POL are transmitted in the control mode; the data signals S _DATA0 and S _DATA0 are transmitted in the data mode; the synchronization signal S _SYNC and the latch signal S _DIO , the data output synchronous signal S _LD and the voltage output signal S _OUTPUT are respectively transmitted in the synchronous mode, the latch mode, the data mode, the data output synchronous mode and the voltage output mode. The working principle of the interface timing in Figure 18 is as follows. When the timing controller operates in synchronous mode (point A), the timing controller outputs current through the differential signal lines DATA0P/N and DATA1P/N, forming a voltage combination on the terminal resistor ( DIF0 _NEW :+2*M, DIF1 _NEW :+2*M) or (DIF0 _NEW :-2*M, DIF1 _NEW :-2*M) to the source driver, after the source driver goes through the decoding process, it starts to receive synchronously Signal S _SYNC to reset and start the internal circuit synchronously. Similarly, when the timing controller operates in the data output synchronous mode (point B), the timing controller outputs current through the differential signal lines DATA0P/N and DATA1P/N, forming a voltage combination on the terminal resistor (DIF0 _NEW : +2 *M, DIF1 _NEW :-2*M) or (DIF0 _NEW :-2*M, DIF1 _NEW :+2*M) to the source driver, the source driver starts to receive the data output synchronization signal S _LD after going through the decoding process , to synchronize the output timing of the image data in the source driver. In addition, the voltage combination of latch mode (point C) is (DIF0 _NEW :-3*M, DIF1 _NEW :±1*M), the source driver starts to receive the latch signal S _DIO after the decoding process, so that the source The pole driver performs data latching; the voltage combinations of the data mode (D and E points) are (DIF0 _NEW :+1*M, DIF1 _NEW :+3*M) and (DIF0 _NEW :+1*M, DIF1 _NEW : -3*M), that is, the source driver starts to receive the data signal S _DATA after the decoding process, so that the source driver performs data reception on the positive and negative clock edges of the clock signal S _CLK .

It should be noted that those skilled in the art can make appropriate changes, increase, decrease or change the number and usage of the data transmission modes in the display device according to requirements, and match the defined current combinations. For example, those skilled in the art can obtain only four modes of synchronization, control, latch and data, and define their corresponding current combinations, so that the synchronization mode is used to transmit the synchronization signal S _SYNC and the data output synchronization signal S _LD , while the control, The latch and data modes are respectively used to transmit the control signal, the latch signal S _DIO and the data signal S _DATA .

Please refer to FIG. 19 , which is a schematic diagram of a serial interface timing according to an embodiment of the present invention. In order to make the display device work normally, each complete sequence needs to include the aforementioned six data transmission modes, and operate according to predetermined rules, so that the image data can be correctly displayed on the panel. The predetermined rule of the embodiment of the present invention is that the data mode is after the synchronous mode and before the data output synchronous mode; the control mode can be freely placed separately, as shown in (c) of Figure 19, only after the synchronous mode and the voltage output synchronous mode Before. Therefore, in the embodiment of the present invention, control signals, setting signals (such as synchronization signals, data output synchronization signals, etc.) and data signals are embedded on the same interface, and through the definition of data transmission mode, the timing controller and Transfer protocol between source drivers.

Please refer to FIG. 20 , which is a schematic diagram of an interface device 900 used for the timing controller 92 of the display device 90 according to an embodiment of the present invention. The interface device 900 includes two sets of differential signal lines DDS0P/N and DDS1P/N, a storage unit 910 , a judging unit 920 and a current output unit 930 . The display device 90 defines different current combinations and stores them in the storage unit 920 according to multiple required data transmission modes. When the timing controller 92 operates in a certain data transmission mode, the judging unit 920 selects a current combination from the plurality of current combinations stored in the storage unit 910 according to the data transmission mode. Next, the current output unit 930 outputs the selected current combination to the source driver 94 through the differential signal lines DATA0P/N and DATA1P/N. The source driver 94 senses the current current combination to perform a decoding process, and decodes the corresponding transmission signal mode, and starts to receive control signals, data signals or perform related operations. Therefore, the present invention utilizes a dedicated channel, and the real-time sequence controller uses two sets of differential signal lines for each source driver to perform data transmission. Of course, those skilled in the art can make appropriate changes to the transmission lines, depending on the number of data transmission modes inside the display device 90, the combination of transmission lines can be increased, decreased or changed, not limited to two sets of differential signal lines.

To sum up, in terms of interface characteristics, the known technology is to use the direction of current to transmit data, so that each set of differential signal lines can only represent a data signal of one bit, and the transmission of control and setting signals needs to be realized through other interfaces. ; In contrast, the present invention uses different current magnitudes and directions to transmit data at the same time, so that a set of transmission lines can transmit multiple current combinations, and then define multiple data transmission modes. In this way, the timing controller can be The control signals, setting signals and data signals of the transmission line are embedded in the transmission line at the same time. On the other hand, in terms of hardware implementation, in order to transmit different signals, the known technology utilizes multiple transmission interfaces to communicate with the source driver, and adopts a bus type, resulting in too many pins, and the signal transmission is easily reflected. On the contrary, the present invention can use fewer transmission lines, and use dedicated channels and serial types to transmit various signals, so as to reduce the number of wiring and reduce the difficulty of impedance matching inside the source driver. Thus, it is apparent that the present invention can solve various problems of the known art.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (12)

1. data transmission method that is used for the display device string type includes:

Obtain a plurality of data-transmission modes of this display device;

According to these a plurality of data-transmission modes, with many groups differential signal line the multiple combination of the last size and Orientation of electric current transmitted is respectively defined a plurality of currents combination, each currents combination is corresponding to a data-transmission mode, wherein, described size of current and direction are chosen from a plurality of size of current and a plurality of direction of current; And

According to the current data transmission mode, by described, organize differential signal lines to exporting the electronic installation of corresponding currents combination to this display device more.

2. method according to claim 1, wherein these a plurality of data-transmission modes include:

Synchronous mode is used for synchronous signal transmission, with this electronic installation and the circuit that opens this electronic installation of beginning synchronously of resetting;

Data output synchronous mode is used for transmitting data output synchronizing signal, with the output timing of synchronous images data;

Control model is used for transmission of control signals, to provide a plurality of setting signals to this electronic installation;

Fasten latching mode, be used for transmitting and fasten lock signal, fasten lock so that this electronic installation carries out data;

Data pattern is used for transmission of data signals, to transmit this view data to this electronic installation; And

The voltage output mode is used for the transmission voltage output signal, exports this view data to drive this electronic installation.

3. method according to claim 2, wherein this synchronous mode and this data output synchronous mode is corresponding to first group of data-transmission mode, and this control model, to fasten latching mode, this data pattern and this voltage output mode be corresponding to second group of data-transmission mode for this.

4. method according to claim 2, it also comprises according to pre-defined rule, determines the order of these a plurality of data-transmission modes.

5. method according to claim 1, wherein should to organize differential signal lines right to comprising two groups of differential signal lines more, and every group of differential signal line is to comprising two differential signal lines.

6. method according to claim 5, wherein these a plurality of size of current are corresponding to two size of current, and these a plurality of direction of current are corresponding to forward current direction and inverse current direction.

7. interface arrangement that is used for display device includes:

Many group differential signal lines are right;

Storage element, be used for storing a plurality of currents combination, these a plurality of currents combination are with these many group differential signal lines the multiple combination of the last size and Orientation of electric current transmitted respectively to be defined, each currents combination is corresponding to a data-transmission mode in a plurality of data-transmission modes of this display device, wherein, described size of current and direction are chosen from a plurality of size of current and a plurality of direction of current;

Judging unit is coupled to this storage element, is used for according to the current data transmission mode, by selecting a currents combination in stored these a plurality of currents combination of this storage element; And

Current output unit is coupled to this judging unit, is used for by these many group differential signal lines to exporting the electronic installation of this currents combination to this display device.

8. interface arrangement according to claim 7, wherein these a plurality of data-transmission modes include:

Synchronous mode is used for synchronous signal transmission, with this electronic installation and the circuit that opens this electronic installation of beginning synchronously of resetting;

Data output synchronous mode is used for transmitting data output synchronizing signal, with the output timing of synchronous images data;

Control model is used for transmission of control signals, to provide a plurality of setting signals to this electronic installation;

Fasten latching mode, be used for transmitting and fasten lock signal, fasten lock so that this electronic installation carries out data;

Data pattern is used for transmission of data signals, to transmit this view data to this electronic installation; And

The voltage output mode is used for the transmission voltage output signal, exports this view data to drive this electronic installation.

9. interface arrangement according to claim 8, wherein this synchronous mode and this data output synchronous mode is corresponding to first group of data-transmission mode, and this control model, to fasten latching mode, this data pattern and this voltage output mode be corresponding to second group of data-transmission mode for this.

10. interface arrangement according to claim 8, it also comprises according to pre-defined rule, determines the order of these a plurality of data-transmission modes.

11. interface arrangement according to claim 7, wherein should to organize differential signal lines right to comprising two groups of differential signal lines more, and every group of differential signal line is to comprising two differential signal lines.

12. interface arrangement according to claim 11, wherein these a plurality of size of current are corresponding to two size of current, and these a plurality of direction of current are corresponding to forward current direction and inverse current direction.

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