CN101243417B - Nonvolatile storage device, memory controller, and defective region detection method - Google Patents

Abstract

It is possible to accurately detect a physical block which has caused a fixture defect in a flash memory so as to limit the use of the physical block. By recording a history of generation of a physical block error and a history of physical erase in an ECC error record, it is judged whether the error which has occurred is accidental or caused by a fixture defect. When no error is caused in the data rewritten by physical erase after a first read error occurrence, the first error is accidental and if another error is caused, the error is judged to be caused by a fixture defect. By using such an ECC error record, it is possible to accurately judge whether the error is accidental or caused by a fixture defect. By eliminating use of the physical block judged to have a fixture defect, it is possible to reduce read errors.

Description

Nonvolatile memory device, memory controller, and method for detecting bad areas

technical field

The present invention relates to methods for reducing error caused by defects in the nonvolatile memory in a nonvolatile memory device using an error correction function for improving the reliability of data recorded in the nonvolatile memory. A non-volatile storage device, a storage controller, and a method for detecting bad areas for sporadic read errors.

Background technique

In recent years, memory cards equipped with nonvolatile memory are expanding their market as memory cards for digital cameras and mobile phones. However, each time data is rewritten in a non-volatile memory, the memory cell gradually deteriorates, and finally a writing or reading error occurs. Of course, if the reliability is sufficiently high that the deterioration of the memory cell due to rewriting is almost negligible, there will be no problem even if it is used for ten years. However, this may not be the case in practice, and a substantially reliable memory card is realized by incorporating an error correction circuit such as an ECC (Error Checking and Correction) circuit in a system that controls the nonvolatile memory.

However, it is difficult to ensure the reliability of a single memory cell due to the downsizing of the memory cell due to the miniaturization of the process, or due to the multi-valued realization of the large capacity. In addition, it is difficult to inspect devices with sufficient high precision because the pattern of memory is increased along with the development of large capacity, and the time for product inspection is also increased.

As a method of managing errors in writing or reading of a flash memory, Patent Document 1 proposes a method of counting error occurrence information during reading and writing so as not to use corrupted areas. In addition, Patent Document 2 proposes a method of performing replacement processing on regions in which read errors continue.

Patent Document 1: JP-A-11-53266

Patent Document 2: WO01/022232

Most nonvolatile memories including flash memory have the ability to continuously hold data without applying energy such as a bias voltage to memory cells. This shows that the state of holding the data is stable. It is completely different from SRAM, which is a volatile memory, which retains data by applying energy. Therefore, in order to rewrite the data of the nonvolatile memory, it is necessary to apply energy to the memory cell in a stable state, and at this time, deterioration of the memory cell occurs although slight.

Errors caused by memory cell deterioration in nonvolatile memories such as flash memories are mostly caused by rewriting of data, and are less affected by data reading. Considering this point, it is possible to appropriately perform processing when an error occurs. However, in the nonvolatile memory device described in Patent Document 1 or Patent Document 2, the nonvolatile memory caused by data rewriting and data reading is not fully considered. Deterioration of volatile memory. In addition, although compared with data rewriting, the influence of data reading on error occurrence is extremely small, but when the same data is read many times, it is not the deterioration of the memory cell that is found, but the gradual progress. The deterioration of the data itself, so the impact of data readout cannot be ignored. However, the nonvolatile memory devices described in Patent Document 1 or Patent Document 2 do not sufficiently consider such progressive data deterioration.

For example, a NAND-type flash memory, which is a representative general nonvolatile memory, is commercialized on the premise of error correction by an ECC circuit. This is because sporadic bit errors are unavoidable in nonvolatile memory. Therefore, a memory controller of a memory card using a NAND type flash memory has a function of generating an ECC code or a function of detecting and correcting an error inside it. The storage controller uses ECC circuits to correct sporadic bit errors and reuse the physical blocks where errors occurred. This increases the substantial reliability of the memory card.

However, although the frequency of sporadic bit errors is lower than that of sporadic bit errors, bit errors may occur during reading due to defects inherent in physical blocks due to deterioration of memory cells or the like. In the case of using a NAND-type flash memory with sufficiently high reliability and a low frequency of bit errors, like the existing memory controller, it does not judge whether the bit errors that occur are accidental or inherently defective, and the use of physical memory is limited. block, no problem occurs in the use of flash memory. However, the frequency of occurrence of bit errors has increased more than ever due to miniaturization or multi-valued processes of flash memory. From this point, it is necessary to allow bit errors on the premise of performing error correction, and it is necessary to continue using the flash memory by correcting the errors even if bit errors occur. However, when the main cause of the bit error is inherent defect of the memory cell, reading errors of the memory card frequently occur in physical blocks having the inherent defect.

For example, sometimes a still image taken with a digital camera cannot be viewed due to a data error caused by an inherent defect in the physical block of the memory card. In this case, if the data of the still image is deleted on the digital camera system, the same block will be reused for the still image captured later, and a data error will occur again. It frequently happens that still images cannot be viewed.

In addition, if there is no inherent defect, but if the reading of the same data is repeated a very large number of times, bit errors will gradually increase, which may degrade the data. In this case, when using a NAND flash memory with sufficiently high reliability and low frequency of bit errors, the use of physical blocks may be limited according to the occurrence of bit errors, as in conventional memory controllers. However, when error correction is a prerequisite, that is, when bit errors must be tolerated, it is necessary to continue using the flash memory after correcting errors even if bit errors occur. Therefore, the number of bits causing bit errors due to data deterioration exceeds the error correction capability, and uncorrectable read errors occur as a result. In view of these circumstances, development of a memory card with reduced reading errors has become a subject.

Contents of the invention

The present invention accurately detects, in a flash memory, a physical block presumed to have an inherent defect, or a physical block presumed to have exceeded error correction capability by accumulating bit defects caused by reading. Furthermore, an object thereof is to provide a highly reliable nonvolatile memory device by limiting or avoiding writing or reading to the physical block.

In order to solve this problem, the nonvolatile memory device of the present invention is a nonvolatile memory device including a nonvolatile memory and a memory controller. The nonvolatile memory has a plurality of physical blocks as units of clearing. , the above-mentioned physical block has a plurality of physical pages as a writing unit, and the above-mentioned storage controller has: an arithmetic processing unit for performing overall control inside the above-mentioned storage controller; an error correction circuit for a function of error and a function of correcting an error when it can be corrected; an address table holding a table necessary for managing data stored in the above-mentioned nonvolatile memory, the address table of the above-mentioned memory controller having: an error table having a plurality of error records, the error records are information related to the above-mentioned read error about the physical block in which the read error has been detected by the above-mentioned error correction circuit; The physical block and the item table of the information whether the data is written or cleared; the logical-physical conversion table representing the conversion information between the logical block address specified by the master device from the outside and the physical block address of the above-mentioned non-volatile memory, the above-mentioned operation The processing unit registers and updates an error record in the error table based on the error detection from the error correction circuit, and determines whether to use the physical block in which the read error was detected.

Here, it is also possible that the address table of the above-mentioned storage controller is further provided with a defective block table that records information related to the address of the physical block that prohibits data writing and reading, and the error record of the above-mentioned error table has: when the above-mentioned error correction When the circuit has detected an error in the data read from the above-mentioned non-volatile memory, record the error block information indicating the address information of the physical block where the error occurred; record the error information indicating that the above-mentioned error has occurred; record the error information indicating After the above-mentioned error occurs, the data of the above-mentioned physical block is cleared, and the error block clear information of the information of new data is written; it indicates that after the information is recorded in the above-mentioned error block clear information, it is detected again in the same physical block When the error recurrence information of the error is read, the above-mentioned operation processing unit refers to the above-mentioned error table when writing data in the above-mentioned non-volatile memory, and when there is at least the above-mentioned error block information and the above-mentioned In the error recording of the error reoccurrence information, information on the address of the physical block in which the data is written is recorded in the defective block table.

Here, the error record in the error table may further include error page information in which an address of the physical page in which a read error has been detected by the error correction circuit is written.

Here, the arithmetic processing unit may record and update information in the error record of the error table only when the read error detected by the error correction circuit cannot be corrected by the error correction circuit.

Here, the arithmetic processing unit may record and update information in the error record of the error table only when the read error detected by the error correction circuit cannot be corrected by the error correction circuit.

Here, it is also possible that the address table of the above-mentioned memory controller further includes a bad block table that records information related to the address of the physical block that is prohibited from writing and reading data, and the error record of the above-mentioned error table includes: When the circuit has detected an error in the data read from the above-mentioned non-volatile memory, record the error block information indicating the address information of the physical block where the error occurred; the error count information as the information indicating the number of times that the error occurred in the readout ; Represent the error block clearing count information of the number of times that the physical block of the above-mentioned read error has been physically cleared, when the above-mentioned arithmetic processing unit writes data in the above-mentioned non-volatile memory, refer to the above-mentioned error table, When the physical block of data has the above-mentioned error record in which the above-mentioned error block information is recorded, the above-mentioned error count information is compared with the above-mentioned error block clear information, the above-mentioned error block clear information indicates a predetermined number of times, and the value of the above error count information is higher than When the error block clear information is large, information on the address of the physical block in which the data is written is recorded in the defective block table.

Here, the error record in the error table may further include error page information in which an address of the physical page in which a read error has been detected by the error correction circuit is written.

Here, in the arithmetic processing unit, if the error correction circuit detects a read error, the error record in the error table may be registered and updated irrespective of whether the error correction circuit can correct it or not.

Here, in the arithmetic processing unit, if the error correction circuit detects a read error, the error record in the error table may be registered and updated irrespective of whether the error correction circuit can correct it or not.

Here, the error record in the error table may include: error block information written in the address of the physical block whose read error is detected by the error correction circuit; error page information of an address of an erroneous physical page; an error bit count of information indicating the number of bits read out error, the above-mentioned operation processing unit using a value having an error bit number less than or equal to the number of error bits that can be corrected by the error correction circuit, and Predetermined correction threshold, read the data of the physical block corresponding to the error record of the above-mentioned error table whose error bit count information is greater than or equal to the above-mentioned correction threshold, so that the above-mentioned error correction circuit corrects the error of the read data, and converts the Corrected data is written to other physical blocks.

Here, the arithmetic processing unit may use a value equal to or less than the number of error bits that can be corrected by the error correction circuit when the data read process from the outside to the nonvolatile memory is not performed, and the error correction circuit may be used in advance. Determine the correction threshold, read the data of the physical block corresponding to the error record of the above-mentioned error table whose information of the above-mentioned error bit count is greater than or equal to the above-mentioned correction threshold, so that the above-mentioned error correction circuit corrects the error of the read data, and the correction The completed data is written to other physical blocks.

Here, the error record in the error table may include: error block information for recording information indicating the address of the physical block in which the error correction circuit detected a read error; Error page information of information on the address of the above-mentioned physical page; recording an error occurrence of information indicating that a read error has occurred with a value less than or equal to the number of error bits that can be corrected by the above-mentioned error correction circuit and greater than or equal to a predetermined correction threshold value information, the above-mentioned operation processing unit reads the data of the physical block corresponding to the error record of the above-mentioned error table that records the above-mentioned error occurrence information, causes the above-mentioned error correction circuit to correct the error of the read data, and writes the corrected data into other physical blocks.

Here, the arithmetic processing unit may read the data of the physical block corresponding to the error record of the error table in which the error occurrence information is recorded, when the processing of reading the data of the nonvolatile memory is not performed. , causing the error correction circuit to correct the error of the read data, and writing the corrected data into another physical block.

In order to solve this problem, the memory controller of the present invention is a nonvolatile memory having a plurality of physical blocks as a unit of erasing, and the physical block has a plurality of physical pages as a unit of writing. The storage controller for reading and writing is provided with: an arithmetic processing unit for performing overall control inside the above-mentioned storage controller; a function of detecting errors in data read from the above-mentioned non-volatile memory and performing error correction when the errors can be corrected; an error correction circuit of a correcting function; an address table for maintaining a table required for managing data stored in the above-mentioned nonvolatile memory, the above-mentioned address table having: an error table having a plurality of error records, the error records being Information about the physical block in which a read error has been detected by the error correction circuit, and information related to the read error; information indicating whether data has been written or erased for each physical block of the nonvolatile memory Item table: a logical-physical conversion table representing conversion information between a logical block address specified by the master device and a physical block address of the nonvolatile memory from the outside, and the above-mentioned arithmetic processing unit registers and The error record of the error table is updated to determine whether to use the physical block in which the read error has been detected.

Here, it is also possible that the above-mentioned address table further includes a bad block table that records information related to the address of the physical block that prohibits data writing and reading, and the error record of the above-mentioned error table includes: when the above-mentioned error correction circuit detects During the error of the data read from above-mentioned non-volatile memory, record represents the error block information of the address information of the physical block that error occurred; Record represents the error information of the information that above-mentioned error occurred; After an error, the data of the above-mentioned physical block is cleared, and the information of new data is written; it indicates that after the information is recorded in the above-mentioned error block clear information, a read error is detected again in the same physical block Error recurrence information. When the above-mentioned operation processing unit writes data in the above-mentioned non-volatile memory, it refers to the above-mentioned error table. When the above-mentioned error recording is performed, the information related to the address of the physical block in which the above-mentioned data is written is recorded in the above-mentioned bad block table.

Here, the error record in the error table may further include error page information in which an address of the physical page in which a read error has been detected by the error correction circuit is written.

Here, the arithmetic processing unit may record and update information in the error record of the error table only when the read error detected by the error correction circuit cannot be corrected by the error correction circuit.

Here, the arithmetic processing unit may record and update information in the error record of the error table only when the read error detected by the error correction circuit cannot be corrected by the error correction circuit.

Here, the address table may further include a bad block table that records information on addresses of physical blocks that are prohibited from writing and reading data, and the error record in the error table includes: During the error of the data read from above-mentioned non-volatile memory, the error block information of the information of the address of the physical block that record expression has occurred error; As the error counting information of the information of the number of times that read error occurrence; The error block clearing count information of the number of times that the wrong physical block has been physically cleared is read. When the arithmetic processing unit writes data in the non-volatile memory, it refers to the above error table. , when there is the above-mentioned error record in which the above-mentioned error block information is recorded, the above-mentioned error count information is compared with the above-mentioned error block clear information, the above-mentioned error block clear information indicates a predetermined number of times, and the value of the above-mentioned error count information is higher than the value of the above-mentioned error block clear When the information is large, information on the address of the physical block in which the data is written is recorded in the defective block table.

Here, the error record in the error table may further include error page information in which an address of the physical page in which a read error has been detected by the error correction circuit is written.

Here, in the arithmetic processing unit, if the error correction circuit detects a read error, the error record in the error table may be registered and updated irrespective of whether the error correction circuit can correct it or not.

Here, in the arithmetic processing unit, if the error correction circuit detects a read error, the error record in the error table may be registered and updated irrespective of whether the error correction circuit can correct it or not.

Here, the error record in the error table may include: error block information written in the address of the physical block whose read error is detected by the error correction circuit; error page information of an address of an erroneous physical page; an error bit count of information indicating the number of bits read out error, the above-mentioned operation processing unit using a value having an error bit number less than or equal to the number of error bits that can be corrected by the error correction circuit, and Predetermined correction threshold, read the data of the physical block corresponding to the error record of the above-mentioned error table whose error bit count information is greater than or equal to the above-mentioned correction threshold, so that the above-mentioned error correction circuit corrects the error of the read data, and converts the Corrected data is written to other physical blocks.

Here, the arithmetic processing unit may use a value equal to or less than the number of error bits that can be corrected by the error correction circuit when the data read process from the outside to the nonvolatile memory is not performed, and the error correction circuit may be used in advance. Determine the correction threshold, read the data of the physical block corresponding to the error record of the above-mentioned error table whose information of the above-mentioned error bit count is greater than or equal to the above-mentioned correction threshold, so that the above-mentioned error correction circuit corrects the error of the read data, and the correction The completed data is written to other physical blocks.

Here, the error record in the error table may include: error block information for recording information indicating the address of the physical block in which the error correction circuit detected a read error; Error page information of information on the address of the above-mentioned physical page; recording an error occurrence of information indicating that a read error has occurred with a value less than or equal to the number of error bits that can be corrected by the above-mentioned error correction circuit and greater than or equal to a predetermined correction threshold value information, the above-mentioned operation processing unit reads the data of the physical block corresponding to the error record of the above-mentioned error table that records the above-mentioned error occurrence information, causes the above-mentioned error correction circuit to correct the error of the read data, and writes the corrected data into other physical blocks.

Here, the arithmetic processing unit may read the data of the physical block corresponding to the error record of the error table in which the error occurrence information is recorded, when the processing of reading the data of the nonvolatile memory is not performed. , causing the error correction circuit to correct the error of the read data, and writing the corrected data into another physical block.

In order to solve this problem, a method for detecting a defective area of the present invention is a method for detecting a defective area of a nonvolatile memory device including a plurality of physical blocks as units of erasing, and the physical blocks have A nonvolatile memory composed of a plurality of physical pages as a writing unit; a memory controller including a function of detecting errors in read data from the above nonvolatile memory and correcting errors when they can be corrected an error correction circuit, an error table holding a plurality of error records, the error records are information related to the above-mentioned read error about the physical block in which a read error has been detected, and in the defective area detection method, in the read When data is used, the physical address is determined according to the logical address specified from the outside, and the data is read from the physical block corresponding to the above physical address. When there is a correctable error in the read data, the above error is corrected and output to the outside, and the above The physical address is registered in the error table above.

Here, it is also possible that when the data of the physical block whose physical address is registered in the above-mentioned error table is rewritten, the information indicating that the above-mentioned data is rewritten is registered in the above-mentioned error table, and when the data is read from the physical block in which the above-mentioned data is rewritten, When there is an error that can be corrected in the output data, correct the error and output it to the outside. At the same time, register the error recurrence information indicating that an error occurred after rewriting the above data into the above error table. Writing and reading of data are prohibited for the physical block in which the above-mentioned error recurrence information is registered.

Here, it is also possible that when the data of the physical block whose physical address is registered in the above-mentioned error table is rewritten, an error block clear count indicating the number of times the above-mentioned data has been rewritten is registered in the above-mentioned error table. When there is a correctable error in the data read from the physical block of the data, the error is corrected and output to the outside, and at the same time, the error count indicating the number of times the error occurred after the above data is rewritten is registered in the above error table, and the above error When the count indicates a predetermined value or more, writing and reading of data to and from the physical block in which the error count is registered is prohibited.

In order to solve this problem, a method for detecting a defective area of the present invention is a method for detecting a defective area of a nonvolatile memory device including a plurality of physical blocks as units of erasing, and the physical blocks have A nonvolatile memory composed of a plurality of physical pages as a writing unit; a memory controller including a function of detecting errors in read data from the above nonvolatile memory and correcting errors when they can be corrected an error correction circuit, an error table holding a plurality of error records, the error records are information related to the above-mentioned read error with respect to the physical block in which a read error has been detected, and the defective area detection method has: The logical address determines the physical address, and determines the step of determining the physical block of the read data; the data read step of reading the data from the above physical block; when there is a correctable error in the read data, correct the above error and output A data output step to the outside; a step of registering the number of errors in the above-mentioned error table with the physical address of the physical block where the above-mentioned correctable error has occurred and information related to the number of errors.

Here, there is a copying step of copying the data written in the physical block to another physical block when the information on the number of errors registered in the error table shows a predetermined value or more.

Here, the copying step may be performed between the data reading step and the data outputting step.

Here, the copying step may be performed when data writing and reading from the outside are not executed to the nonvolatile memory device.

Here, the copying step may be performed immediately after the nonvolatile memory device is powered on.

According to the present invention, by appropriately estimating a physical block assumed to have a high probability of error occurrence, it is possible to limit or avoid writing or reading data to or from the physical block, thereby providing a highly reliable nonvolatile memory device.

Description of drawings

FIG. 1 is a block diagram showing the configuration of a nonvolatile memory device according to a first embodiment.

FIG. 2 is a block diagram showing the internal structure of the flash memory.

FIG. 3 is a block diagram showing the internal structure of the physical block 201 .

FIG. 4 shows the structure of the BB table 112.

FIG. 5 shows the structure of the ECC error table 111. As shown in FIG.

Fig. 6 shows the ECC error record and changes of information stored in the ECC error record in the first embodiment.

Fig. 7 is a flow chart of reading in the first embodiment.

Fig. 8 is a flow chart of ECC error table registration in the first embodiment.

Fig. 9 is a flow chart of updating the ECC error table at the time of physical erasure in the first embodiment.

Fig. 10 shows the ECC error log of the second embodiment.

Fig. 11 is a flowchart showing the registration of the ECC error table in the second embodiment.

Fig. 12 shows the ECC error record and changes of information stored in the ECC error record in the third embodiment.

Fig. 13 is a flowchart of ECC error table registration in the third embodiment.

Fig. 14 is a flow chart of updating the ECC error table at the time of physical erasure in the third embodiment.

Fig. 15 is a flowchart of readout in the fourth embodiment.

Fig. 16 shows the occurrence status of progressive errors.

FIG. 17 is a block diagram showing the configuration of a nonvolatile memory device according to a fifth embodiment.

Fig. 18 is a block diagram showing the internal structure of the flash memory.

FIG. 19 is a block diagram showing the internal structure of the physical block 201 .

FIG. 20 shows the structure of the ECC error table 111.

Fig. 21 shows the ECC error log of the fifth embodiment.

Fig. 22 is a flow chart of reading in the fifth embodiment.

Fig. 23 is a flowchart of ECC error table registration in the fifth embodiment.

Fig. 24 is a flowchart of data correction copy processing in the fifth embodiment.

Fig. 25 is a flow chart of reading in the sixth embodiment.

Fig. 26 is a flowchart of data correction copy processing in the sixth embodiment.

(Description of Reference Signs)

101: memory card

102: storage controller

103: Flash memory

104: main interface

105: MPU

106: address table

107: Flash interface

108: buffer memory

109: ECC circuit

110: Logical physical conversion table

111: ECC error table

112: BB table

113: Item table

501: ECC error record

601: Bad Block

602: error message

603: Error block clear message

604: Error recurrence message

701: memory card

702: storage controller

703: Flash memory

704: Main interface

705: MPU

706: address table

707: Flash interface

708: buffer memory

709: ECC circuit

710: Logical-physical conversion table

711: ECC error table

712: Project table

801: ECC error record

1001: Error page

1201: Bad block

1202: Error count

1203: Error Block Clear Count

1601: Error Bit Count

Detailed ways

(Example 1)

FIG. 1 is a block diagram showing the configuration of a nonvolatile memory device according to a first embodiment. The memory card 101 includes a memory controller 102 and a flash memory 103 as a nonvolatile memory.

FIG. 2 is a block diagram showing the internal structure of the flash memory 103 . Here, a flash memory having a capacity of 1 Gbit will be described. The interior of the flash memory 103 is composed of 1024 physical blocks PB0 to PB1023. A physical block is the smallest unit of data erasing in the flash memory 103 . The capacity of one physical block is 128kB+4kB, which is not a power of 2 value but a capacity slightly larger than the power of 2. Here, 128kB+4kB is not expressed as 132kB to indicate that the capacity of data that can be written in one physical block is 128kB. On this basis, the ECC code or the physical block is written in the 4kB area. Management data such as logical address values.

Fig. 3 is a block diagram showing the internal structure of a physical block. Each physical block in the flash memory 103 includes 64 physical pages PP0 to PP63. A physical page is the minimum unit of data writing in the flash memory 103 . The capacity of a physical page is 2kB+64B. This expression is the same as the case of the above-mentioned physical block, which means that the data capacity that can be written in one physical page is 2kB, and management data including ECC is written in the remaining 64B.

The memory controller 102 has a host interface 104 , an address table 106 , a flash interface 107 , a buffer memory 108 , an ECC circuit 109 , and an MPU (small arithmetic unit) 105 . The host interface 104 controls an interface with a host device connected to the outside of the memory card 101 .

The address table 106 is a table having management information of data stored in the flash memory 103 , and includes a logical-physical conversion table 110 , an ECC error table 111 , an entry table 113 , and a BB (bad block) table 112 . These tables are maintained in volatile memory.

The logical-physical conversion table 110 is a table showing a correspondence relationship between addresses of logical blocks, which are logical addresses specified from the outside of the memory card 101 , and addresses of physical blocks, which are internal physical addresses of the flash memory 103 . The logical-physical conversion table 110 is used to obtain the physical address corresponding to the logical block from the logical address.

The ECC error table 111 has information such as the physical address of a physical block where a read error has occurred, the history of physical erasure of data, or the history of occurrence of a read error after physical erasure, and is used to detect inherently defective physical blocks.

The entry table 113 is a table having information indicating whether data has been written or erased for each physical block of the flash memory 103 in 1 bit. For example, a physical block whose data has been written is represented by a bit "0", and a physical block whose data has been cleared is represented by a bit "1".

FIG. 4 shows the structure of the BB table 112. The BB table 112 includes the same number of BB records i (i=0 to 1023) as there are physical blocks in the flash memory 103 . The BB record i is in one-to-one correspondence with the physical block, and has the address of the corresponding physical block. Furthermore, there is information represented by 1 bit as to whether or not the corresponding physical block is a defective block. In the BB record i, a physical block of a bad block is represented by a bit "0", and a non-defective physical block is represented by a bit "1". Here, the BB table 112 does not need to have BB records i for all physical blocks. It is also possible to have BB record i only for bad blocks.

The flash interface 107 writes the data of the buffer memory 108 into the flash memory 103 through the control of the MPU 105 described later, or writes the data of the flash memory 103 into the buffer memory 108, or clears the data of the flash memory 103 . The buffer memory 108 is a volatile memory for temporarily holding data during data writing and reading between an external host device and the flash memory 103 .

The ECC circuit 109 generates a code of ECC added to the write data transferred from the buffer memory 108 to the flash memory 103 . In addition, the ECC circuit 109 is an error correction circuit for performing an ECC operation on data read from the flash memory 103 to the buffer memory 108 to detect an error, and to correct the data in the buffer memory 108 when the error is a correctable error. .

The MPU 105 is a microcomputer that performs overall control of the memory controller 102 . It directly controls the host interface 104, the ECC circuit 109, the flash interface 107, and the address table 106 when writing and reading data with the host device. In particular, when there is an error in the read data, MPU 105 refers to information in ECC error table 111 in address table 106, and updates ECC error table 111 as necessary. As a result, if there is a physical block whose use should be prohibited, MPU 105 records the information of the physical block in BB record i of BB table 112 and updates BB table 112 . Furthermore, MPU 105 also updates the item table based on the contents of the updated BB table.

FIG. 5 shows the structure of the ECC error table 111. As shown in FIG. The ECC error table 111 is composed of 16 ECC error records #i of #0 to #F expressed in hexadecimal notation. FIG. 6 shows information groups of ECC error record #i and changes in information stored in ECC error record #i. Each ECC error record #i includes error block 601 , error occurrence information 602 , error block clear information 603 , and error recurrence information 604 . The error block 601 stores the physical address of the physical block 201 where a read error occurred. Error occurrence information 602 is information indicating that the first read error occurred. The error block clear information 603 is information indicating that the physical block 201 has been physically cleared after the first read error occurred. The error recurrence information 604 is information indicating that a read error occurred again in the same physical block despite physical erasure after the first read error occurred.

FIG. 7 is a flowchart of data reading in the nonvolatile memory device of this embodiment. When the external host device reads data from the memory card 101 , the external host device transmits a read command and a start address to the memory card 101 . After receiving the command and the start address, the host interface 104 notifies the MPU 105 of the reception. The flowchart in FIG. 7 shows the processing after receiving the notification.

The MPU 105 obtains the physical block address from the logical-physical conversion table 110 using the start address and the upper address portion corresponding to the 128 kB unit as a logical block address. The lower address portion corresponding to 128 kB or less is assumed to be the logical page address, which is the same as the logical page as it is. Next, the MPU 105 instructs the address of the physical block and the address of the physical page to be read to the flash memory interface 107, and reads data from the flash memory 103 (S701).

Next, the ECC circuit 109 determines whether or not a read error has occurred in the data read in S701 (S702). When no read error is detected, MPU 105 instructs host interface 104 to output data to an external master (S705). Then, as long as the reading is continued (S706), the address is incremented by the unit of reading, and at the same time, the loop goes to S701, and the data reading process is continued.

When a read error is detected in S702, the ECC circuit 109 judges whether the read error can be corrected (S703). If correctable, the read error is corrected (S704). After the reading error is corrected, the process moves to S705 to output the read data. If the read error cannot be corrected, the ECC error table is registered (S707), and the read process ends after the registration.

Here, the process of registering the ECC error table (S707) will be described using the flowchart of FIG. 8 . If the read error cannot be corrected, the MPU 105 searches the registration status of the ECC error table 111 (S801). Specifically, it is checked whether the physical address of the physical block in which the read error occurred matches the value of any error block 601 of the ECC error record #i.

Next, when there is no matching ECC error record #i in the search in S801, it is determined that there is no registration (S802). Next, MPU 105 newly registers error block 601 and error occurrence information 602 (S803). Fig. 6(b) shows the state after new login. In the error block 601, the address of the physical block where a read error occurred is written as a valid value. Information “1” indicating that a read error has occurred is written in error occurrence information 602 , and “0” is written in error block clear information 603 and error recurrence information 604 .

If there is a registration in S802, MPU 105 judges whether or not it is a read error that occurred after physical clearing (S804). If the error block clear information 603 of the ECC error record #i registered in the error block 601 is "0", the update of the ECC error record #i and the ECC error are not performed because it is not a read error that occurs after physical clearing. The registration of the table 111 ends the registration process. Even if a read error occurs, count the number of read errors after registering "1" in the error occurrence information 602, as long as the same data in the same block is read, it cannot be judged whether the error occurred accidentally or due to inherent defects. caused. As a result, the ECC error record #i is not updated, and the registration process ends.

In S804, if the error record #i is in the state shown in FIG. 6(c), the error block clear information 603 is "1", and it can be known that a read error occurred after physical erasure. At this time, as shown in FIG. 6(d), the log-in process ends after rewriting the error reoccurrence information 604 to "1" (S805). That is, the read error that should update the content of the ECC error record #i refers to a read error that occurs even in newly written data after the physical block in which a read error once occurred is physically cleared.

9 is a flowchart of ECC error table update and bad block registration at the time of physical erasing performed before data writing. When the external master device writes data in the memory card 101 , the external master device transmits a write command and a write start address to the memory card 101 . Upon receiving the command and the start address, the MPU 105 searches the registration status of the ECC error table 111 (S901). Specifically, it is checked whether the address of the physical block to be written matches the value of the error block 601 of the ECC error record.

In the search at S901, if there is no ECC error record #i that matches the physical block to be written, it is determined that there is no registration (S902), no registration is performed in the ECC error table 111, and the registration process ends. Conversely, when there is a matching ECC error record #i, it is judged that there is registration (S902). Also, when only the error occurrence information 602 is "1" and the error block clear information 603 and error reoccurrence information 604 are "0", only the error occurrence information 602 is recorded. It is judged to be the first physical erasing after a read error has occurred (S903). In this case, "1" is registered in the error block clear information 603, and the update of the ECC error table 111 is completed (S907).

Next, when the error occurrence information 602 and the error block clear information 603 are "1" and the error recurrence information 604 is "0", there is a record up to the error block clear information 603 (S904). From this, it can be seen that although an error occurred before, no error occurred in writing after physical erasing. That is, it is determined that the error that occurred first is an accidental error. At this time, the registration of the ECC error record #i is cancelled, and the update of the ECC error table 111 is completed (S906). Registration is canceled by making the value of the error block 601 of the ECC error record #i in FIG. 6( a ) an invalid value.

In addition, as shown in FIG. 6( d), when not only the error occurrence information 602 and the error block clear information 603, but also the error reoccurrence information 604 are all "1", it can be seen that a read error has occurred before. Read errors also occur in data written after the block has been physically erased. In this case, it is judged that it is an error caused by an inherent defect, and the physical block in which the error occurred is registered as a defective block (S905). Next, the registration of the ECC error record #i of the physical block is cancelled, and the update of the ECC error table 111 is completed (S906).

As described above, the bad block registration in S905 refers to registering bit "0" in the BB record i corresponding to the address of the physical block in the BB table 112 . Although the registration of bad blocks is completed through the registration of BB record i, this alone cannot limit the use of bad blocks. Therefore, bit “0” is registered in the entry table 113 for the physical block registered as bit 0 in the BB record i. If the bit "0" is registered in the entry table 113, the use of defective blocks can be limited because the defective blocks are treated as written blocks. In short, by registering a bit "0" in the entry table for a physical block registered as a defective block in the BB record i, it is possible to prevent the use of a defective block.

The feature of this embodiment is that only when the reading error that takes place can not be corrected, the registration and updating of the ECC error table is carried out, and the ECC error record in the ECC error table is recorded with the physical block address unit, and in the same physical block, Bad block registration is performed when two consecutive errors occur before and after physical clearing. In this embodiment, the ECC error table has information for judging whether an error that has occurred is accidental or caused by an inherent defect. That is, if the data of the physical block is physically erased after the first read error occurs, and no read error occurs in the newly written data, it can be determined that the first error is a sporadic error. If a read error still occurs in newly written data even if the data of the physical block is physically erased after the first read error occurs, it can be determined that the error is caused by an inherent defect. Thus, in this embodiment, it is possible to accurately determine whether an error is a sporadic error or an error caused by an inherent defect. In addition, based on this determination, there is an effect of reducing read errors by not using inherently defective physical blocks.

(Example 2)

FIG. 1 shows the structure of the nonvolatile memory device in this embodiment. The memory card 101 includes a memory controller 102 and a flash memory 103 as a nonvolatile memory. The components included in the memory controller 102 are the same as those described in the first embodiment.

FIG. 2 is a block diagram showing the internal structure of the flash memory 103. The interior of the flash memory 103 is composed of 1024 physical blocks PB0 to PB1023. FIG. 3 is a block diagram showing the internal structure of a physical block, and each physical block includes 64 physical pages PP0 to PP63. These are the same as those described in the first embodiment.

The ECC error table 111 shown in FIG. 5 includes a plurality of ECC error records #i, as described in the first embodiment.

Fig. 10 shows the structure of the ECC error record #i of this embodiment. In FIG. 10, an error page 1001 is provided in addition to the error block 601, error occurrence information 602, error block clear information 603, and error reoccurrence information 604 shown in FIG. 6 of the first embodiment. Since this error page 1001 has the address of the physical page in which the read error was detected as information, the ECC error record #i can be configured in units of physical pages.

Data reading in the nonvolatile memory device of this embodiment is performed according to the flowchart shown in FIG. 7, and the processing in each step except S707 is the same as that of the first embodiment. Here, using FIG. 11, the ECC error table registration in S707 performed when the error cannot be corrected in S703 will be described. First, the MPU 105 searches the registration status of the ECC error table 111, searches for an ECC error that has the address of the physical block in which the read error occurred in the error block 601, and has the address of the physical page in which the error occurred in the error page 1001. #i is recorded (S1101).

If there is no corresponding ECC error record #i in the search in S1101, MPU 105 judges that there is no ECC error record #i registered (S1102), and newly registers error occurrence information in ECC error record #i (S1103). In this registration, the address of the physical block containing the page in which the error occurred is written in the error block 601, "1" indicating that a read error has occurred is written in the error occurrence information 602, and the error occurred in the error page 1001. The physical page address of the page to complete. "0" indicating an initial value is registered in the error block clear information 603 and the error recurrence information 604 that are unnecessary for this registration.

When it is determined in S1102 that there is a registration, MPU 105 determines whether or not it is a read error after physical clearing (S1104). That is, if the error block clear information 603 of the registered ECC error record #i is "0", the MPU 105 judges that the physical clear has not yet been performed, and it is not a read error after the physical clear, and the update of the ECC error record #i is not performed. Finish. This determination is based on the fact that as long as the same data on the same physical page is read, no matter how many times a read error occurs, it cannot be determined whether it is a random error or an error caused by an inherent defect.

FIG. 9 is a flowchart showing updating of the ECC error table and registration of defective blocks during physical erasure, and will be described because the processing of S901 is different from that of the first embodiment. If the search in S901 is performed based on the physical block address which is the unit of physical clearing, several ECC error records #i having the same physical block address but different physical page addresses may be detected. That is, a plurality of ECC error records #i having the same value of the error block 601 and different values of the error page 1001 are retrieved (S901). Since the plurality of ECC error records #i detected in the order detected in S901 are to be processed in the next step, the processing after S902 is the same as that in the first embodiment.

In addition, the method of registering a bad block and the method of preventing the use of a bad block by registering in the item table are the same as those of the first embodiment.

The present embodiment is characterized in that an error page 1001 is provided in the structure of the ECC error record #i, and the ECC error record #i is newly registered for each physical page address. In this way, even if errors occur consecutively in the same physical block, it is possible to distinguish whether errors occurred in different physical pages or errors occurred in the same physical page, and it is possible to judge with high precision whether it is a sporadic error or an error. Errors caused by inherent badness.

In addition, in this embodiment, the page unit for reading is taken as the minimum unit of writing, that is, the physical page, and even if the reading unit of the configured system or the unit of ECC code is used, it is possible to compare the physical block unit. Error management with higher precision error management. It is also possible to register and update the ECC error table irrespective of whether or not the read error can be corrected.

(Example 3)

FIG. 1 shows the structure of the nonvolatile memory device in this embodiment. The memory card 101 includes a memory controller 102 and a flash memory 103 as a nonvolatile memory. The components included in the memory controller 102 are the same as those described in the first embodiment.

FIG. 2 is a block diagram showing the internal structure of the flash memory 103. The interior of the flash memory 103 is composed of 1024 physical blocks PB0 to PB1023. FIG. 3 is a block diagram showing the internal structure of a physical block, and each physical block includes 64 physical pages PP0 to PP63. These are the same as those described in the first embodiment.

The ECC error table 111 shown in FIG. 5 includes a plurality of ECC error records #i, as described in the first embodiment.

Fig. 12 shows the structure of the ECC error record #i of this embodiment. Fig. 12 shows the information group of the ECC error record #i and the change of the information stored in the ECC error record #i. The error block 1201 stores the physical address of the physical block where the error occurred. The error count 1202 stores the number of read errors that have occurred. If a read error occurs in the data newly written after the physical erasing of the physical block, the number of errors in the error count 1202 is incremented by 1. The error block clear count 1203 indicates the number of times physical clearing has been performed on a physical block in which a read error has occurred.

Data reading in the nonvolatile memory device of this embodiment is performed according to the flowchart shown in FIG. 7, and the processing in each step except S707 is the same as that of the first embodiment. Here, the ECC error table registration in S707 performed when the error cannot be corrected in S703 will be described.

Fig. 13 shows registration processing of the ECC error table. First, the MPU 105 searches the registration status of the ECC error table 111 (S1301). Specifically, it is a search for an ECC error record #i having a physical block address in which a read error has occurred in the error block 601 .

In the search in S1301, when there is no ECC error record #i whose physical address matches, MPU 105 judges that it is not registered (S1302), and newly registers ECC error record #i (S1303). Fig. 12(b) shows the state after new login. In the error block 1201, the address of the physical block where the read error occurred is written as a valid value. In the error count 1202, "1" indicating that a read error has occurred once is written. In the error block clear count 1203, "0" indicating that the number of times of physical erasure after the occurrence of an error is 0 is written.

When it is judged in S1302 that there is a registration, the MPU 105 refers to the registered ECC error record #i, and judges whether or not it is the first error that occurred after physical clearing (S1304). Specifically, the error count 1202 of the ECC error record #i detected in S1301 is compared with the error block clear count 1203 . If the error count 1202 is a value larger than the error block clear count 1203, it is determined that the immediately preceding update of the ECC error record #i is an increase in the error count 1202 due to the occurrence of a read error. Since no physical clearing is performed after the occurrence of a read error, the ECC error record #i is not updated, and the registration in the ECC error table 111 is completed. Once the error count 1202 is registered or updated, as long as the physical block 201 is not physically cleared, no matter how many read errors occur, it cannot be determined whether it is a sporadic error or an error caused by an inherent defect. Therefore, if the error count 1202 is a value larger than the error block clear count 1203, the error count 1202 will not be further increased.

Next, if the value of the error count 1202 and the error block clear count 1203 are the same, it is judged that the immediately preceding update of the ECC error record #i is an increase of the error block clear count 1203 caused by physical clear. Since the physical erasing was performed after the error occurred, MPU 105 judges that a read error has occurred after the physical erasing, and proceeds to S1305. In FIG. 12, the information of the error count 1202 is incremented by 1, and the update of the table is completed, such as changing from (c) to (d) and from (e) to (f). A read error that should update the content of the ECC error record #i refers to a read error that occurs even in newly written data after the physical block in which a read error once occurred is physically cleared.

FIG. 14 is a flowchart of updating the ECC error table at the time of physical erasure before data writing. First, the MPU 105 searches the registration status of the ECC error table 111 (S1401). Specifically, it is a search for an ECC error record having a physical block address of the flash memory 103 to be physically erased in the error block 1201 .

In the search at S1401, when there is no ECC error record #i whose physical address matches, the MPU 105 determines that there is no registration (S1402), and ends without updating the ECC error table 111 . When there is a corresponding ECC error record #i in the search in S1401, it is determined that there is registration (S1402).

Next, the MPU 105 refers to the ECC error record #i to determine whether or not an error after physical clearing has occurred (S1403). Specifically, the error count 1202 is compared with the error block clear count 1203, and if both are the same value, the immediately preceding update of the ECC error record #i is an increase in the physical block clear count 1203 caused by the physical clear , it is judged that no error has occurred after clearing. Therefore, it is judged that the read error occurring before the physical erasure is a sporadic error. After this determination, the MPU 105 deletes the registration of the ECC error record #i (S1404), and ends the update of the ECC error table 111. As shown in FIG. 12( a ), by setting the value of the error block 1201 to an invalid value, the registration can be canceled.

In addition, the error count 1202 of the ECC error record #i is compared with the error block clear count 1203, and if the error count 1202 is a value larger than the error block clear count 1203, it can be determined that the ECC error record #i is immediately before The update is an increase of the error count 1202 due to the occurrence of an error, and the cleared error occurred in S1403. The MPU 105 refers to the error count 1202 (S1405), and determines whether or not it is within a predetermined number of times. If it is within the predetermined number of times, since bad block registration is unnecessary, the value of the error block clear count 1203 of the ECC error table 111 is incremented by 1 (S1406), and the update of the ECC error table 111 is completed. If the number of errors exceeds the predetermined number of times in S1405, it is regarded as a physical block inherently defective, and defective block registration is performed. The bad block registration means that it is registered in the BB record i corresponding to the address of the physical block (S1407). After the registration of the bad block, the registration of the ECC error record #i of the physical block is deleted (S1404).

The method of registering bad blocks and the method of preventing the use of bad blocks by registering in the item table are the same as those of the first embodiment.

In the case of a storage device using a flash memory with a high occurrence frequency of sporadic bit errors such as a multi-valued flash memory, sporadic bit errors may occur consecutively before and after physical erasure in the same physical block or page. mistake. In this case, the physical block that is not inherently defective is registered as a bad block, and it is not appropriate to restrict the use of this physical block. Therefore, the present embodiment can arbitrarily set the number of times of occurrence of errors until a bad block is registered to be three or more. By setting the predetermined value of the number of times of error occurrence until a defective block is registered to a large value, it is possible to accurately detect an inherent defect.

In addition, the error page information of the physical block page may be recorded in the ECC error record #i of this embodiment, and the error table may be registered in units of physical pages. In addition, the registration and update of the ECC error table may be performed regardless of whether the read error can be corrected or not.

(Example 4)

FIG. 1 shows the structure of the nonvolatile memory device in this embodiment. The memory card 101 includes a memory controller 102 and a flash memory 103 as a nonvolatile memory. The components included in the memory controller 102 are the same as those described in the first embodiment.

FIG. 2 is a block diagram showing the internal structure of the flash memory 103. The interior of the flash memory 103 is composed of 1024 physical blocks PB0 to PB1023. FIG. 3 is a block diagram showing the internal structure of a physical block, and each physical block includes 64 physical pages PP0 to PP63. These are the same as those described in the first embodiment.

The ECC error table 111 shown in FIG. 5 includes a plurality of ECC error records #i, as described in the first embodiment.

FIG. 15 is a flowchart of data reading in the nonvolatile memory device of this embodiment. The processing in S1501 is the same processing as in S701 in the first embodiment.

After S1501, the ECC circuit 109 determines whether or not a read error has occurred in the read data (S1502). When no read error occurs, MPU 105 instructs host interface 104 to output data to an external master (S1506). Then, as long as the reading is continued (S1507), the address is incremented by the unit of reading, and at the same time, the loop goes to S1501, and the data reading process is continued.

It is determined whether a read error has occurred (S1502), and if a read error has occurred, the ECC error record #i is registered in the ECC error table 111 (S1503). When registration to the ECC error table 111 is completed, the ECC circuit 109 judges whether the read error can be corrected (S1504), and corrects the read error if correctable (S1505). After the reading error is corrected, the read data is output, and it is judged whether to continue reading the data (S1507). Also, when the read error cannot be corrected (S1504), the read is immediately terminated.

In the present embodiment, as long as a read error is detected, registration in the ECC error table 111 is performed regardless of whether the error can be corrected or not. The method of registering the ECC error table 111 is the same as that of the first embodiment, as shown in FIG. 8 .

The updating of the ECC error table and registration of bad blocks at the time of physical erasing before data writing are the same as those in the first embodiment, as shown in FIG. 9 .

The method of registering bad blocks and the method of preventing the use of bad blocks by registering in the item table are the same as those of the first embodiment.

In the case where the memory card is constituted by a flash memory 103 with a low occurrence frequency of sporadic bit errors such as a binary flash memory, the frequency of uncorrectable errors occurring twice consecutively before and after physical erasure is very low, and almost all errors can be corrected. Even errors caused by inherent defects can be corrected in most cases, so only when the registration of the ECC error table is performed when the errors cannot be corrected, the physical blocks having inherent defects cannot be accurately detected. On the other hand, in this embodiment, if a bit error is detected, the ECC error record #i is registered in the ECC error table regardless of whether the error can be corrected. It may also be desirable to limit the use of inherently bad physical blocks.

In addition, it is also possible to add and record error page information of a physical block page to the ECC error record #i of this embodiment, and register the error table in units of physical pages. In addition, the registration and update of the ECC error table may be performed regardless of whether the read error can be corrected or not.

(Example 5)

FIG. 16 shows how bit errors increase in accordance with the number of reads when data written in a certain physical block is repeatedly read. In the figure, the grid pattern indicates the number of erroneous bits that have occurred, and as the number of times of reading increases, the dotted line increases toward the number of bits that can be corrected by ECC, which indicates the error correction capability of the ECC circuit. Such an error occurs because a bit written in a memory cell changes due to a voltage applied to the memory cell for data reading or the like. In this embodiment, such an error is called a progressive error.

The position indicated by E/W in FIG. 16 indicates erasing and writing of data, which means that after erasing the data of the physical block, new data is written in the same physical block. There is no progressive error immediately after E/W, but if the number of data readouts is increased, the number of progressive error bits gradually increases, so there is no margin in the error correction capability of the ECC circuit. If data reading is repeated in this state, an error of the number of bits exceeding the correction capability of the ECC circuit will occur, which is not preferable. To this end, the correction threshold is set to be less than or equal to the number of bits that can be corrected by the ECC circuit, and if an error greater than or equal to the number of bits of the correction threshold is detected in the data read from a certain physical block, the detected error is corrected , and write the corrected data into other physical blocks. By doing so, progressive errors are temporarily eliminated, data security is ensured, and at the same time, a margin is restored to the error correction capability of the ECC circuit. In addition, in this embodiment, both the number of bits capable of error correction and the correction threshold of the ECC circuit are set to 4 bits. In this embodiment, a method for coping with the above situation will be described below.

Hereinafter, this embodiment will be described. FIG. 17 is a block diagram showing the configuration of the nonvolatile memory device of this embodiment. The memory card 701 includes a memory controller 702 and a flash memory 703 as a nonvolatile memory.

FIG. 18 is a block diagram showing the internal structure of the flash memory 703 . Here, a flash memory having a capacity of 1 Gbit will be described. The interior of the flash memory 703 is composed of 1024 physical blocks PB0 to PB1023. A physical block is the smallest unit of data erasing in the flash memory 703 . A physical block capacity is represented by 128kB+4kB. This means that the data capacity of one physical block is 128 kB, and management data such as an ECC code or a logical address value of the physical block is written in an area of 4 kB.

Fig. 19 is a block diagram showing the internal structure of a physical block. Each physical block in the flash memory 703 includes 64 physical pages PP0 to PP63. A physical page is the smallest unit of data writing in the flash memory 703 . The capacity of a physical page is 2kB+64B. This means that the capacity of data that can be written in one physical page is 2kB, and management data including ECC is written in the remaining 64B.

The memory controller 702 has a host interface 704 , an address table 706 , a flash interface 707 , a buffer memory 708 , an ECC circuit 709 , and an MPU (small arithmetic unit) 705 . The host interface 704 controls an interface with a host device connected to the outside of the memory card 701 .

The address table 706 is a table having management information of data stored in the flash memory 703 , and includes a logical-physical conversion table 710 , an ECC error table 711 , and an entry table 712 . These tables are maintained in volatile memory.

The logical-physical conversion table 710 is a table showing correspondence between logical block addresses that are logical addresses specified from outside the memory card 701 and physical block addresses that are physical addresses inside the flash memory 703 . The logical-physical conversion table 710 is used to obtain the physical address corresponding to the logical block from the logical address.

The ECC error table 711 has information such as the physical address of a physical block where a read error has occurred, the history of physical erasure of data, or the history of occurrence of a read error after physical erasure, and is used to detect inherently defective physical blocks.

The entry table 712 is a table having information indicating whether data has been written or erased to each physical block of the flash memory 703 by 1 bit. For example, a physical block whose data has been written is represented by a bit "0", and a physical block whose data has been cleared is represented by a bit "1".

The flash interface 707 writes the data of the buffer memory 708 into the flash memory 703 through the control of the MPU 705 described later, or writes the data of the flash memory 703 into the buffer memory 708, or clears the data of the flash memory 703 . The buffer memory 708 is a volatile memory for temporarily holding data when writing and reading data between an external host device and the flash memory 703 .

The ECC circuit 709 generates a code of ECC added to the write data transferred from the buffer memory 708 to the flash memory 703 . In addition, the ECC circuit 709 is an error correction circuit that performs an ECC operation on data read from the flash memory 703 to the buffer memory 708 to detect an error, and corrects the data in the buffer memory 708 when the error is a correctable error. .

The MPU 705 is a microcomputer that performs overall control of the memory controller 702 . When writing and reading data with the host device, it directly controls the host interface 704, ECC circuit 709, flash interface 707, and address table 706. In particular, when there is an error in the read data, the MPU 705 refers to the information in the ECC error table 711 in the address table 706, and updates the ECC error table 711 as necessary. Furthermore, the MPU 705 also updates the item table based on the contents of the updated BB table.

FIG. 20 shows the structure of the ECC error table 711. The ECC error table 711 is composed of 16 ECC error records #i of #0 to #F expressed in hexadecimal notation.

Fig. 21 shows the structure of the ECC error record #i of this embodiment. The ECC error record #i of this embodiment includes an error block 601 storing the address of the physical block in which the error occurred and an error page 1001 storing the address of the physical page in which the error occurred, as well as an error record for storing the bit number of the error occurred. Bit count 1601. This error bit count 1601 has the number of bits that have occurred read errors as information, and the degree of the bit errors that have occurred is indicated by ECC error record #i.

FIG. 22 is a flowchart of data reading in the nonvolatile memory device of this embodiment. The MPU 705 instructs the address of the physical block and the address of the physical page to be read to the flash memory interface 707, and reads data from the flash memory 703 (S1701). After S1707, the ECC circuit 709 determines whether or not a read error has occurred in the read data (S1702). When no read error occurs, the MPU 705 instructs the host interface 704 to output data to the external master (S1707). Then, as long as the reading is continued (S1708), the address is incremented by the unit of reading, and at the same time, the loop goes to S1701, and the data reading process is continued.

When a read error has occurred in the determination in S1702, registration to the ECC error table 711 is performed (S1703). When registration to the ECC error table 711 is completed, the ECC circuit 709 judges whether or not the read error is equal to or less than 4 bits that can be corrected (S1704). If the read error cannot be corrected (S1704), the data read is immediately terminated.

If correctable, the read error is corrected (S1705). After the reading error is corrected, data correction copy processing is performed (S1706), and the read data is output (S1707). Then, it is determined whether to continue reading (S1708).

In this embodiment, if a read error is detected, it is registered in the ECC error table irrespective of whether it can be corrected or not. Here, the process of registering the ECC error table (S1703) will be described using the flowchart of FIG. 23 .

When a read error is detected, the MPU 705 searches the registration status of the ECC error table 711 (S1801). Specifically, it is checked whether the physical address of the physical block and the physical page in which the read error occurred matches the values of the error block 601 and the error page 1001 of any ECC error record #i in the ECC error table 711 .

Next, when there is no corresponding ECC error record #i in the search in S1801, it is determined that there is no registration (S1802). Next, each value of the error block 601, the error page 1002, and the error bit count 1603 is newly registered in the empty ECC error record #i (S1803). At this time, if an error of 5 bits or more that exceeds the correction capability of the ECC circuit 709 occurs, the error bit count registered in the ECC error record #i cannot be determined. value. For example, if the maximum correction capability of the ECC circuit 709 is 4 bits, 5 can be registered as a value exceeding 4 bits.

When registration of ECC error record #i is detected in S1802, MPU 705 determines whether or not the error bit count of the error occurring this time is larger than the error bit count of ECC error record #i (S1804). The error bit count 1601 of the registered ECC error record #i is compared with the error bit count currently being read, and if the bit count has not increased, the ECC error record is not updated and the process ends. When increasing, the error bit count 1601 is rewritten to the increased value, and registration of the ECC error table is completed (S1805).

Next, the data correction copy process (S1706) will be described using the flowchart of FIG. 24 . After the correction of the correctable error (S1705), the MPU 705 judges whether it is possible to continue reading the data of the physical page read this time in the future. That is, the purpose is to determine whether there is a high possibility that an uncorrectable bit error will occur when data reading is continued in the future, and to perform appropriate processing.

First, the value of the error bit count 1601 is acquired from the ECC error record #i (S1901). Next, it is determined whether or not the acquired error bit count is greater than or equal to the correction threshold value of 4 bits (S1902). If the error bit count is less than the correction threshold of 4 bits, it is judged that an uncorrectable read error will not be reached immediately even if the number of error bits increases in the future, and the data correction copy process is terminated.

When the error bit count is 4 bits, since it is equal to the correction threshold value, writing of corrected data is performed (S1903). Specifically, the MPU 705 writes the corrected data existing in the buffer memory 708 to an arbitrary physical block of the flash memory 703, for example. In this case, the physical block into which data is written is a physical block other than the physical block from which the data has been read. Finally, the registration of the ECC error record #i for the physical block in which the error occurred is deleted (S1904).

As above, it is judged that the data of the physical page whose error bit count is greater than or equal to the correction threshold has the possibility of developing into an uncorrectable read error in the future, corrects it during the correctable period, and writes the corrected data to physical pages of other physical blocks.

In this embodiment, when the number of bit errors that occur is 5 bits or 6 bits, etc., exceeding the correction capability of the ECC circuit, and the error cannot be corrected, the data correction copying process is not performed (S1706). When the error can be corrected, when the number of bits of the error is within the correctable range of the ECC circuit 709 and is greater than or equal to 4 bits of the correction threshold, write the error-corrected data into other physical blocks of the flash memory 103 .

In addition, here, the error bit count 1601 is set in the ECC error record #i of the ECC error table 711, but it is not limited thereto, as long as it indicates the degree of error. For example, it is easily conceivable that the effect of the present invention can be achieved by using a flag as error occurrence information indicating whether or not the correction threshold value is greater than the specific number of bits. Furthermore, registration in the ECC error table may be performed only when a correctable error of equal to or greater than the correction threshold occurs.

In addition, in this embodiment, since an ECC circuit capable of bit correction is assumed, the error bit count 1601 is used. However, when an error correction circuit capable of symbol correction such as Reed-Solomon code is assumed instead of bit correction, it is necessary to use information on the number of symbols in which errors occurred as error symbol counts instead of error codes. Bit count.

(Example 6)

FIG. 17 shows the structure of the nonvolatile memory device in this embodiment. The memory card 701 includes a memory controller 702 and a flash memory 703 as a nonvolatile memory. The components included in the memory controller 702 are the same as those described in the fifth embodiment.

FIG. 18 is a block diagram showing the internal structure of the flash memory 103. The interior of the flash memory 703 is composed of 1024 physical blocks PB0 to PB1023. FIG. 19 is a block diagram showing the internal structure of a physical block, and each physical block in the flash memory 703 includes 64 physical pages PP0 to PP63. These are the same as those described in the fifth embodiment. As shown in FIG. 20 , the ECC error table 711 includes a plurality of ECC error records #i. In addition, the structure of the ECC error record #i of this embodiment is as shown in FIG. 21 . In addition to the error block 601 storing the address of the physical block in which the error occurred and the error page 1001 storing the address of the physical page in which the error occurred, ECC error record #i also includes an error bit count 1601 storing the number of bits of the error occurred. . These are the same as the fifth embodiment.

FIG. 25 is a flowchart of data reading in the nonvolatile memory device of this embodiment. First, the address of the physical block and the address of the physical page to be read are instructed to the flash memory interface 707, and data is read from the flash memory 703 (S2001). After S2001, the ECC circuit 709 determines whether or not a read error has occurred in the read data (S2002). When no read error occurs, the MPU 705 instructs the host interface 704 to output data to the external master (S2006). Then, as long as the reading is continued (S2007), the address is incremented by the unit of reading, and at the same time, the loop goes to S2001, and the processing of data reading is continued.

When it is determined that there is a read error (S2002), it is determined whether the error can be corrected (S2003). When it is determined that correction is impossible, the readout process is immediately terminated.

When it is judged that it can be corrected, the registration of the ECC error table is performed (S2004). Here, the ECC error table is registered in the same manner as the processing described in FIG. 23 of the fifth embodiment. After registering the ECC error table, errors are corrected in the buffer memory 708 (S2005), and the MPU 705 instructs the host interface 704 to output data to an external master (S2006). Then, as long as the read is continued (S2007), the address is incremented by the read unit, and at the same time, the loop goes to S2001 to perform the read process.

In this embodiment, the data correction copy processing performed in the fifth embodiment is not included in the flow chart of data readout. This is because, in this embodiment, data is not written into the flash memory 703 during the data read process. In general, the writing time of a flash memory is longer than the reading time, and therefore, if such time-consuming writing processing is performed during data reading, the processing performance will be reduced. Therefore, writing to the flash memory 703 is not performed during data reading.

Therefore, in this embodiment, the data correction copy processing is performed in idle time when no other processing is performed. The so-called idle time refers to the period during which data writing and reading from the outside of the memory card 701 are not performed, or after the memory card 701 is powered on until the writing and reading of data from the outside of the memory card 701 is performed. period until processing.

The data correction copy process performed during idle time will be described using the flowchart of FIG. 26 . The MPU 705 searches the error count of the ECC error table 711 during idle time, and selects the ECC error record #i whose error bit count 1601 is 4 bits or more equal to or greater than the correction threshold (S2101). At this time, if there is no corresponding error record (S2102), the data correction copying process ends.

When there is a corresponding error record #i, the addresses of the physical block and the physical page are obtained from the error block 601 and the error page 1001 of the error record #i (S2103). Then, the data belonging to the acquired address is read to the buffer memory 708 (S2104). Next, the error is corrected by the ECC circuit 109 (S2105), and the corrected data is written into an arbitrary physical block of the flash memory 703 (S2106). At this time, the physical block to which data is written is a physical block other than the physical block registered in the error record #i. Finally, the registration of the corresponding error record #i is deleted, and the process ends (S2107).

As described above, since the data of the physical page with the error bit count greater than or equal to the correction threshold is judged to have the possibility of developing into an uncorrectable read error in the future, the error correction is performed using the idle time as described above, and the The corrected data is written into physical pages of other physical blocks. In this way, if data written once is repeatedly read, defective bits increase, but uncorrectable read errors can be avoided by correcting the data and rewriting it to another physical block.

In this embodiment, when the generated bit error is uncorrectable, since the registration of the ECC error table is not performed, the data correction copy process is not performed either. It is also possible that only when an error occurs when the data of a certain physical page is read, and the number of error bits of the error is within the range that can be corrected by the ECC circuit 709 and exceeds the correction threshold, other physical pages in the flash memory 703 Error-corrected data is written in the block and used for reading, so that data from the physical page does not need to be read in the future.

In addition, here, the error bit count 1601 is set in the ECC error record #i of the ECC error table 711, but it is not limited thereto, as long as it indicates the degree of error. For example, it is easily conceivable that the effect of the present invention can be achieved by using a flag as error occurrence information indicating whether or not a correction threshold value has been exceeded, even if the number of bits is not specific. Furthermore, registration in the ECC error table may be performed only when a correctable error greater than or equal to the correction threshold occurs.

In addition, in this embodiment, the error bit count 1601 is used because an ECC circuit capable of bit correction is assumed. On the other hand, in the case of an error correction circuit capable of symbol correction such as Reed-Solomon code instead of bit correction, it is necessary to use information on the number of symbols in which errors occurred as the error symbol count instead of the error bit count.

Industrial availability

The nonvolatile memory device of the present invention can reduce read errors by detecting inherent defects of the nonvolatile memory and restricting the use of the block in the future. It is used in a memory card system of permanent memory, for example, a storage device for storing still images of a digital camera.

Claims (26)

1. A non-volatile storage device comprising a non-volatile memory and a storage controller, wherein the non-volatile storage device is characterized in that, The nonvolatile memory includes a plurality of physical blocks as units of erasing, and the physical block has a plurality of physical pages as units of writing, The above storage controllers have: An arithmetic processing unit for performing overall control inside the storage controller; An error correction circuit having a function of detecting an error in data read from the above-mentioned nonvolatile memory and a function of correcting the error when the error can be corrected; maintaining an address table of a table necessary for managing data held in the above-mentioned nonvolatile memory, The address table of the memory controller above has: an error table having a plurality of error records, said error records being information related to said read error with respect to a physical block in which a read error has been detected by said error correction circuit; A bad block table that records information related to addresses of physical blocks that prohibit data writing and reading; There is an item table for each physical block of the above-mentioned non-volatile memory, whether the data is written or cleared; a logical-physical conversion table representing conversion information between a logical block address externally specified by the master device and a physical block address of the nonvolatile memory, The error record of the above error table has: When the above-mentioned error correction circuit detects an error in the data read from the above-mentioned non-volatile memory, recording error block information representing information of an address of a physical block where an error has occurred; Log an error message indicating that the above error has occurred; Recording error block clearing information indicating that the information of the above-mentioned physical block has been cleared after the above-mentioned error occurred; Error recurrence information indicating that a read error was detected again in the same physical block after information was recorded in the above error block clear information, The arithmetic processing unit registers and updates the error record of the error table based on the error detection from the error correction circuit, and when writing data in the non-volatile memory, refers to the error table, and when the physical When there is the above-mentioned error record in which the above-mentioned error block information and the above-mentioned error recurrence information are recorded, information related to the address of the physical block in which the above-mentioned data is written is recorded in the above-mentioned defective block table, and it is determined whether to use the Bad physical block. 2. The non-volatile memory device according to claim 1, wherein: The error record in the error table further includes error page information in which an address of the physical page in which a read error has been detected by the error correction circuit is written. 3. The non-volatile memory device according to claim 1, wherein: The arithmetic processing unit records and updates information in the error record of the error table only when the read error detected by the error correction circuit cannot be corrected by the error correction circuit. 4. The non-volatile memory device according to claim 2, wherein: The arithmetic processing unit records and updates information in the error record of the error table only when the read error detected by the error correction circuit cannot be corrected by the error correction circuit. 5. The non-volatile memory device according to claim 1, wherein: The information indicating that an error has occurred recorded in the above error message is the number of times an error occurred, The information recorded in the above-mentioned error block clearing information indicating that the above-mentioned physical block has been cleared is the number of times that the above-mentioned physical block has been physically cleared, When the arithmetic processing unit writes data in the nonvolatile memory, referring to the error table, when there is the error record in which the error block information and the error recurrence information are recorded with respect to the physical block in which the data is written, and Comparing the above-mentioned number of times of occurrence of errors with the above-mentioned error block clear information, and the above-mentioned error block clear information indicates a predetermined number of times, and when the value of the above-mentioned number of times of error occurrence is greater than the above-mentioned error block clear information, in the above-mentioned bad block table Information related to the address of the physical block in which the above-mentioned data is written is recorded. 6. The non-volatile memory device according to claim 5, wherein: The error record in the error table further includes error page information in which an address of the physical page in which a read error has been detected by the error correction circuit is written. 7. The non-volatile memory device according to claim 5, wherein: In the above operation processing unit, If the error correction circuit detects a read error, an error record in the error table is registered and updated regardless of whether the error correction circuit can correct it. 8. The non-volatile memory device according to claim 6, wherein: In the above operation processing unit, If the error correction circuit detects a read error, an error record in the error table is registered and updated regardless of whether the error correction circuit can correct it. 9. A non-volatile storage device comprising a non-volatile memory and a storage controller, wherein the non-volatile storage device is characterized in that The nonvolatile memory includes a plurality of physical blocks as units of erasing, and the physical block has a plurality of physical pages as units of writing, The above storage controllers have: An arithmetic processing unit for performing overall control inside the storage controller; An error correction circuit having a function of detecting an error in data read from the above-mentioned nonvolatile memory and a function of correcting the error when the error can be corrected; maintaining an address table of a table necessary for managing data held in the above-mentioned nonvolatile memory, The address table of the memory controller above has: an error table having a plurality of error records, said error records being information related to said read error with respect to a physical block in which a read error has been detected by said error correction circuit; There is an item table for each physical block of the above-mentioned non-volatile memory, whether the data is written or cleared; a logical-physical conversion table representing conversion information between a logical block address externally specified by the master device and a physical block address of the nonvolatile memory, The error record of the above error table has: The error block information of the address of the physical block whose read error is detected by the above-mentioned error correction circuit is written; The error page information of the address of the physical page whose read error is detected by the above-mentioned error correction circuit is written; record an error bit count indicating the information of the above-mentioned number of read-out errors, The arithmetic processing unit registers and updates the error record in the error table according to the error detection from the error correction circuit, and uses a predetermined correction threshold to read out the error table whose error bit count information is greater than or equal to the correction threshold. The error records the data of the corresponding physical block, so that the above-mentioned error correction circuit corrects the error of the read data, and writes the corrected data into other physical blocks, wherein the above-mentioned correction threshold is less than or equal to the above-mentioned The value of the number of erroneous bits corrected by the error correction circuit. 10. The non-volatile memory device according to claim 9, wherein: When the above-mentioned operation processing unit is not performing the data read process from the outside to the above-mentioned non-volatile memory, using a predetermined correction threshold value, read out the information of the above-mentioned error bit count greater than or equal to the above-mentioned error table. Misrecord the data of the corresponding physical block, so that the above-mentioned error correction circuit corrects the error of the read data, and writes the corrected data into other physical blocks, wherein the correction threshold is less than or equal to the The value of the number of errored bits corrected by the error circuit. 11. A memory controller for controlling data reading and writing in a nonvolatile memory having a plurality of physical blocks as a unit of erasing, and said physical block having a plurality of physical pages as a unit of writing, The memory controller is characterized in that it has: An arithmetic processing unit for performing overall control inside the storage controller; An error correction circuit having a function of detecting an error in data read from the above-mentioned nonvolatile memory and a function of correcting the error when the error can be corrected; maintaining an address table of a table necessary for managing data held in the above-mentioned nonvolatile memory, The above address table has: an error table having a plurality of error records, said error records being information related to said read error with respect to a physical block in which a read error has been detected by said error correction circuit; A bad block table that records information related to addresses of physical blocks that prohibit data writing and reading; There is an item table for each physical block of the above-mentioned non-volatile memory, whether the data is written or cleared; a logical-physical conversion table representing conversion information between a logical block address externally specified by the master device and a physical block address of the nonvolatile memory, The error record of the above error table has: When the above-mentioned error correction circuit detects an error in the data read from the above-mentioned non-volatile memory, recording error block information representing information of an address of a physical block where an error has occurred; Log an error message indicating that the above error has occurred; Recording error block clearing information indicating that the information of the above-mentioned physical block has been cleared after the above-mentioned error occurred; Error recurrence information indicating that a read error was detected again in the same physical block after information was recorded in the above error block clear information, The arithmetic processing unit registers and updates the error record of the error table based on the error detection from the error correction circuit, and when writing data in the non-volatile memory, refers to the error table, and when the physical When there is the above-mentioned error record in which the above-mentioned error block information and the above-mentioned error recurrence information are recorded, information related to the address of the physical block in which the above-mentioned data is written is recorded in the above-mentioned bad block table, and it is determined whether to use the Bad physical block. 12. The storage controller of claim 11, wherein The error record of the error table further includes error page information in which an address of the physical page in which a read error has been detected by the error correction circuit is written. 13. The memory controller of claim 11, wherein In the above operation processing unit, Only when the read error detected by the error correction circuit cannot be corrected by the error correction circuit, information is recorded and updated in the error record of the error table. 14. The memory controller of claim 12, wherein In the above operation processing unit, Only when the read error detected by the error correction circuit cannot be corrected by the error correction circuit, information is recorded and updated in the error record of the error table. 15. The storage controller of claim 11, wherein The information indicating that an error has occurred recorded in the above error message is the number of times an error occurred, The information recorded in the above-mentioned error block clearing information indicating that the above-mentioned physical block has been cleared is the number of times that the above-mentioned physical block has been physically cleared, When the arithmetic processing unit writes data in the nonvolatile memory, referring to the error table, when there is the error record in which the error block information and the error recurrence information are recorded with respect to the physical block in which the data is written, and Comparing the above-mentioned number of times of occurrence of errors with the above-mentioned error block clear information, and the above-mentioned error block clear information indicates a predetermined number of times, and when the value of the above-mentioned number of times of error occurrence is greater than the value of the above-mentioned error block clear information, in the above-mentioned bad block table Information related to the address of the physical block in which the above-mentioned data is written is recorded. 16. The memory controller of claim 15, wherein The error record of the error table further includes error page information in which an address of the physical page in which a read error has been detected by the error correction circuit is written. 17. The storage controller of claim 15, wherein In the above operation processing unit, If the error correction circuit detects a read error, an error record in the error table is registered and updated regardless of whether the error correction circuit can correct it. 18. The memory controller of claim 16, wherein In the above operation processing unit, If the error correction circuit detects a read error, an error record in the error table is registered and updated regardless of whether the error correction circuit can correct it. 19. A memory controller for controlling reading and writing of data in a nonvolatile memory having a plurality of physical blocks as units of erasing, wherein said physical block has a plurality of physical pages as units of writing, The memory controller is characterized in that it has: An arithmetic processing unit for performing overall control inside the storage controller; An error correction circuit having a function of detecting an error in data read from the above-mentioned nonvolatile memory and a function of correcting the error when the error can be corrected; maintaining an address table of a table necessary for managing data held in the above-mentioned nonvolatile memory, The address table of the memory controller above has: an error table having a plurality of error records, said error records being information related to said read error with respect to a physical block in which a read error has been detected by said error correction circuit; There is an item table for each physical block of the above-mentioned non-volatile memory, whether the data is written or cleared; a logical-physical conversion table representing conversion information between a logical block address externally specified by the master device and a physical block address of the nonvolatile memory, The error record of the above error table has: The error block information of the address of the physical block whose read error is detected by the above-mentioned error correction circuit is written; The error page information of the address of the physical page whose read error is detected by the above-mentioned error correction circuit is written; record an error bit count indicating the information of the above-mentioned number of read-out errors, The arithmetic processing unit registers and updates the error record in the error table according to the error detection from the error correction circuit, and uses a predetermined correction threshold to read out the error table whose error bit count information is greater than or equal to the correction threshold. The error records the data of the corresponding physical block, so that the above-mentioned error correction circuit corrects the error of the read data, and writes the corrected data into other physical blocks, wherein the above-mentioned correction threshold is less than or equal to the above-mentioned The value of the number of erroneous bits corrected by the error correction circuit. 20. The memory controller of claim 19, wherein When the above-mentioned operation processing unit is not performing the data read process from the outside to the above-mentioned non-volatile memory, using a predetermined correction threshold value, read out the information of the above-mentioned error bit count greater than or equal to the above-mentioned error table. Misrecord the data of the corresponding physical block, so that the above-mentioned error correction circuit corrects the error of the read data, and writes the corrected data into other physical blocks, wherein the correction threshold is less than or equal to the The value of the number of errored bits corrected by the error circuit. 21. A method for detecting a defective area, used in a nonvolatile storage device, the nonvolatile storage device having: a plurality of physical blocks as units of erasing, said physical block having a plurality of physical blocks as units of writing A nonvolatile memory composed of pages; a memory controller including an error correction circuit having a function of detecting an error in read data from the nonvolatile memory and a function of correcting an error when the error can be corrected; holding a plurality of An error table of an error record, the error record is information related to the above-mentioned read error about a physical block in which a read error has been detected, and the method for detecting a defective area is characterized in that When reading data, determine the physical address according to the logical address specified from the outside, read data from the physical block corresponding to the above physical address, If there is a correctable error in the read data, correct the error and output it to the outside, register the above physical address in the above error table, and When the data of the physical block whose physical address is registered in the above-mentioned error table is rewritten, information indicating that the above-mentioned data has been rewritten is registered in the above-mentioned error table, When there is a correctable error in the data read from the physical block in which the above data has been rewritten, the error is corrected and output to the outside, and error recurrence information indicating that an error has occurred after rewriting the above data is registered in the above error table, Data writing and reading are prohibited for the physical block in which the error recurrence information is registered in the error table. 22. The defective area detection method according to claim 21, characterized in that, The information indicating rewriting registered in the above-mentioned error table is the number of times of rewriting, The error recurrence information registered in the above error table is the number of times the error occurred after rewriting the data, When the value of the error recurrence information indicates a predetermined value or more, writing and reading of data to and from the physical block registered in the error table are prohibited. 23. A method for detecting a defective area, used in a nonvolatile storage device, the nonvolatile storage device having: a plurality of physical blocks as units of erasing, the physical block having a plurality of physical blocks as units of writing A nonvolatile memory composed of pages; a memory controller including an error correction circuit having a function of detecting an error in read data from the above nonvolatile memory and a function of correcting an error when it can be corrected; storing a plurality of An error table of an error record, the error record is information related to the above-mentioned read error about a physical block in which a read error has been detected, and the method for detecting a bad area is characterized in that it has: A step of determining a physical address based on a logical address specified from outside, and determining a physical block from which data is read; A data reading step of reading data from the physical block; When there is a correctable error in the read data, the error is corrected and output to an external data output step; The physical address of the physical block of the above-mentioned error that can be corrected and the information relevant to the error number are registered in the error bit number registration steps in the above-mentioned error table: In the copying step, when the information on the number of error bits registered in the error table shows a predetermined value or more, the data written in the physical block is copied to another physical block. 24. The defective area detection method according to claim 23, characterized in that, The copying step is performed between the data reading step and the data outputting step. 25. The defective area detection method according to claim 23, characterized in that, The copying step is performed when data writing and reading from the outside are not performed on the nonvolatile memory device. 26. The defective area detection method according to claim 25, characterized in that, The copying step is performed immediately after the nonvolatile memory device is powered on.

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