CN101242169A - Device and method for generating multi-phase clock pulse signal by ring oscillator - Google Patents

Abstract

An apparatus and method for generating multi-phase clock signals with a ring oscillator, the apparatus comprising: a first stage phase mixing module comprising a plurality of differential operational amplifier phase mixing circuits, each of which receives 2 input signals, and an output signal whose phase is interpolated between the two input signals; and a second-stage phase mixing module including a plurality of inverter phase mixing circuits, each of which receives the two signals output from the first-stage phase mixing module as input signals and outputs a clock signal having a phase interpolated between the two signals output from the first-stage phase mixing module. The method of the invention comprises the following steps: using a ring oscillator to provide at least two non-full wobble signals; mixing the phases of two non-full swing signals generated by a ring oscillator using a differential operational amplifier phase mixing circuit; and generating the multi-phase clock pulse signal with the interpolated phase using an inverter phase mixing circuit.

Description

Device and method for generating multi-phase clock pulse signal by ring oscillator

technical field

The present invention relates to a high-frequency multi-phase ring oscillator, especially a new device and method for generating a high-frequency multi-phase oscillator by means of interpolation of non-full swing signals.

Background technique

A multi-phase oscillator (MPO) plays an important role in many data transmission applications, and many methods have been proposed to realize the multi-phase oscillator circuit. For example, a ring oscillator is an oscillator with an odd number of inverters connected in series. Because the odd number of levels is connected in series, the output signal of the inverter will be at a high level. (high)/low (low) oscillation. However, the traditional ring oscillator configuration can only generate an odd number of multi-phase signals; another problem with the ring oscillator is that too many inverters are connected in series in the ring oscillator, which will lead to inability to obtain High frequency oscillation.

U.S. Patent No. 5,592,126 discloses a multi-phase output oscillator, which includes some oscillator circuits connected in series to form a ring structure, wherein each oscillator also includes a plurality of interconnected inverters. The multiphase output oscillator structure can generate even-number multiphase signals.

U.S. Patent No. 6,870,431 discloses an oscillator with multiphase complementary outputs, which includes a first plurality of single-ended amplifiers connected in series to form an input and an output, a second plurality of single-ended amplifiers connected in series to An input terminal and an output terminal are formed. The first plurality of single-ended amplifiers and the second plurality of single-ended amplifiers are further interconnected through a feedback path and a locking circuit to generate multi-phase complementary signals.

Another common method is to use interpolation (also called phase-blending) to generate a multi-phase clock signal among multiple input signals. FIG. 1 illustrates a schematic diagram of a conventional single-stage phase hybrid circuit. Referring to FIG. 1, the four phase mixing circuits (a)-(d) have input signals ΦA, ΦB and output signals ΦA, ΦB, ΦAB, wherein signal ΦAB is generated by interpolation between signals ΦA, ΦB. For example, IEEE Journal of Solid-State Circuits, vol.34, No.5 (May 1999), discloses a portable digital delay locked loop (delay locked loop, DLL) of a high-speed CMOS interface circuit.

However, one problem with the interpolation approach is that it is usually impossible to interpolate an accurate signal on the phase interpolated signal, because the input signal is a full swing signal, and it needs to be obtained from two full swing signals. It is difficult to interpolate between adjacent input signals to find a signal that is precisely in the middle of two adjacent phase signals.

A commonly used method to solve the aforementioned phase inaccuracy problem is to add a load on the input signal, such as adding a capacitor. Adding the load makes the input signal a non-full swing signal, which improves the phase accuracy when the signal is interpolated. For example, IEEE Journal of Solid-State Circuits, vol.35, No.11 (November 2000), discloses a 1.3 cycle lock time, non-phase-locked loop/delay-locked loop clock pulse multiplier, which is generated by interpolating the clock pulse period That is to take the clock pulse (clock on demand), but this method will reduce the accuracy of the signal due to the instability and potential shift caused by the variation of the process parameters of the external capacitor.

To sum up, it is necessary to provide an accurate and stable phase interpolation to generate multi-phase signals for various data transmission applications, and a multi-phase oscillator that can be manufactured conveniently and simply.

Contents of the invention

The object of the present invention is to overcome the shortcomings of the aforementioned traditional multi-phase oscillator and provide a device and method for generating multi-phase clock signals (multi-phase clock signals) with a ring oscillator. The phase of the signal generated by it is accurate and easy to be detected. control.

The device and method for generating a multi-phase clock pulse signal by a ring oscillator of the present invention does not require an external capacitor as an external load to generate a non-full swing signal. Since no external capacitor is needed as a load, the present invention can avoid circuit instability caused by the process of the ring oscillator.

The device for generating multi-phase clock pulse signals with a ring oscillator of the present invention includes a first stage phase-blender module and a second stage phase-blender module. The first-stage phase mixing module also includes a plurality of differential OP phase-blender circuits, and each differential OP phase-blender circuit has two input signals and one output signal. The phase of the output signal is interpolated between the two input signals.

The second-stage phase-blending module includes a plurality of inverter phase-blender circuits. Each inverter phase mixing circuit receives two signals output by the first-stage phase mixing module as input signals, and outputs a clock pulse signal, and the phase of this clock pulse signal is interpolated between the two signals output by the first-stage phase mixing module between signals.

The present invention also provides a method for generating a multi-phase clock pulse signal with a ring oscillator, which includes the following steps: (1) using a ring oscillator to provide at least two non-full swing signals; (2) using a differential operational amplifier phase mixing a circuit to mix the phases of two partial swing signals generated by the ring oscillator; and (3) an inverter phase mixing circuit to generate a multiphase clock signal with interpolated phases.

Preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, so as to better understand the purpose, features and advantages of the present invention.

Description of drawings

FIG. 1 is a schematic diagram illustrating a conventional single-stage phase hybrid circuit.

FIG. 2 is a schematic diagram of an embodiment of the present invention in which the ring oscillator of the present invention is applied to generate three phase signals.

Fig. 3 shows another embodiment of the present invention, illustrating a 2-stage phase mixer which performs phase mixing for 2 input signals of different phases.

FIG. 4 is a schematic diagram illustrating a differential operational amplifier phase mixing circuit.

FIG. 5 is a flowchart of the operation of generating a multi-phase clock signal by a ring oscillator according to the present invention.

Detailed ways

FIG. 2 is a schematic diagram showing a first embodiment of the present invention, illustrating a ring oscillator generating three-phase clock pulse signals. Referring to FIG. 2, the ring oscillator that can generate 3 phase clock pulse signals includes 3 delay elements (delay element 1-delay element 3), which are connected in series with each other and generate signals Phi_1, Phi_1b, Phi_2, Phi_2b, Phi_3, and Phi_3b , wherein the signals Phi_1b, Phi_2b, and Phi_3b have opposite phases to the signals Phi_1, Phi_2, and Phi_3, respectively. The signals Phi_1, Phi_1b, Phi_2, Phi_2b, Phi_3, and Phi_3b are all non-full swing signals.

Fig. 3 shows another embodiment of the present invention, illustrating a 2-stage phase mixer which performs phase mixing for 2 input signals of different phases. The 2-stage phase mixer utilizes 2 pairs of non-full swing signals (Phi_1, Phi_2 and their complementary Phi_1b, Phi_2b signals) to generate 3 phase clock signals. The 2-stage phase mixer includes a first stage phase mixing module and a second stage phase mixing module. The first-stage phase mixing module also includes a plurality of differential operational amplifier phase mixing circuits, and each differential operational amplifier phase mixing circuit receives two input signals.

Referring to FIG. 3 , the differential operational amplifier phase mixing circuit 301A receives input signals Phi_1 and Phi_1b, and the differential operational amplifier phase mixing circuit 301B also receives input signals Phi_1 and Phi_1b. Similarly, the differential operational amplifier phase mixing circuit 301E receives signals Phi_2 and Phi_2b as input, and the differential operational amplifier phase mixing circuit 301F also receives signals Phi_2 and Phi_2b as input. However, the differential operational amplifier phase mixing circuit 301C receives the signals Phi_1 and Phi_2b as input, and the differential operational amplifier phase mixing circuit 301D receives the signals Phi_2 and Phi_1b as input. The differential operational amplifier phase mixing circuits 301A- 301F respectively output signals Phi_A, Phi_A, Phi_AB, Phi_BA, Phi_B, Phi_B.

It is further explained that the signal Phi_A is an amplified signal of the signal Phi_1, that is, the phase of the signal Phi_A is the same as that of the signal Phi_1, and the amplitude of the signal Phi_A is greater than the amplitude of the signal Phi_1; similarly, the signal Phi_B is the amplified signal of signal Phi_2. The main purpose of the differential operational amplifier phase mixing circuits 301A, 301B, 301E and 301F is to generate delays to compensate for the delays caused by the differential operational amplifier phase mixing circuits 301C and 301D.

The phase of the output signal Phi_AB of the differential operational amplifier phase mixing circuit 301C is obtained by interpolating the signals Phi_1 and Phi_2b; the phase of the output signal Phi_BA of the differential operational amplifier phase mixing circuit 301D is obtained by interpolating the signals Phi_2 and Phi_1b. Get it by plugging in.

The second-stage phase mixing module in FIG. 3 includes a plurality of inverter phase mixing circuits, and in this embodiment, each inverter phase mixing circuit further includes 3 inverters. For example, the inverters 302A, 302B, and 303A form an inverter phase mixing circuit to mix the signals Phi_A and Phi_A to generate a clock signal Phi_1'. It is worth mentioning that the phase of the signal Phi_1' is the same as that of the signal Phi_A , Phi_1 phase is the same. Similarly, the phase of the clock signal Phi_2' is the same as that of the signals Phi_B and Phi_2.

On the other hand, the inverters 302C, 302D, and 303C form an inverter phase mixing circuit to mix the signals Phi_AB and Phi_BA to generate a clock signal Phi_12. The phase of the signal Phi_12 is interpolated from the signals Phi_1 and Phi_2. Come. Therefore, the 2-stage phase mixer mixes the input signals Phi_1 and Phi_2 and generates 3-phase clock signals Phi_1', Phi_12, and Phi_2'.

Similarly, this 2-stage phase mixer can also be used to mix two input signals Phi_2 and Phi_3 and generate 3-phase clock pulse signals Phi_2', Phi_23, and Phi_3'; and mix two input signals Phi_3 and Phi_1 and generate Three phase clock signals Phi_3 ′, Phi_31 , and Phi_1 ′ are generated.

FIG. 4 is a schematic diagram of a detailed circuit of a differential operational amplifier phase mixing circuit. Referring to FIG. 4, the differential operation circuit has input signals V+ and V-, and outputs a Vout signal. Taking the differential operational amplifier phase mixing circuit 301C of FIG. 3 as an example, since the signal Phi_2b(V−) has a phase delay to compensate the signal Phi_1(V+), the transistor MN2 delays its current reduction. Therefore, the output signal Phi_AB(Vout) has a phase delay relative to the signal Phi_A, wherein the signal Phi_A is the signal output by the differential operational amplifier phase mixing circuits 301A and 301B.

Similarly, as shown in the differential operational amplifier phase mixing circuit 301D of FIG. 3 , because the signal Phi_2 (V+) has a phase delay relative to the signal Phi_1b (V−), the transistor MN2 pulls the current low before the transistor MN1 . Therefore, the output signal Phi_AB(Vout) has a phase delay relative to the signal Phi_B, wherein the signal Phi_B is the signal output by the differential operational amplifier phase mixing circuits 301E and 301F.

The signal Phi_AB and the signal Phi_BA are mixed again by the inverters 302C, 302D, 303C to generate the clock signal Phi_12. It is worth mentioning that the inverter phase hybrid circuit composed of inverters 302A, 302B, 303A and the inverter phase hybrid circuit composed of inverters 302E, 302F, 303E are used to compensate the delay.

FIG. 5 is a flowchart illustrating the use of a ring oscillator to generate a multi-phase clock signal. Referring to FIG. 5 , a ring oscillator is used to provide at least two partial swing signals, as shown in step 501 . Multiple differential operational amplifier phase mixing circuits are used to mix the phases of the two partial swing signals generated by the ring oscillator to produce different combinations, as shown in step 502 . Finally, a plurality of inverter phase mixing circuits are used to mix the output signals of step 502 to generate multi-phase clock pulse signals with interpolated phases, as shown in step 503 .

However, what is described above is only the best embodiment of the invention, and should not limit the implementation scope of the present invention accordingly. All equivalent changes and modifications made according to the claims of the present application shall still fall within the scope covered by the patent of the present invention.

Claims (5)

1. A device for generating a multi-phase clock pulse signal with a ring oscillator, the device comprising: a first-stage phase mixing module, which receives at least two signals of different phases output from the ring oscillator as input, and outputs a plurality of signals of different phases; and A second-stage phase mixing module is connected with the first-stage phase mixing module, which receives the signal output by the first-stage phase mixing module and generates the multi-phase clock pulse signal. 2. The device for generating a multi-phase clock pulse signal with a ring oscillator according to claim 1, wherein the first stage phase mixing module further comprises a plurality of differential operational amplifier phase mixing circuits. 3. The device for generating a multi-phase clock pulse signal with a ring oscillator according to claim 1, wherein the second-stage phase mixing module further comprises a plurality of inverter phase mixing circuits. 4. The device for generating a multi-phase clock pulse signal with a ring oscillator according to claim 3, wherein the inverter phase mixing circuit comprises a first inverter for receiving a first signal and generating a a first inverted signal; a second inverter for receiving a second signal and generating a second inverted signal; and a third inverter for receiving the first inverted signal and the second inverted signal phase signals, and generate the multi-phase clock signal with interpolated phases of the first signal and the second signal. 5. A method for generating a multiphase clock pulse signal with a ring oscillator, the method comprises the following steps: a. Use a ring oscillator to provide at least two partial swing signals; b. using a plurality of differential operational amplifier phase mixing circuits to mix the phases of the two partial swing signals generated by the ring oscillator; and c. Mixing the signals output by the step b. using a plurality of inverter phase mixing circuits and generating the multi-phase clock signal with interpolated phases.

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