CN101236927A - Self-aligned contact and method for fabricating the same - Google Patents

Abstract

A method for fabricating a self-aligned contact. The method includes providing a substrate having formed thereon a plurality of NAND-type memory cell rows including drain regions. Then, an interlayer dielectric layer is formed on the substrate to cover the NAND type memory cell rows. Then, the interlayer dielectric layer is patterned to form a plurality of openings, and the drain regions are exposed by the openings. Then, a selective silicon growth process is performed to form a material layer on the drain region exposed by the opening. And finally, forming a metal layer on the material layer to fill the opening.

Description

Self-aligning contact window and manufacturing method thereof

technical field

The invention relates to a semiconductor process, and in particular to a self-aligned contact window and a manufacturing method thereof.

Background technique

Flash storage devices have been widely used in personal computers and electronic devices because they can store, read, and erase data multiple times, and the stored data will not disappear after power failure. A non-volatile memory element.

A typical flash memory device uses doped polysilicon to make a floating gate (Floating Gate) and a control gate (Control Gate). Moreover, the control gate is directly disposed on the floating gate, the floating gate and the control gate are separated by an inter-gate dielectric layer, and the floating gate and the substrate are separated by a tunnel dielectric layer (that is, so-called stacked gate flash memory).

On the other hand, flash memory arrays commonly used in the industry include NOR array structures and NAND array structures. Since the non-volatile memory structure of the NAND array is to connect the memory cells in series, its integration and area utilization are better than the non-volatile memory of the NOR array, so it has been widely used in various electronic products.

Please refer to FIG. 1 , which is a cross-sectional view of a bit line contact window structure of a NAND storage device. The existing method for forming the bit line contact window is, for example, to form the bit line contact window 106 by self-aligned contact process (Self-aligned Contact Process) after the isolation structure 102 and the interlayer dielectric layer 104 are formed, and to fill the bit line The material of the opening of the contact window is polysilicon. However, when the device size is reduced, the bit line contact window 106 may be shifted due to process variation, and the bit line contact window 106 will be in contact with the substrate 100, such as the circled portion 108, causing junction leakage current (Junction Leakage) )The phenomenon. In addition, using polysilicon as the material for filling the opening of the bit line contact window will increase the resistance value of the bit line contact window and affect the operating performance of the device.

Contents of the invention

In view of this, the object of the present invention is to provide a method for fabricating self-aligned contacts, which can prevent the problem of junction leakage and reduce the resistance of the contacts.

Yet another object of the present invention is to provide a self-aligned contact whose structure can prevent junction leakage and has a lower contact resistance.

The invention provides a method for manufacturing a self-aligned contact window. This method includes the following steps. First, a substrate is provided, on which a plurality of rows of NAND memory cells have been formed, and the rows of NAND memory cells include drain regions. Then, an interlayer dielectric layer is formed on the substrate to cover the row of NAND memory cells. Then, the interlayer dielectric layer is patterned to form a plurality of openings, which respectively expose the drain region. Then, a selective silicon growth process is performed to form a material layer on the drain region exposed by the opening. Furthermore, a metal layer is formed on the material layer to fill the opening.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the aforementioned selective silicon growth process uses, for example, silane gas as the reaction gas.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned silane gas includes silane, silane or silane.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned selective silicon growth process includes an epitaxial process.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned selective silicon growth process includes a selective silicon deposition process.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned selective silicon deposition process includes chemical vapor deposition.

According to the method for manufacturing the self-aligned contact window in the preferred embodiment of the present invention, the material of the above material layer is, for example, doped or undoped single crystal silicon, or doped or undoped polycrystalline silicon.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the material of the above-mentioned interlayer dielectric layer is, for example, phosphosilicate glass or borophosphosilicate glass.

According to the method for manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the method for forming the above-mentioned interlayer dielectric layer is, for example, chemical vapor deposition.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the material of the metal layer is, for example, tungsten.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the above metal layer is formed by chemical vapor deposition, for example.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, after the above metal layer is formed, it further includes removing the metal layer outside the opening.

The invention provides a method for manufacturing a self-aligned contact window. This method includes the following steps. Firstly, a substrate is provided, in which a plurality of element isolation structures arranged in parallel have been formed. Next, a doped region is formed in the substrate between the device isolation structures, and an interlayer dielectric layer is formed on the substrate. There are a plurality of openings in the interlayer dielectric layer, and these openings respectively expose the doped regions. Then, a selective silicon growth process is performed to form a material layer on the doped region exposed by the opening. Afterwards, a metal layer is formed on the material layer to fill the opening.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the aforementioned selective silicon growth process uses, for example, silane gas as the reaction gas.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned silane gas includes silane, silane or silane.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned selective silicon growth process includes an epitaxial process.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned selective silicon growth process includes a selective silicon deposition process.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned selective silicon deposition process includes chemical vapor deposition.

According to the method for manufacturing the self-aligned contact window in the preferred embodiment of the present invention, the material of the above material layer is, for example, doped or undoped single crystal silicon, or doped or undoped polycrystalline silicon.

According to the method of manufacturing the self-aligned contact window described in the preferred embodiment of the present invention, the material of the above-mentioned interlayer dielectric layer is, for example, phosphosilicate glass or borophosphosilicate glass.

The method for manufacturing the self-aligned contact window of the present invention adopts a selective silicon growth process, first forming a material layer at the bottom of the opening of the self-aligned contact window, and then forming a metal layer to fill the opening. In this way, even if the misalignment of the self-aligned contact window occurs, the metal layer will not be in direct contact with the substrate, thereby avoiding the occurrence of junction leakage current. Furthermore, replacing the existing polysilicon with tungsten as the main material of the contact window can reduce the resistance of the contact window and improve the performance of the device.

The invention provides a self-aligned contact window. The self-aligned contact window includes a substrate, an interlayer dielectric layer, a selective silicon growth material layer and a metal layer. A plurality of rows of NAND memory cells are arranged on the substrate, and the rows of NAND memory cells include source regions and drain regions. The interlayer dielectric layer is disposed on the base and has a plurality of openings, and the openings expose part of the drain region. The selective silicon growth material layer is disposed in the opening and located on the drain region. The metal layer is disposed on the selective silicon growth material layer and fills the opening.

According to the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned row of NAND memory cells further includes a plurality of memory cells, two selection cells and a plurality of doped regions. The memory cells are disposed on the substrate between the source region and the drain region, and each memory cell has a charge storage layer. The doped regions are disposed in the substrate between the memory cells, so that the memory cells are connected in series. The two selection units are respectively arranged between the memory cells connected in series and the source region and the drain region.

According to the self-aligned contact window described in the preferred embodiment of the present invention, the above-mentioned memory cell includes, for example, a tunnel dielectric layer, a charge storage layer, an inter-gate dielectric layer, and a control gate from the base.

According to the self-aligned contact window described in the preferred embodiment of the present invention, the material of the inter-gate dielectric layer is, for example, silicon oxide/silicon nitride/silicon oxide.

According to the self-aligned contact window described in the preferred embodiment of the present invention, the material of the above-mentioned charge storage layer is, for example, doped polysilicon.

According to the self-aligned contact window described in the preferred embodiment of the present invention, the material of the tunneling dielectric layer is, for example, silicon oxide.

According to the self-aligned contact window described in the preferred embodiment of the present invention, the material of the interlayer dielectric layer is, for example, phosphosilicate glass or borophosphosilicate glass.

According to the self-aligned contact window described in the preferred embodiment of the present invention, the material of the metal layer is, for example, tungsten.

The self-aligned contact window of the present invention has a layer of silicon material at the bottom of the opening of the self-aligned contact window. In this way, even if the misalignment of the self-aligned contact window occurs, the metal layer will not be in direct contact with the silicon substrate, thereby avoiding the occurrence of junction leakage current. Furthermore, using tungsten as the main material of the contact window can reduce the resistance of the contact window and improve the performance of the device.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below in conjunction with the accompanying drawings.

Description of drawings

Figure 1 is a cross-sectional view of the junction leakage current phenomenon caused by the process variation of the self-aligned contact window.

2A to 2C are top views of the manufacturing process of the self-aligned contact window of the NAND memory according to the preferred embodiment of the present invention.

FIGS. 3A to 3C are cross-sectional views of the manufacturing process along the line A-A' in FIGS. 2A to 2C respectively.

FIGS. 4A to 4C are cross-sectional views of the manufacturing process along the tangent line B-B' in FIGS. 2A to 2C respectively.

simple notation

200: base

202: Isolation structure

204: active area

206: Memory cell row

208: storage unit

210: drain region

212: source region

214a, 214b: selection unit

216: doped area

218: Tunneling dielectric layer

220: charge storage layer

222: inter-gate dielectric layer

224: Control grid

226, 232: interlayer dielectric layer

228: channel

230: source line

234: opening

236: material layer

238: metal layer

Detailed ways

2A to 2C are top views of the manufacturing process of the self-aligned contact window of the NAND memory according to the preferred embodiment of the present invention. FIGS. 3A to 3C are cross-sectional views of the manufacturing process along the line A-A' in FIGS. 2A to 2C respectively. FIGS. 4A to 4C are cross-sectional views of the manufacturing process along the tangent line B-B' in FIGS. 2A to 2C respectively.

Please refer to FIG. 2A , FIG. 3A and FIG. 4A at the same time. First, a substrate 200 is provided, such as a silicon substrate. Then, a plurality of isolation structures 202 are formed in the substrate 200 to define active regions 204 between adjacent isolation structures 202 . The isolation structure 202 is, for example, a trench isolation structure. The method for forming the trench isolation structure is, for example, prior to forming a patterned mask layer on the substrate 200 . Next, using the patterned mask layer as a mask, part of the substrate is removed to form a plurality of channels. Next, an insulating material layer is formed on the substrate 200, and the insulating material layer fills up the trench. Afterwards, part of the insulating material layer outside the trench is removed to form the isolation structure 202 . The isolation structures 202 are arranged in parallel in the X direction (row direction).

Then, a plurality of memory cell rows 206 are formed on the substrate 200 . Each memory cell row 206 is composed of, for example, a plurality of memory cells 208 , a drain region 210 and a source region 212 , and two selection units 214 a and 214 b. Wherein, the memory cell 208 is connected in series between the drain region 210 and the source region 212 . The two selection units 214 a and 214 b are respectively formed between the two outermost memory cells in the memory cell row 206 and the drain region 210 and the source region 212 . In addition, the storage units 208 and the storage unit 208 and the two selection units 214a, 214b are connected together by the doped region 216, for example. The memory cell 208 at least includes a tunneling dielectric layer 218 , a charge storage layer 220 , an inter-gate dielectric layer 222 and a control gate 224 starting from the substrate 200 .

Referring to FIGS. 2B , 3B and 4B at the same time, an interlayer dielectric layer 226 is formed on the substrate 200 . The material of the interlayer dielectric layer 226 is, for example, phosphosilicate glass or borophosphosilicate glass or other suitable dielectric materials, and its formation method is, for example, chemical vapor deposition. Then, the interlayer dielectric layer 226 is patterned to form the trench 228 . A method for patterning the ILD layer 226 is, for example, a photolithographic etching process. Wherein, the channel 228 exposes part of the source region 212 . A metal layer is then formed in trench 228 as source line 230 .

Next, please refer to FIG. 2C , FIG. 3C and FIG. 4C at the same time. An interlayer dielectric layer 232 is formed on the substrate 200 . The material of the interlayer dielectric layer 232 is, for example, phosphosilicate glass or borophosphosilicate glass or other suitable dielectric materials, and its formation method is, for example, chemical vapor deposition. Then, the interlayer dielectric layer 232 and the interlayer dielectric layer 226 are patterned to form a plurality of openings 234 . The openings 234 respectively expose the drain regions 210 . A layer of material 236 is formed in opening 234 . The material of the material layer 236 is, for example, doped or undoped single crystal silicon, or doped or undoped polycrystalline silicon. The method of forming the material layer 236 includes a selective silicon growth process. The method for forming the material layer 236 is, for example, a selective epitaxy method. The selective silicon growth process involves using silane gas, such as silane, silethane, or silane, as a reactive gas. In another embodiment, the material layer 236 may also be formed by a selective silicon deposition process. A selective silicon deposition process is, for example, chemical vapor deposition. Before forming the contact window, a layer of silicon material is formed at the bottom of the opening. This design can avoid the junction leakage current caused by the direct contact between the metal layer of the contact window and the substrate in case of misalignment of the self-aligned contact window. Phenomenon.

Then, referring to FIG. 2C , FIG. 3C and FIG. 4C , metal layers 238 are respectively formed in the openings 234 . The metal layer 238 is formed by, for example, firstly forming a metal material layer on the substrate 200 , and the metal material layer fills the opening 234 . Afterwards, a chemical mechanical polishing process is performed, using the interlayer dielectric layer 232 as a polishing stop layer, and removing the metal material layer outside the opening 234 . The material of the metal layer 238 is, for example, tungsten. Using tungsten instead of the commonly used polysilicon as the metal layer filling the opening of the contact window can reduce the resistance of the contact window and improve the performance of the device. The subsequent process for completing the semiconductor element is well known to those skilled in the art, and will not be repeated here.

Next, the self-aligned contact window structure of the NAND memory of the present invention will be described.

Referring to FIG. 2C , FIG. 3C and FIG. 4C again, the self-aligned contact window of the NAND memory of the present invention is mainly composed of a substrate 200 , interlayer dielectric layers 226 and 232 , a material layer 236 and a metal layer 238 . Wherein, a plurality of NAND memory cell rows 206 are disposed on the substrate 200 , and the NAND memory cell row 206 includes a drain region 210 , a source region 212 , a memory cell 208 , selection units 214 a and 214 b and a doping region 216 . The storage unit 208 is disposed on the substrate 200 between the source region 212 and the drain region 210. The composition of the storage unit 208 from the substrate 200 is a tunneling dielectric layer 218, a charge storage layer 220, and an inter-gate dielectric layer 222. with control gate 224. The material of the inter-gate dielectric layer 222 is, for example, silicon oxide/silicon nitride/silicon oxide. The material of the charge storage layer 220 is, for example, doped polysilicon. The material of the tunneling dielectric layer 218 is, for example, silicon oxide. A plurality of doped regions 216 are disposed in the substrate 200 between the memory cells 208 such that the memory cells 208 are connected in series. The selection units 214 a and 214 b are respectively disposed between the memory unit 208 connected in series and the source region 212 and the drain region 210 .

Please continue to refer to FIG. 2C , FIG. 3C and FIG. 4C , the interlayer dielectric layers 226 and 232 are disposed on the substrate 200 and have a plurality of openings 234 , and the openings 234 expose part of the drain region 210 . The material of the interlayer dielectric layers 226 and 232 can be phosphosilicate glass or borophosphosilicate glass or other suitable dielectric materials. The material layer 236 is disposed in the opening 234 and located on the drain region 210 . The material of the material layer 236 is, for example, doped polysilicon. The metal layer 238 is disposed on the material layer 236 and fills the opening 234 . The material of the metal layer 234 is, for example, tungsten.

The purpose of forming a layer of material layer 236 at the bottom of the opening 234 is that if the misalignment of the self-aligned contact window occurs during the manufacturing process and the contact window is shifted, the metal layer 234 can avoid contact with the substrate 200 due to the shielding of the material layer 236. direct contact, thereby preventing the occurrence of junction leakage current phenomenon. On the other hand, using tungsten as the material of the metal layer 238 can improve the existing problem of high contact window resistance caused by using polysilicon.

To sum up, the method for manufacturing the self-aligned contact window of the present invention is to perform a selective silicon growth process to form a material layer at the bottom of the self-aligned contact window opening. In this way, even if the misalignment of the self-aligned contact window occurs, the metal layer will not be in direct contact with the silicon substrate, thereby avoiding the occurrence of junction leakage current. Furthermore, using tungsten as the main material of the contact window can reduce the resistance of the contact window to improve the performance of the device.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any skilled person in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention is defined by the appended claims.

Claims (28)

1. manufacture method of aiming at contact hole voluntarily comprises:

Substrate is provided;

Form a plurality of NAND type memory cell rows in this substrate, those NAND type memory cell rows respectively comprise the drain region;

In this substrate, form interlayer dielectric layer, to cover those NAND type memory cell rows;

This interlayer dielectric layer of pattern, to form a plurality of openings, those openings expose those drain regions respectively;

Carry out selective silicon growth technology, on those drain regions that those openings were exposed, to form material layer; And

On this material layer, form metal level to fill up those openings.

2. manufacture method of aiming at contact hole voluntarily as claimed in claim 1, wherein this selective silicon growth technology comprises that the use silane gas is as reacting gas.

3. manufacture method of aiming at contact hole voluntarily as claimed in claim 2, wherein silane gas comprises silicomethane, silicon ethane or silicon propane.

4. manufacture method of aiming at contact hole voluntarily as claimed in claim 1, wherein this selective silicon growth technology comprises epitaxy technique.

5. manufacture method of aiming at contact hole voluntarily as claimed in claim 1, wherein this selective silicon growth technology comprises the selective silicon depositing operation.

6. manufacture method of aiming at contact hole voluntarily as claimed in claim 5, wherein this selective silicon depositing operation comprises chemical vapour deposition technique.

7. manufacture method of aiming at contact hole voluntarily as claimed in claim 1, wherein the material of this material layer comprises doping or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.

8. manufacture method of aiming at contact hole voluntarily as claimed in claim 1, wherein the material of this interlayer dielectric layer comprises phosphorosilicate glass or boron-phosphorosilicate glass.

9. manufacture method of aiming at contact hole voluntarily as claimed in claim 1, wherein the formation method of this interlayer dielectric layer comprises chemical vapour deposition technique.

10. manufacture method of aiming at contact hole voluntarily as claimed in claim 1, wherein the material of this metal level comprises tungsten.

11. manufacture method of aiming at contact hole voluntarily as claimed in claim 1, wherein the formation method of this metal level comprises chemical vapour deposition technique.

12. manufacture method of aiming at contact hole voluntarily as claimed in claim 1 after wherein this metal level forms, also comprises this metal level that removes outside those openings.

13. a manufacture method of aiming at contact hole voluntarily comprises:

Substrate is provided, has been formed with a plurality of component isolation structures in this substrate, those component isolation structures are arranged in parallel;

Form doped region in the substrate between those component isolation structures;

Form interlayer dielectric layer in this substrate, have a plurality of openings in this interlayer dielectric layer, those openings expose those doped regions respectively;

Carry out selective silicon growth technology, on those doped regions that those openings were exposed, to form material layer; And

On this material layer, form metal level to fill up those openings.

14. manufacture method of aiming at contact hole voluntarily as claimed in claim 13, wherein this selective silicon growth technology comprises that the use silane gas is as reacting gas.

15. manufacture method of aiming at contact hole voluntarily as claimed in claim 14, wherein silane gas comprises silicomethane, silicon ethane or silicon propane.

16. manufacture method of aiming at contact hole voluntarily as claimed in claim 13, wherein this selective silicon growth technology comprises epitaxy technique.

17. manufacture method of aiming at contact hole voluntarily as claimed in claim 13, wherein this selective silicon growth technology comprises the selective silicon depositing operation.

18. manufacture method of aiming at contact hole voluntarily as claimed in claim 17, wherein this selective silicon depositing operation comprises chemical vapour deposition technique.

19. manufacture method of aiming at contact hole voluntarily as claimed in claim 13, wherein the material of this material layer comprises doping or unadulterated monocrystalline silicon, doping or unadulterated polysilicon.

20. manufacture method of aiming at contact hole voluntarily as claimed in claim 13, wherein the material of this interlayer dielectric layer comprises phosphorosilicate glass or boron-phosphorosilicate glass.

21. aim at contact hole voluntarily, comprising for one kind:

Substrate, this substrate are provided with a plurality of NAND type memory cell rows, and those NAND type memory cell rows respectively comprise source area and drain region;

Interlayer dielectric layer is disposed in this substrate and has a plurality of openings, and those openings expose those drain regions of part;

Selective silicon growth material layer is disposed in those openings, and is positioned on those drain regions; And

Metal level is disposed on this selective silicon growth material layer and fills up those openings.

22. the contact hole of aiming at voluntarily as claimed in claim 21, wherein respectively this NAND type memory cell rows also comprises:

A plurality of memory cell are arranged in this substrate between this source area and this drain region, and each those memory cell has electric charge storage layer;

A plurality of doped regions are arranged in this substrate between those memory cell, and those memory cell series connection are linked together; And

Two selected cells are arranged at respectively between those memory cell of being connected in series and this source area, this drain region.

23. the contact hole of aiming at voluntarily as claimed in claim 22, wherein each those memory cell is risen by this substrate and comprises dielectric layer and control grid between tunneling dielectric layer, electric charge storage layer, grid at least.

24. the contact hole of aiming at voluntarily as claimed in claim 23, wherein the material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between these grid.

25. the contact hole of aiming at voluntarily as claimed in claim 23, wherein the material of this electric charge storage layer is a doped polycrystalline silicon.

26. the contact hole of aiming at voluntarily as claimed in claim 23, wherein the material of this tunneling dielectric layer comprises silica.

27. the contact hole of aiming at voluntarily as claimed in claim 21, wherein the material of this interlayer dielectric layer comprises phosphorosilicate glass or boron-phosphorosilicate glass.

28. the contact hole of aiming at voluntarily as claimed in claim 21, wherein the material of this metal level comprises tungsten.

Images