CN101232362B - Method for anti-false locking frequency synthesizer - Google Patents
Method for anti-false locking frequency synthesizer Download PDFInfo
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- CN101232362B CN101232362B CN200810065634XA CN200810065634A CN101232362B CN 101232362 B CN101232362 B CN 101232362B CN 200810065634X A CN200810065634X A CN 200810065634XA CN 200810065634 A CN200810065634 A CN 200810065634A CN 101232362 B CN101232362 B CN 101232362B
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000001514 detection method Methods 0.000 claims description 6
- 230000007257 malfunction Effects 0.000 claims description 4
- 238000009826 distribution Methods 0.000 claims description 3
- 238000004891 communication Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000005304 joining Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
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Abstract
The invention discloses an anti-false locking method of a frequency synthesizer, which comprises the following steps that: the power supply is carried out to a chip of the frequency synthesizer, the data outside the locking scope is configured; whether the locking indicating level of the chip of the frequency synthesizer is failure in locking or not is detected, if in locking, the chip of the frequency synthesizer is in the fault state of failure in locking; otherwise, the frequency data of the locking scope is configured to carry out the judgment. As the anti-false locking method of the frequency synthesizer adopts the number matching mode, the invention effectively can avoid the system misjudgment problem of the false locking which is randomly caused by locking the initial power supply state of a locking indicating pin and facilitate the fault positioning of the system at the same time.
Description
Technical field
The present invention relates to a kind of communication field clock anti-false locking fixed join counting method, the detection method during in particular a kind of frequency synthesizer chip lockout failure.
Background technology
In the prior art, phase-locked loop (PLL, Phase Lock Loop) being can be effectively with a kind of circuit of input signal with the phase locking of reference signal, usually in communication system, be extensive use of the data transmit-receive clock synchronization that PHASE-LOCKED LOOP PLL TECHNIQUE guarantees each communication node, and the local oscillation signal that radio-frequency (RF) transceiver is provided.
Along with the continuous progress of electronics manufacturing processing technic, the improving constantly of design level, the phase-locked loop circuit of being built by discrete component in the design in the past partly or entirely integratedly advances the frequency synthesizer integrated chip.The frequency synthesizer integrated chip has become the industry main flow gradually, its typical structure as shown in Figure 1, chip internal multi-point signal (comprising lock indication signal) is for the convenience of the users monitored, chip is connected to MUX (MUX) output with a plurality of signals in inside, by configuration to inner control register, one of them signal output of gating.
When device just powered on, the initial value of control register was a random value, so the output level of MUX also is a stochastic regime.When it detects as the locking indication, will the frequency of occurrences not lock but " spurious lock " situation of locking indicated number locking.
If in communication system, use, the system failure is complained to the backstage by the form of information, when the frequency synthesizer chip is in above-mentioned " spurious lock " state, and failure of chip occurs or join situations such as logarithmic data link problem, can't find that from the system backstage frequency synthesizer goes wrong, this moment need expend the plenty of time and manpower is investigated fault.
At present existing patent at phase-locked loop lost efficacy and spurious lock is all the design and the decision method of pll lock testing circuit, but also do not have the correlation technique settling mode at the problem of top chip " spurious lock ".
Summary of the invention
Technical problem to be solved by this invention is: state causes system's erroneous judgement problem of " spurious lock " at random when overcoming initially powering on owing to locking indication pin of existing in the existing frequency synthesizer phase-locked loop chip technology, provide a kind of and avoid the frequency synthesizer of " spurious lock " phenomenon to join counting method, and can be according to locking result judgement that whether the frequency synthesizer chip was lost efficacy, to assist to shorten to the location of the system failure and to solve the required time.
Technical scheme of the present invention comprises:
A kind of method of anti-false locking frequency synthesizer, it may further comprise the steps:
A, the frequency synthesizer chip is powered on, and to the extraneous data of its configuration locking;
Whether the locking indication level of B, the described frequency synthesizer chip of detection is losing lock, if for locking, then report described frequency synthesizer chip to be in the losing lock malfunction; Otherwise the frequency data of configuration locking scope are judged.
Described method wherein, when the indication of locking described in described step B level is out-of-lock condition, also comprises step:
B1, to the frequency data in described its lock-in range of frequency synthesizer chip configuration, whether the locking indication level that detects described frequency synthesizer chip is locking;
If the described locking indication of B2 level is a lock-out state, then described frequency synthesizer locking is normal; Otherwise, report described frequency synthesizer chip to be in the losing lock malfunction.
Described method, wherein, repeating said steps A and described step B detect judgement, if each extraneous data of configuration locking, detecting the locking indication all is locking, then orientates data distribution link problem or described frequency synthesizer failure of chip as.
Described method, wherein, described number of repetition is above 3 times.
The method of a kind of anti-false locking frequency synthesizer provided by the present invention, owing to adopt several mode of joining, effectively avoided having made things convenient for the fault location of system simultaneously owing to lock system's erroneous judgement problem of state causes at random when indicating pin initially to power on " spurious lock ".
Description of drawings
Fig. 1 is the frequency synthesizer chip typical structure block diagram of prior art;
Fig. 2 is the process chart of the inventive method.
Embodiment
Below in conjunction with accompanying drawing, will be described in further detail technical scheme of the present invention:
The core idea of the method for anti-false locking frequency synthesizer of the present invention is, the specific lock-in range of utilizing each frequency synthesizer chip all to have, join number locking test according to adopting frequency and extraneous frequency in the described lock-in range in this correspondence lock-in range respectively, because in this corresponding lock-in range, just might lock, the frequency that surpasses lock-in range can't lock, and respectively by adopting outer frequency of lock-in range and the frequency in the lock-in range, the locking indication level that detects described frequency synthesizer respectively is in locking or out-of-lock condition, whether is in pseudo-locked state to judge it.
The anti-false locking of the inventive method is joined several processes as shown in Figure 2, may further comprise the steps substantially:
Steps A, described frequency synthesizer chip power are to frequency synthesizer chip configuration chip losing lock data;
Whether the locking indication level of step B, the described frequency synthesizer chip of detection is losing lock;
If the described locking indication of step C level is locking, because be losing lock data to described frequency synthesizer chip configuration this moment, it is the outer frequency of described lock-in range, described frequency synthesizer should be in out-of-lock condition, if and described locking indication level is that the described frequency synthesizer chip of decidable is spurious lock for locking, be the losing lock fault; Otherwise, but execution in step D;
Step D, to described frequency synthesizer chip configuration system requirements frequency data, promptly the frequency in its lock-in range detects described frequency synthesizer chip lock definiteness then and shows whether be locking;
If the locking indication level of step e described frequency synthesizer chip this moment represents then that for locking the locking of this frequency synthesizer is normal; Be in out-of-lock condition else if, then should report described frequency synthesizer is the losing lock fault.The situation of step e is the existing detected state of prior art, so its implementation procedure is that prior art is known, does not repeat them here.
The method of anti-false locking frequency synthesizer of the present invention, its specific embodiment to join several process descriptions as follows, please refer to shown in Figure 2:
Step 1: at first give described frequency synthesizer chip power work;
Step 2: with software in the normal order when each register is configured in the described frequency synthesizer chip, a frequency values that surpasses chip locking frequency range is set, for example when the lock-in range of frequency synthesizer is 2500MHz～2600MHz, can first configuration locking frequency be 100MHz then, so just make described frequency synthesizer chip just often should be in out-of-lock condition.
Step 3: detecting the output level of the locking indication pin of described frequency synthesizer chip, if output level is designated as locking, then is false lock fault; In order to improve accuracy, general step 2, step 3 will repeat repeatedly to carry out, can determine to repeat to join number for several times according to concrete applied environment, general above 3 times, if each extraneous data of configuration locking such as configuration locking frequency are 100MHz, detecting the locking indication all is locking, then orientates data distribution link problem or described frequency synthesizer failure of chip as, report frequency synthesizer losing lock fault, flow process finishes.If output level is designated as losing lock, then execution in step 4 is carried out the detection of frequency in the normal lock-in range.
Step 4: in the normal order the frequency that described frequency synthesizer chip carries out in its lock-in range is joined number with software, and the state of detection locking indication level, if detecting its locking indication level is lock-out state, show that then this frequency synthesizer lock-in circuit is normal, flow process finishes; Otherwise, must report frequency synthesizer losing lock fault, flow process finishes.
The method of anti-false locking frequency synthesizer of the present invention detects by the above-mentioned number of joining to described frequency synthesizer chip, need not hardware is changed, just can detect the present pseudo-locked state of described frequency synthesizer, effectively avoided owing to lock " spurious lock " problem that state is caused at random when indicating pin initially to power on, the judgement that can whether lose efficacy to the frequency synthesizer chip according to the locking result simultaneously, assist to shorten the location of the system failure and to solve the required time, made things convenient for the fault location of system.
Should be understood that above-mentioned description at preferred embodiment of the present invention is comparatively detailed, can not therefore think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (4)
1. the method for an anti-false locking frequency synthesizer, it may further comprise the steps:
A, the frequency synthesizer chip is powered on, and to the extraneous data of its configuration locking;
Whether the locking indication level of B, the described frequency synthesizer chip of detection is losing lock, if for locking, then report described frequency synthesizer chip to be in the losing lock malfunction; Otherwise the frequency data of configuration locking scope are judged.
2. method according to claim 1 is characterized in that, when the indication of locking described in described step B level is out-of-lock condition, also comprises step:
B1, to the frequency data in described its lock-in range of frequency synthesizer chip configuration, whether the locking indication level that detects described frequency synthesizer chip is locking;
If the described locking indication of B2 level is a lock-out state, then described frequency synthesizer locking is normal; Otherwise, report described frequency synthesizer chip to be in the losing lock malfunction.
3. method according to claim 2, it is characterized in that repeating said steps A and described step B detect judgement, if each extraneous data of configuration locking, detecting the locking indication all is locking, then orientates data distribution link problem or described frequency synthesizer failure of chip as.
4. method according to claim 3 is characterized in that, described number of repetition is above 3 times.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200810065634XA CN101232362B (en) | 2008-01-21 | 2008-01-21 | Method for anti-false locking frequency synthesizer |
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| CN200810065634XA CN101232362B (en) | 2008-01-21 | 2008-01-21 | Method for anti-false locking frequency synthesizer |
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| CN101232362A CN101232362A (en) | 2008-07-30 |
| CN101232362B true CN101232362B (en) | 2010-12-08 |
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| CN200810065634XA Expired - Fee Related CN101232362B (en) | 2008-01-21 | 2008-01-21 | Method for anti-false locking frequency synthesizer |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473639A (en) * | 1993-07-26 | 1995-12-05 | Hewlett-Packard Company | Clock recovery apparatus with means for sensing an out of lock condition |
| CN1358351A (en) * | 2000-01-10 | 2002-07-10 | 通用电气公司 | Method and apparatus for improving capture and lock characteristics of phase lock loops |
| US6895525B1 (en) * | 1999-08-20 | 2005-05-17 | International Business Machines Corporation | Method and system for detecting phase-locked loop (PLL) clock synthesis faults |
| CN1801622A (en) * | 2004-12-31 | 2006-07-12 | 华为技术有限公司 | Phase-locked loop frequency locking judging method and circuit |
-
2008
- 2008-01-21 CN CN200810065634XA patent/CN101232362B/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5473639A (en) * | 1993-07-26 | 1995-12-05 | Hewlett-Packard Company | Clock recovery apparatus with means for sensing an out of lock condition |
| US6895525B1 (en) * | 1999-08-20 | 2005-05-17 | International Business Machines Corporation | Method and system for detecting phase-locked loop (PLL) clock synthesis faults |
| CN1358351A (en) * | 2000-01-10 | 2002-07-10 | 通用电气公司 | Method and apparatus for improving capture and lock characteristics of phase lock loops |
| CN1801622A (en) * | 2004-12-31 | 2006-07-12 | 华为技术有限公司 | Phase-locked loop frequency locking judging method and circuit |
Non-Patent Citations (1)
| Title |
|---|
| JP特开2004-350116A 2004.12.09 |
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| CN101232362A (en) | 2008-07-30 |
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