CN101231883A - Method and apparatus for efficient operation of dynamic random access memory - Google Patents

Abstract

The present invention relates to a method of reading and writing information to a memory cell in communication with one of a word line and a bit line or a complementary bit line. A method according to an embodiment includes: equalizing the bit line and the complementary bit line to a common voltage; addressing the memory cell by connecting the memory cell to one of the bit line or the complementary bit line; reading the memory cell by detecting a first charge stored in the memory cell and transferring the first charge to one of the bit line or the complementary bit line; and writing a second charge to the memory cell by transferring the second charge to the memory cell through an inverter and one of the bit line or the complementary bit line. In one embodiment, the inverter is utilized to transfer only the second charge to the memory cell.

Description

Method and device for efficient operation of dynamic random access memory

technical field

The present invention relates to memory circuits. More particularly, it relates to a dynamic random access memory (DRAM) circuit and a method for its efficient operation.

Background technique

Traditional DRAMs provide random access to memory circuits by storing each bit of data in a single memory cell. Each memory cell includes a capacitor connected to an access transistor. The capacitor has a charge representing a data bit, and the transistor accesses the capacitor during read and write operations. A DRAM circuit includes an array of individual memory cells arranged in rows and columns. Each row of memory cells communicates with a word line, and each column of memory cells communicates with one of a bit line or a complementary bit line. Data is transferred to and from each memory cell by the bit line and the complementary bit line.

Data is generally accessed by cell addresses, which identify memory cells by row and column in the array. The memory circuitry addresses a memory cell in the array by identifying the memory cell located at the intersection of the identified row and column. In order to read or write (store) information to a memory cell, it must first be selected or addressed. Addressing of memory cells is accomplished by inputting signals to a row of detectors and a column of detectors. The row detector activates a word line responsive to the row address, and the selected word line in turn activates the access transistors of all memory cells in communication with the word line. Similarly, a column decoder identifies a pair of bit lines and a complementary bit line that respond to a column address. Thus, when a cell is read, the selected word line activates the row address access transistor and data is latched on the bit line and the complementary bit line communicating with the desired cell.

As described above, the capacitance in the memory cell stores a charge that represents the logic state of the memory. A logic state of 1 represents the charge stored on the capacitor, while a discharged capacitor has a logic state of 0. The bit line and complementary bit line transfer the charge of the capacitor to a sense amplifier, which can detect small charge differences on the bit line pair. The sense amplifier also connects this pair of bit lines to the power rails to read or write to the memory cell.

Traditional sense amplifiers use a back-to-back inverter by cross-connecting a pull-down transistor and a pull-up transistor. Additionally, to perform refresh and write operations, the back-to-back inverter drives an appropriate charge to the bit line pair. If the memory cell contains a charge different from the charge to be written, the inverter will resist or resist the detection operation, thereby delaying the write operation and consuming additional power.

Contents of the invention

In one embodiment, the present invention relates to a method of reading and writing information to a memory cell in communication with one of a word line and a bit line or a complementary bit line, the method comprising: connecting the bit line to the the complementary bit line is equalized to a common voltage; the memory cell is addressed by connecting the memory cell to the bit line or one of the complementary bit lines; and the memory cell is addressed by detecting a first charge stored in the memory cell and transferring a first charge to the bit line or one of the complementary bit lines, reading the memory cell; and by transferring a second charge to the memory cell by an inverter and the bit line or one of the complementary bit lines, The second charge is written into the memory cell. In one embodiment, the step of writing the second charge further includes: using the inverter to communicate with the memory unit; using the inverter to transfer the second charge to the memory unit; and The inverter is released from the memory cell.

In another embodiment, the present invention relates to a memory circuit for data storage, comprising: a memory row having a plurality of memory cells each connected to a word line and a bit line or a complementary bit One of the lines is connected; a column selector is used to selectively identify one of the plurality of memory cells for a read operation or a write operation; a sensor is used for a read operation during detection of a first charge stored in the memory cell; an inverter circuit for driving the voltages of the bit line and the complementary bit line; and a controller for controlling the voltage by applying The bit line or one of the complementary bit lines is driven to a voltage commensurate with a second charge for selectively utilizing the inverter to write the second charge into the memory cell.

In another embodiment, the present invention relates to a sense amplifier circuit for use with a memory device, comprising: an equalizer for driving a bit line and a complementary bit line to a common voltage; a a memory cell capable of communicating with the bit line or one of the complementary bit lines and capable of driving the bit line or one of the complementary bit lines to a first voltage; a column selector for selectively connecting each of the bit line and the complementary bit line to a voltage supply that provides a second voltage; an inverter circuit for when the second voltage is written into the A memory cell is connected to the bit line or one of the complementary bit lines; and a controller for using the inverter to write the second voltage into the memory cell, and for writing the second voltage to the memory cell at the The inverter is deactivated after the memory cell is charged with the second voltage.

Description of drawings

1 is a schematic diagram of a conventional memory cell and a sense amplifier;

FIG. 2 is a graph of voltage variation during a read/write cycle of a conventional memory system;

Fig. 3 is an exemplary storage circuit diagram of an embodiment of the present invention;

Figure 4 is an exemplary method of an embodiment of the present invention;

FIG. 5 is a diagram of voltage variation during a read/write cycle of a memory system according to an embodiment of the present invention.

Detailed ways

FIG. 1 is a schematic diagram of a conventional memory cell and a sense amplifier. In FIG. 1 , memory cell 110 includes PMOS transistor 112 and capacitor 114 . The gate of transistor 112 is connected to word line (WL) 116 . The drain of transistor 112 is connected to bit line (BL) 118 . A second memory unit 120 is arranged opposite to the memory unit 110 . Memory cell 120 includes a PMOS transistor 122 connected to WL 117 and complementary bit line (ZBL) 119 . Transistors 112, 122 form the transistors of the DRAM array. Each transistor 112 or 122 may be an NMOS transistor or a PMOS transistor.

Each BL118 and ZBL119 is respectively connected to a global BL158 and a global ZGBL159 through a column selector 150 . Column selector 150 may include transistor switches 152, 154 that are selectively connected and disconnected to BL 118 and ZBL 119 for read and write operations.

In FIG. 1 , an exemplary sense amplifier 175 includes precharge equalization circuit 130 and back-to-back inverter 140 . The precharge circuit 130 includes transistors 134 , 136 , 138 . Transistors 134, 136, 138 may be NMOS transistors. A precharge circuit 130 is optionally connected to each BL 118 and ZBL 119 to provide precharge equalization between these lines.

The inverter 140 includes transistors 141 , 142 , 143 , 144 . The inverter 140 can be, for example, a back-to-back inverter or a cross-connected CMOS inverter. Transistors 141, 142 may be NMOS transistors, while transistors 143, 144 may be PMOS transistors. As shown in the figure, the gates of the transistors 141 and 143 may be connected to the source electrodes of the transistors 142 and 144, and may also be connected to the ZBL119. Similarly, the gates of transistors 142, 144 can be connected to the drain electrodes of transistors 141, 143, and can also be connected to BL8. Transistor switches 145 , 146 control the inverter 140 . In an embodiment of the present invention, the transistor switch 145 may be a PMOS transistor, and the transistor switch 146 may be an NMOS transistor.

Operation of inverter 140 within conventional sense amplifier 175 will now be described with reference to FIG. 1 and in terms of an exemplary state when memory cell 110 has a logic charge of one. After the equalization step, BL118 is connected to the drain electrodes of transistors 141, 143 at node (a) and to the gate electrodes of transistors 142, 144 at node (b). Similarly, ZBL 119 is connected to the drain electrodes of transistors 142 , 144 at node (c) and to the gate electrodes of transistors 141 , 143 at node (d). The source electrodes of the transistors 143 and 144 are connected to the switch 145 (SP) at the node (e), and the source electrodes of the transistors 141 and 142 are connected to the switch 146 (SN) at the node (f).

During development, WL 116 utilizes memory unit 110 . As the transistor 112 is utilized, the charge stored in the capacitor 114 flows into the BL118, resulting in a slight increase in the voltage of the BL118. BL is connected to the drain electrodes of transistors 141, 143 at node (a), and to the gate electrodes of transistors 142, 144 at node (b); ZBL is connected to the drain electrodes of transistors 142, 144 at node (c) connected at node (d) to the gate electrodes of transistors 141 and 143 . Source electrodes (node (e)) of transistors 143 and 144 are connected to switch 145 (SP), and source electrodes of transistors 141 and 142 are connected to switch 146 (SN).

During detection, switch 146 (SN) is high and switch 145 (SP) is low. In other words, VDD is connected to the node (e) and the source electrodes of the transistors 143 , 144 , and VSS is connected to the node (d) and the source electrodes of the transistors 141 , 142 . During this time, a slightly rising voltage at BL 118 is applied to node (b), causing transistor 142 to turn on slightly. Now that transistor 142 is slightly on, the voltage at node (c) is connected to VSS and pulled down. The voltage at node (c) is also applied to node (d) (ie the gate electrodes of transistors 141 , 143 ), causing transistor 143 to turn on slightly. Since transistor 143 is in an on state and its source electrode at node (e) is connected to VDD, the voltage at node (a) is connected to VDD and pulled up. In turn, the voltage at node (a) is applied to node (b) and further turns on transistor 142 and further connects VSS to node (c). Under this cyclic reaction, the voltage at node (a) (ie, the voltage of BL118) is pulled up quickly, while the voltage at node (c) (ie, the voltage of ZBL119) is quickly pulled down. This situation is often referred to as "full amplitude vibration" and is discussed further in Figure 2.

In an exemplary write operation, precharge equalization circuit 132 is utilized to precharge BL 118 and ZBL 119 to the same voltage (ie, VBL). Next, memory cell 110 is addressed by turning on WL 116 . To select a particular memory cell (ie, cell 112 or 122), one of BL118 or ZBL119 and one of WL116 or WL117 can optionally be used to detect data stored in the corresponding memory. Once BL 118 is connected to capacitor 114, BL 118 will develop substantially the same charge as the capacitor. This stage will be called the development stage. Back-to-back inverter 140 is then utilized by turning on switches 145 and 146 . Once developed, the charge on capacitor 114 can be determined by detecting the voltage difference between BL118 and ZBL119. Finally, column selector 150 is used to connect one of BL118 or ZBL119 to a voltage supply for writing data into memory cell 110 or 120 .

Problems arise during read and write operations when the memory cell contains an opposite charge to the charge to be written. During detection, switch 146 is switched to a low voltage (off state) and switch 145 is switched to a high voltage (on state). That is, the transistors 143, 144 are connected to VDD, and the transistors 141, 142 are connected to VSS. Correspondingly, the inverter 140 pulls up the voltage of BL118 (VBL). If the logic state of the cell is 1, the operation of inverter 140 will resist going to logic state 0. This situation will be further described with reference to FIG. 1 and FIG. 2 together.

FIG. 2 is a graph of voltage variation during a read/write cycle in a conventional memory system. A conventional read/write cycle includes equalizing BL 118 and ZBL 119 , developing the charge of capacitor 114 in BL 118 , sensing the charge of BL 118 opposite ZBL 119 , and writing new data to memory cell 110 .

The first step in the process is to equalize the charge of BL118 and ZBL119. As shown in FIG. 2, in phase A, the precharge equalizer 132 in FIG. 1 connects BL118 and ZBL119 to each other, thereby equalizing the charge to about 0.55v. At this point, the conventional sense amplifier de-energizes the precharge equalizer 132 and utilizes the inverter 140 . It should be noted that the charge equalization voltage can be between about 0V and 0.5V or between 0V and VDD.

To detect the logic state of memory cell 110 , WL 116 is connected to transistor 112 , which connects capacitor 114 to BL 118 . Assuming memory cell 110 has logic state 1, charge will flow from capacitor 114 to BL 118 . The process showing charge development of BL118 is shown in Fig. 2 region B. Since inverter 140 is utilized, it will pull up VBL while pulling down VZBL. As shown in Figure 2, this will make the VBL curve peak and the VZBL curve concave. This delays write operations and increases energy consumption.

In order to write an inverse logic state (ie, low charge) to the memory cell 110, the sense amplifier 175 must undo the existing charge. In an embodiment where the memory cell 110 has a logic state of 1, writing a logic state of 0 would require discharging the capacitor 114 . At this time, column selector 150 is used so that GBL158 applies a voltage to BL118 and ZGBL159 applies a voltage to GBL119. The write operation is shown between points D and A' in Figure 2. The state of various parts of a conventional memory system during a read/write cycle is listed in Table 1 below.

Table 1 Read/Write Operations of Traditional Memory Systems

balanced develop detection write balanced switch 146 Low Low high high Low switch 145 high high Low Low high Inverter 140 close close open open close WL116 close open open open close

In order to overcome the above and other disadvantages, the inverter 140 in one embodiment of the present invention can be disarmed during the detection operation and only used during the write operation. In one embodiment, the deactivated inverter 140 can work with existing circuitry during detection operations without modifying the circuitry. In an alternate embodiment, the circuit may include a controller for utilizing the inverter 140 during write operations.

FIG. 3 is an exemplary memory circuit diagram of an embodiment of the present invention. In FIG. 3, memory cells 110, 120 are connected to word lines 116, 117, respectively. Memory cells 110, 120 are also connected to bit line 118 and complementary bit line 119, respectively. Sense amplifier 175 includes precharge circuit 130 , back-to-back inverter 140 and controller 340 among other components. Although the exemplary memory circuit shown in FIG. 3 shows the controller 340 as part of the sense amplifier 175 , it should be noted that the invention is not so limited and the controller can be independent of the sense amplifier 175 . The controller 340 may include a switch or a switching circuit, a microprocessor controlled by suitable software (eg, firmware), or any other structure that can selectively enable/disable the inverter 140 .

The controller 340 can enable or disable the back-to-back inverter 140 by controlling one or both of the switches 145 (SP) and 146 (SN). In an alternate embodiment (not shown), in addition to or instead of controlling switches 145(SP) and 146(SN), controller 340 may control slave bit line 118 and/or complementary bit line 119 to inverter 140 to enable or disable back-to-back inverter 140 .

According to an embodiment of the present invention, the controller 340 may be configured to utilize the back-to-back inverters 140 during a certain operation. For example, the controller 340 may disable the back-to-back inverters 140 during detection operations while utilizing the back-to-back inverters 140 during write operations. The controller 340 can keep the back-to-back inverter 140 in the deactivated state after the write operation is completed.

Figure 4 is an exemplary method according to an embodiment of the invention. Referring to the process shown in FIG. 4, in step 410, the bit line and the complementary bit line are equalized to a common voltage. In step 420, the memory cell is addressed by connecting the memory cell to one of the bit line or the complementary bit line. In step 430, the memory cell is read by detecting a first charge stored in the memory cell and transferring the stored charge to one of the bit line or the complementary bit line. In step 440, the inverter is first activated, and then the write process is initiated by writing a second charge into the memory cell by transferring the second charge from the inverter to the memory cell (step 450). According to one embodiment, the inverter is deactivated in step 460 once the write operation is complete. This process can be repeated as needed during a read/write cycle.

An exemplary operation of an exemplary embodiment of the present invention may refer to both FIG. 3 and FIG. 5 . FIG. 5 is a voltage variation diagram of a memory system according to an embodiment of the present invention. In FIG. 5 , equalization step A is realized by connecting BL118 and ZBL119 by precharge equalizer 132 . Thereafter, the equalizer 132 is disabled. Controller 340 also deactivates back-to-back inverter 140 by deactivating one or both of switches 145 (SP) and 146 (SN). Next, WL116 can connect capacitor 114 to BL118. The difference in charge between capacitor 114 and BL 118 creates a flow of charge during development phase B. It is worth noting that because the pre-charge equalizer 132 is deactivated, only VBL develops charge, while VZBL remains substantially unchanged.

After point D is the write operation. At this stage, column selector 150 and inverter 140 may optionally be utilized to connect BL118 and ZBL119 to GBL158 and ZGBL159, respectively. Controller 340 may also utilize back-to-back inverters 140 at or about the same time. Once BL 118 is charged, it may write an appropriate charge or logic state to capacitor 114 of memory cell 110 . The end of the write operation is shown at point E in Figure 4. At the end of the write operation, the back-to-back inverters 140 are again deactivated by the controller 340, and the equalization process begins at A' as shown. Table 2 summarizes the operation of the memory system during a read/write cycle according to an embodiment of the present invention.

Table 2 Operation of the memory system during a read/write cycle

balanced develop detection write balanced switch 146 Low Low Low high Low switch 145 high high high Low high Inverter 140 close close close open close WL116 close open open open close

A comparison of Fig. 2 and Fig. 4 shows the advantages of the method of an embodiment of the present invention. For example, the voltage difference of the VBL and VZBL curves (ie, between points B and D) in FIG. 4 during the detection phase is substantially smaller than that in FIG. 2 . The vanished areas between the curves indicate, inter alia, that less energy is consumed during the detection phase and that the writing process is not hindered.

The embodiments disclosed herein are exemplary in nature and serve to illustrate the principles herein. The scope of the principles disclosed herein is not limited by these exemplary embodiments.

Claims (14)

1. one kind is carried out communication with a word line and one of a bit line or a paratope line and reads method with writing information to a memory cell, and this method comprises:

This bit line and this paratope line is balanced to using voltage altogether;

By this memory cell is connected this memory cell of addressing with one of this bit line or this paratope line;

Be stored in one first electric charge in this memory cell and send described first electric charge one of to this bit line or this paratope line by detection, read this memory cell; And

Give this memory cell by transmitting one second electric charge, this second electric charge is write this memory cell by a phase inverter and one of this bit line or this paratope line.

2. the method for claim 1 is characterized in that, the step that described this second electric charge writes further comprises:

Utilize this phase inverter and this memory cell to carry out communication;

Send this second electric charge to this memory cell by this phase inverter; And

This phase inverter is removed from this memory cell.

3. the method for claim 1 is characterized in that, the step of described this memory cell of addressing further comprises: this word line that indication is connected with this memory cell, making can communication between this memory cell and one of this bit line or this paratope line.

4. the method for claim 1 is characterized in that, the described step that reads this memory cell further comprises: this first electric charge is instructed to a detection circuit.

5. the memory circuit of a data storage comprises:

One memory lines, this memory lines has a plurality of memory cells, and each memory cell is connected with one of a bit line or a paratope line with a word line;

One column selector, this column selector is used for optionally discerning one of these a plurality of memory cells, to carry out a read operation or a write operation;

One sensor, this sensor are used for surveying one first electric charge that is stored in described memory cell during a read operation;

One inverter circuit, this inverter circuit are used to drive the voltage of this bit line and this paratope line; And

One controller, this controller are used for optionally utilizing this phase inverter so that this second electric charge is write this memory cell by one of this bit line or this paratope line being urged to a voltage that matches with one second electric charge.

6. memory circuit as claimed in claim 5 is characterized in that, after this second electric charge write this memory cell, this controller was removed this storer.

7. memory circuit as claimed in claim 5 is characterized in that, it further comprises a precharge equalizer, and this precharge equalizer is used for this bit line and this paratope line be urged to uses voltage altogether.

8. memory circuit as claimed in claim 5 is characterized in that, it further comprises a precharge equalizer, and this precharge equalizer is used for driving this bit line and this paratope line before this read operation.

9. memory circuit as claimed in claim 5 is characterized in that, each memory cell further comprises an electric capacity and a transistor.

10. memory circuit as claimed in claim 5 is characterized in that, this data storage is a dynamic randon access memory system.

11. memory circuit as claimed in claim 5 is characterized in that, this phase inverter is a cross-coupled CMOS phase inverter.

12. a detection amplifying circuit that uses jointly with a memory device comprises:

One balanced device, this balanced device are used for a bit line and a paratope line be urged to uses voltage altogether;

One memory cell, this memory cell can carry out communication with one of this bit line or this paratope line, and one of this bit line or this paratope line can be urged to one first voltage;

One column selector, this column selector are used for each this bit line and this paratope line optionally are connected to a voltage source, and this voltage source provides one second voltage;

One inverter circuit, this inverter circuit are used for when this second voltage writes this memory cell this memory cell being connected to one of this bit line or this paratope line; And

One controller, this controller are used to utilize this phase inverter so that this second voltage is write this memory cell, and are used for removing after this memory cell is filled with this second voltage this phase inverter.

13. detection amplifying circuit as claimed in claim 12 is characterized in that, this inverter circuit is a cross-coupled CMOS phase inverter.

14. detection amplifying circuit as claimed in claim 12 is characterized in that this inverter circuit is connected to one of this bit line or this paratope line with this memory cell, to indicate this second voltage to this memory cell.

Images