CN101231808A - display device - Google Patents

Abstract

A display panel is scanned every two lines during a period of binary writing area in the first half of one frame period in partial display (or in small gradation display) and a steady-state current of an output amplifier for buffering gradation signals supplied to the display panel in a non-scanning period in the second half of one frame period is reduced.

Description

display device

This application is based on, and claims the benefit of priority from, Japanese Priority Patent Application No. 2007-010952 filed on January 22, 2007 and Japanese Priority Patent Application No. 2007-011740, filed on January 22, 2007, the latter applications being incorporated by reference All methods are incorporated into this application.

technical field

The present invention relates to a display device and a driving method thereof with a multi-grayscale display mode and a few grayscale display mode (the number of grayscale levels is less than that of the multi-grayscale display mode), and in particular to a liquid crystal display, an organic EL display, and a plasma display , Field emission display and its driving method.

Furthermore, the present invention relates to a display device in which power consumption during partial display is reduced.

Background technique

U.S. Patent Laid-Open 2005/0179677 (Japanese Patent Application Laid-Open No. 2005-234029) discloses an image display device, which is used for writing signals in the non-display area when a multi-row selection part is displayed. A scanning circuit composed of a register and an AND circuit, the shift register and Hsync perform data transmission synchronously, and the AND circuit generates an output signal based on the output signal of the shift register and the Enable signal. Make the Hi level time of the start signal input to the shift register be multiple horizontal periods—for example, 4 horizontal periods, and make the Enable signal have only one horizontal period within multiple horizontal periods—for example, only one within 4 horizontal periods A signal whose horizontal period is Hi level can realize a scanning circuit capable of selecting multiple lines (4 horizontal lines) at the same time.

U.S. Patent No. 6,781,605 (Japanese Patent Application Laid-Open No. 2002-366115) discloses a display device that reduces the number of gradation levels that flow through a circuit that generates a plurality of gradation level voltages to generate unnecessary gradation levels when the number of display gradation levels is small. The current flowing in the circuit part (ladder resistance) of the grade voltage.

Furthermore, in a display device for portable use, it is difficult to implement a partial display mode without reducing power consumption during partial display.

In U.S. Patent 7123247 (Japanese Patent Laid-Open No. 2006-3923), a display device is described. The display device scans the display area of the driving part every frame period, and scans the non-display area outside the display area of the driving part every odd frame period. This reduces power consumption.

Since the operation (clock signal, etc.) of the shift register is the same as that of the normal display even when multiple rows are selected for writing at the same time, US Laid-Open Patent No. 2005/0179677 (Japanese Patent Laid-Open No. 2005-234029 ) is in progress In the case of display, it is difficult to reduce the power consumption of the shift register part. Even in the case of writing black data into the non-display area, voltage writing is performed at a ratio of one horizontal period among multiple horizontal periods, so US Patent Application Publication No. 2005/0179677 (Japanese Patent Laid-Open No. 2005-234029 ) It is difficult to stop the output amplifier for a long time and cut the stable power.

In US Patent No. 6,781,605 (Japanese Patent Application Laid-Open No. 2002-366115 ), the reduction in power consumption is insufficient because the current flowing only in the circuit portion that generates grayscale voltages that are not required for display is reduced.

Also, as described in U.S. Patent No. 7,123,247 (Japanese Patent Application Laid-Open No. 2006-3923), when a partial display is performed by frame inversion, when a display pattern such as a checkered pattern or horizontal stripes is displayed in the partial display area, due to the display Since the frequency of the pattern is high, the power to drive the signal line becomes large.

Contents of the invention

The object of the present invention is to provide a display device and its driving method with reduced power consumption. In particular, it is necessary to suppress the deterioration of image quality and reduce the power consumption of the drive circuit during partial display or low-gradation display.

Another object of the present invention is to provide a display device that reduces power consumption without deteriorating the image quality of partial displays.

In the first display mode (such as non-partial display, multi-grayscale display), the display panel is scanned every n (n is an integer greater than 1) lines during the entire period of one frame period, and in the second display mode (such as Partial display, less grayscale display), the display panel is scanned once every m (m is an integer greater than n) lines during a part of a frame period (for example, the first half period), and the display panel in a frame period At other times (for example, during the second half period), the current flowing in the driving circuit (for example, a buffer amplifier) that drives the display panel is reduced.

For example, a scan circuit is composed of a shift register for shifting an input signal that is Hi level only for two horizontal periods by two horizontal periods, and an AND circuit for converting the input signal of the shift register to Output data (Hi level: 2 horizontal periods) is time-distributed to 2 horizontal periods, and horizontal lines are sequentially selected and displayed according to the time-distributed 2 drive clocks input to the AND circuit. In the case of partial display (8-color display), the period of the control clock of the shift register is shortened to 1/2, and two rows are simultaneously selected by making the two driving clocks have the same phase. Since the dominant capacitance at the time of signal writing is the capacitance of the drain line, even if two rows are selected at the same time to write, the writing time can be the same as the normal case, and the writing time of one screen can be shortened to half of the normal case. . During the non-scanning period, the steady current of the amplifier driving the drain line is reduced. And the shift register of the scanning circuit is also stopped during this period.

Switch frame flip or row flip according to the display pattern in some display areas, and frame flip in non-display areas outside of some display areas.

During partial display, an AC signal for frame inversion or line inversion is generated according to an external control signal indicating partial display. The common voltage is inverted every row or every frame by using the AC signal. Furthermore, the display data of two lines are compared to generate an AC signal.

According to the present invention, since the current flowing to the drive circuit for driving the display panel is reduced at other times within one frame period, power consumption of the drive circuit can be reduced. That is, since the non-scanning time in one frame period can reduce the steady current of the amplifier of the signal output unit, power consumption can be reduced.

According to the present invention, since the period during which the shift register is stopped can be set, the power source for driving the shift register can be stopped during the stop period, and power consumption can be reduced. Since a sufficient write time can be ensured, it is possible to suppress deterioration of image quality during partial display. In addition, since no special signal is required for partial display in the scanning circuit, increase in circuit scale can be suppressed.

According to the present invention, since the display pattern is displayed by inverting the common voltage every row or every frame, it is possible to reduce the charging and discharging power of the signal voltage supplied to the signal line, and power reduction can be expected. Also, since the non-display portion is fixed by frame inversion, low power is ensured. Furthermore, since the display data of 2 lines is compared also for partial display (8 colors), the amount of data to be compared is small, so it can be realized with a small circuit scale.

Description of drawings

FIG. 1 is a structural diagram of a display device according to Embodiment 1 of the present invention.

Fig. 2 is an internal block diagram of an image signal generating circuit according to Embodiment 1 of the present invention.

Fig. 3 is a diagram of the internal structure of the output circuit of Embodiment 1 of the present invention.

FIG. 4 is a structural diagram of a scanning circuit according to Embodiment 1 of the present invention.

Fig. 5 is a structural diagram of a selection circuit in Embodiment 1 of the present invention.

Fig. 6 is a timing chart of non-partial display in Embodiment 1 of the present invention.

FIG. 7 is a timing chart when the scan time is shortened in the partial display mode of Embodiment 1 of the present invention.

Fig. 8 is another timing chart partially shown in Embodiment 1 of the present invention.

Fig. 9 is a display screen of Embodiment 1 of the present invention.

FIG. 10 is a structural diagram of a scanning circuit according to Embodiment 2 of the present invention.

Fig. 11 is a structural diagram of a selection circuit in Embodiment 2 of the present invention.

Fig. 12 is a timing chart of non-partial display in Embodiment 2 of the present invention.

Fig. 13 is a timing chart when the scan time is shortened in the partial display mode according to Embodiment 2 of the present invention.

Fig. 14 is another timing chart partially shown in Embodiment 2 of the present invention.

Fig. 15 is a display screen of Embodiment 2 of the present invention.

Fig. 16 is a structural diagram of a display device of the present invention.

FIG. 17 is an internal block diagram of the signal voltage generating circuit 11 shown in FIG. 16 .

FIG. 18 is an internal block diagram of the gate scanning circuit 13 shown in FIG. 16 .

FIG. 19 is an internal block diagram of the common scanning circuit 12 shown in FIG. 16 .

Fig. 20 is a display image of the display unit.

Fig. 21 is a timing chart when the normal display shown in Fig. 20(a) is performed.

FIG. 22 partially shows a timing chart when the checkered pattern display pattern shown in FIG. 20( b ) is displayed.

FIG. 23 partially shows a timing chart when the white squares display the pattern shown in FIG. 20(c).

FIG. 24 is another block diagram of the signal voltage generating circuit 11 shown in FIG. 16 .

FIG. 25 is a block diagram of the AC judging circuit 91 shown in FIG. 24 .

Fig. 26 is a display image of the display unit.

Fig. 27 is an output diagram of the judgment signal MSEL.

FIG. 28 is a timing chart showing the operation of the AC judging circuit 91 shown in FIG. 25 .

FIG. 29 shows a timing chart when the pattern shown in FIG. 26 is displayed.

Detailed ways

Embodiment 1 is to illustrate that in the partial display/less gray scale display mode, scan every 2 lines during the first half of a frame period and write the gray scale signal (such as gray scale voltage) corresponding to the display data An example in which no line is scanned in the second half of one frame period in the entire screen.

Example 2 is to illustrate that in the partial display/less gray scale display mode, scan every 2 lines in the first half of a frame period and write the gray scale signal corresponding to the display data into the first half For some areas, scan every 4 lines in the remaining 1/3 period of the first half of a frame period and write a grayscale signal of a low grayscale different from the display data, and do not scan in the second half of a frame period Example of any line.

[Example 1]

FIG. 1 is a structural diagram of a display device according to Embodiment 1 of the present invention. In Fig. 1, 1 is a display panel in which a plurality of pixels are arranged in a matrix shape; 2 is a power supply circuit for generating grayscale voltages necessary for display from a power supply voltage; 3 is input of PSL signals, Synchronous signal and other control signals or setting values and display data, control circuit for generating and outputting control signals; 4 is a memory for temporarily storing display data, and 5 is for applying the grayscale voltage corresponding to the display data to the drain line D1 ˜Dm image signal generating circuits, 6 is a scanning circuit for scanning the gate lines G1˜Gn once every row or every few rows.

The display panel 1 includes a plurality of drain lines (signal lines) D1 to Dm and a plurality of gate lines (scanning lines) G1 to Gn, and each pixel is connected to each drain line and each gate line. Each pixel includes a TFT (Thin Film Transistor) and a capacitive element. The power supply circuit 2, the control circuit 3, the memory 4, the image signal generating circuit 5, and the scanning circuit 6 may be composed of a single LSI as a drive circuit, or may be composed of separate LSIs. The memory capacity of the memory 4 is preferably greater than or equal to the capacity capable of storing display data for one frame (one screen). The PSL signal is a signal for controlling switching between a partial motion (action displayed on a partial area) and a non-partial motion (action displayed on a full screen). For example, during a partial operation, the PSL signal is set to a high level, and during a non-partial operation, the PSL signal is set to a low level. Partial actions may rewrite display data only in some display areas and not rewrite display data in other display areas, or may display display data only in some display areas and display black data in other display areas. Therefore, the storage capacity of the memory 4 can only store display data required for a part of the operation. In addition, in the partial operation, the display data is set to 2 gradation levels (1 bit) of ON or OFF for each color of RGB, and in the non-partial operation, the display data is set to all gradation levels (for example, 6 bits or 8 bits). That is, in partial display, a few grayscale display mode (for example, 8-color mode) is formed, and in non-partial display, a multi-grayscale display mode is formed. However, the few grayscale display mode is not limited to 2 grayscales (1 bit), and may be 4 grayscales (2 bits) or 8 grayscales (3 bits). The CPU interface can also be a set value representing partial action or non-partial action instead of the PSL signal. It is preferable to have the memory 4 when partial display is performed, but the memory 4 may not be present when partial display is not performed and only a few grayscales are displayed.

The power supply circuit 2 divides the power supply voltage to generate and output grayscale voltages whose number corresponds to the grayscale indicated by the display data. The control circuit 3 receives a PSL signal and a synchronization signal from a peripheral device, generates a control signal group, and outputs it. The memory 4 stores the display data according to the control signal group, and outputs the display data according to the control signal group. The image signal generating circuit 5 reads display data from the memory 4 according to the control signal group, converts the display data into grayscale voltages, and applies them to the drain lines D1 to Dn. On the other hand, the scanning circuit 6 sequentially applies selection voltages to the gate lines G1-Gn according to the control signal group, and sequentially makes the pixels (pixel rows) connected to the gate lines G1-Gn into the selected state. A pixel in the selected state stores charges corresponding to gray scale voltages in capacitors, and displays luminance corresponding to the charges within one frame period.

FIG. 2 is an internal block diagram of an image signal generating circuit according to Embodiment 1 of the present invention. In Fig. 2, 51 and 52 are data latch circuits for latching the display data of one row, 53 is a DA converter for converting digitized display data into analog grayscale voltages, and 54 is for applying grayscale voltages to Output circuit on the drain lines D1-Dm.

The control signal group includes timing signals, signals for distinguishing partial display and non-partial display according to the PSL signal. In non-partial display, as shown in FIG. 6 , the image signal generating circuit 5 converts the display data into a plurality of gradation voltages VDH to VDL and outputs them. On the other hand, at the time of partial display, as shown in FIGS. 7 and 8 , the image signal generation circuit 5 converts it into two values (VPH, VPL) and outputs them.

The data latch circuit 51 sequentially inputs display data according to the control signal group, and outputs display data for one line. The data latch circuit 52 receives display data for one line according to the control signal group, holds it for one horizontal period, and outputs display data for one line. The DA converter 53 selects, from the plurality of grayscale voltages output from the power supply circuit 2 , each grayscale voltage corresponding to each display data of one line of display data in accordance with the control signal group. The output circuit 54 applies the respective grayscale voltages to the respective drain lines.

FIG. 3 is an internal structure of an output circuit according to Embodiment 1 of the present invention. In FIG. 3 , 541 is an output amplifier for buffering the grayscale voltage, and 542 and 543 are current control circuits for controlling the stable current of the output amplifier 541 . One output amplifier 541 is provided on one drain line D(x).

The BIAS signal (analog voltage) is included in the group of control signals output by the control circuit 3 . The current control circuits 542 and 543 are preferably MOS switches. The BIAS signal is input to the gate of the MOS switch, and the stable current of the output amplifier 541 is controlled by the voltage value of the BIAS signal.

FIG. 4 is a structural diagram of a scanning circuit according to Embodiment 1 of the present invention. 61 in FIG. 4 is a shift register, and 62 is a selection circuit that outputs a gate signal to the gate line according to the output signal of the shift register 61 and the GCK signal (gate clock signal) included in the control signal group. One selection circuit 62 is provided for every two gate lines.

The shift register 61 inputs the ST signal (start signal), the SCK signal (shift clock signal) A and the SCK signal (shift clock signal) B contained in the control signal group output from the control circuit 3, and outputs the SR signal (shift clock signal) Registered signals) 1˜s (s is, for example, n/2). The selection circuit 62 outputs the strobe signal according to time distribution according to the SR signals 1 to s output from the shift register 61, the GCK signal (strobe clock signal) A and the GCK signal (strobe clock signal) B contained in the control signal group Give 2 gate wires.

FIG. 5 is a configuration diagram of a selection circuit according to Embodiment 1 of the present invention. 621 and 622 in FIG. 5 are logic circuits. Although it is preferable to connect a level shift diode between the output signal (logic amplitude) of the slave control circuit 3 and the output (G signals 1 to n) of the selection circuit 62, it may be provided in another place.

The logic circuit 621 inputs the SR signal and the GCK signal A, and applies a selection voltage to the gate line G1 for a period corresponding to the values of the SR signal 1 and the GCK signal A. Similarly, the logic circuit 622 inputs the SR signal and the GCK signal B, and applies a selection voltage to the gate line G1 for a period corresponding to the values of the SR signal and the GCK signal B. Wherein, the logic circuit is, for example, an AND circuit.

Fig. 6 is a timing chart of non-partial display in Embodiment 1 of the present invention. The PSL signal is low level when it is not partially displayed. In order to set the steady current Icnt of the output amplifier 541 to the optimum current I(nml) for non-partial driving, the BIAS signal is set to V(nml) for non-partial display. The output amplifiers 541 of all the drain lines D1 to Dm share the BIAS signal.

The ST signal is a signal that changes from low level to high level every one frame period. The SCK signal is a signal that repeatedly changes between low level and high level within every two horizontal periods. The SCK signal A is high level in the first two horizontal periods of one frame period, and the SCK signal B is high level in the next two horizontal periods. The GCK signal is a signal that repeatedly changes between high level and low level every one horizontal period. The GCK signal A is at a high level for the first horizontal period in one frame period, and the GCK signal B is at a high level for a subsequent horizontal period. The SR signal is a frame-period and a signal at a high level within two horizontal periods. The SR signal 1 is at a high level in the first two horizontal periods of one frame period. SR signal 2 is high level in the next two horizontal periods. The SR signal 3 is at a high level for the next two horizontal periods. That is, the period during which the SR signals 1 to s are at the high level is shifted every two horizontal periods. The G signal (gate signal) is a signal whose period is a frame and is at a high level within one horizontal period. The G signal 1 is at a high level for the first horizontal period of one frame period. G signal 2 is high level in the next horizontal period. The G signal 3 is at a high level in the next horizontal period. That is, the period during which the G signals 1 to n are at the high level is shifted every horizontal period.

When the ST signal is high level, during the high level period of the SCK signal A (2 horizontal periods), the shift register 61 makes the SR signal 1 high level, and then during the high level period of the SCK signal B (2 horizontal periods). Horizontal period) make SR signal 2 high level, and then make SR signal 3 high level during the period when SCK signal A is high level (two horizontal periods). When the SR signal 1 is at a high level, the logic circuit 621 of the selection circuit 62 makes the G signal 1 be at a high level while the GCK signal A is at a high level (one horizontal period). When the SR signal 1 is high level, the logic circuit 622 of the selection circuit 62 makes the G signal 2 high level while the GCK signal B is high level (one horizontal period). On the other hand, a gradation voltage D(x) corresponding to display data is applied from the image signal generating circuit 5 to the respective drain lines D1 to Dm every horizontal period. That is, in the non-partial display, the pixels of the display panel are scanned once per row, and the grayscale voltage corresponding to the display data is applied to each pixel.

FIG. 7 is a timing chart when the scan time is shortened in the partial display mode according to Embodiment 1 of the present invention. The PSL signal is high level in some display modes. In the partial display mode, all pixel rows are sequentially scanned in the first half of a frame period (active period), and no pixel rows are scanned in the second half of a frame period (sleep period). In addition, in the partial display mode, the BIAS signal is set to V(ps) in the first half of one frame period, the constant current Icnt of the output amplifier 541 is set to I(ps), and in the second half of one frame period is set to V(ps). The BIAS signal is set to V(slp), and the steady current Icnt of the output amplifier 541 is set to I(slp). V(nml)>V(ps)>V(slp), by which I(nml)>I(ps)>I(slp). Therefore, (power of output amplifier 541 during non-partial display)>(power of output amplifier 541 during activity during partial display)>(power of output amplifier 541 during sleep during partial display). I(slp) is the current when the output amplifier 541 is in a stop state or a sleep state. Therefore, the partial display mode can reduce the power consumption of the output amplifier.

The ST signal changes from low level to high level every frame period. The SCK signal repeatedly changes between low level and high level in each horizontal period during the first half of one frame period, and becomes low level during the second half of one frame period. SCK signal A is high level in the first horizontal period of a frame period, SCK signal B is high level in the subsequent horizontal period, and in the second half of a frame period, SCK signal A and SCK Signal B is both low. Both the GCK signal A and the GCK signal B are at high level during the first half of one frame period, and are at low level during the second half of one frame period. The SR signal is at a high level during one horizontal period in the first half of a frame period, and is at a low level in the second half of a frame period. The SR signal 1 is at a high level during the first horizontal period of one frame period. SR signal 2 is high level in the next horizontal period. The SR signal 3 is at a high level for one subsequent horizontal period. That is, the period during which the SR signals 1 to s are at the high level is shifted every one horizontal period. The G signal (gate signal) is at a high level for one horizontal period in the first half of one frame period, and is at a low level in the second half of one frame period. Both the G signal 1 and the G signal 2 are at a high level in the first horizontal period of one frame period. Both G signal 3 and G signal 4 are at high level in the next horizontal period. Both G signal 5 and G signal 6 are at high level in the next horizontal period. That is, the G signals 1 to n are set as a set of two adjacent G signals, and the periods during which they are at the high level are shifted every horizontal period.

When the ST signal is high level, the shift register 61 makes the SR signal 1 high level during the high level period of the SCK signal A (1 horizontal period), and then the high level period of the SCK signal B (1 horizontal period). Horizontal period) make SR signal 2 high level, and then make SR signal 3 high level while SCK signal A is high level (one horizontal period). When the SR signal 1 is at a high level, the logic circuit 621 of the selection circuit 62 makes the G signal 1 be at a high level while the GCK signal A is at a high level (one horizontal period). When the SR signal 1 is high level, the logic circuit 622 of the selection circuit 62 makes the G signal 2 high level while the GCK signal B is high level (one horizontal period). On the other hand, in each horizontal period, one voltage D(x) of the two grayscale voltages corresponding to the display data is applied from the image signal generating circuit 5 to each of the drain lines D1 to Dm, During the second half of the period, no gray scale voltage is applied.

The period of the control signal (ST signal, SCK signal A, SCK signal B) of the shift register is shortened by 1/2, and the gate line selection GCK signal A and GCK signal B are set as in-phase signals. In each horizontal period Each output, therefore, the partial display mode can rewrite the voltages of all horizontal scanning lines in half the time of the non-partial display mode. In addition, since the voltage applied to the pixel is only two values of VPL and VPH for ON/OFF control, even if two values are controlled (RGB display is 8-color display), it is difficult to cause image quality deterioration. Therefore, by making the output The stable current of the amplifier is most suitable, which can make it smaller than normal.

In the partial display mode, no pixel row is scanned during the first half of one frame period (sleep period), and all pixel rows are scanned sequentially during the second half of one frame period (active period). Also, the active period and the sleep period do not have to be half of one frame period. If the active period is longer than the sleep period, image quality can be improved, and if the sleep period is longer than the active period, power consumption can be further reduced.

Although not shown in the figure, since it is not necessary to operate the shift register in the second half of one frame period, the power supply for operating the shift register and the amplifier for generating the control signal group (ST signal, SCK signal, GCK signal) The steady current is in sleep state. Accordingly, in the partial display mode, the power consumption of the scanning circuit 6 can be reduced. In addition, although not shown in the figure, in the partial display mode, it is also possible to generate gray-scale voltages not required for display (for example, excluding the maximum and minimum intermediate gray-scale voltages) in the first half period (active period) of one frame period. gradation voltage), and the circuits that generate all the gradation voltages are stopped during the second half period (sleep period) of one frame period. Accordingly, in the partial display mode, the power consumption of the power supply circuit 2 can be reduced. In addition, in the second half period of one frame period, the current flowing in the power supply circuit 2, the image signal generation circuit 5, and the scanning circuit 6 may be reduced to stop the operation of the power supply circuit 2, the image signal generation circuit 5, and the scanning circuit 6, or is dormant.

Fig. 8 is another timing chart of the partial display mode in Embodiment 1 of the present invention. Unlike FIG. 7 , not only the sleep period is provided, but also the writing time (scanning period) for each row is extended (approximately twice the normal time). Thereby, the steady current of the output amplifier is suppressed to be small, and the power consumption is reduced.

The ST signal changes from low level to high level every frame period. The SCK signal repeatedly changes between low level and high level in every two horizontal periods. The SCK signal A is high level in the first two horizontal periods of one frame period, and the SCK signal B is high level in the next two horizontal periods. Both the GCK signal A and the GCK signal B are at high level for the entire period of one frame period. The SR signal takes a frame as a period, and is high level in 2 horizontal periods. The SR signal 1 is at a high level for the first two horizontal periods in one frame period. SR signal 2 is high level in the next two horizontal periods. The SR signal 3 is at a high level for the next two horizontal periods. That is, the period during which the SR signals 1 to s are at the high level is shifted every two horizontal periods. The G signal (strobe signal) takes a frame as a period, and is at a high level within 2 horizontal periods. The G signal 1 and the G signal 2 are at a high level during the first two horizontal periods of one frame period. G signal 3 and G signal 4 are at high level in the next two horizontal periods. G signal 5 and G signal 6 are at high level for the next two horizontal periods. That is, the G signals 1 to n are set as a set of two adjacent G signals, and the periods during which they are at the high level are shifted every two horizontal periods.

When the ST signal is high level, during the high level period of the SCK signal A (2 horizontal periods), the shift register 61 makes the SR signal 1 high level, and then during the high level period of the SCK signal B (2 horizontal periods). Horizontal period) make SR signal 2 high level, and then make SR signal 3 high level during the period when SCK signal A is high level (two horizontal periods). When the SR signal 1 is high level, the logic circuit 621 of the selection circuit 62 makes the G signal 1 high level while the GCK signal A is high level (two horizontal periods). When the SR signal 1 is at a high level, the logic circuit 622 of the selection circuit 62 makes the G signal 2 be at a high level while the GCK signal B is at a high level (two horizontal periods). On the other hand, one voltage D(x) of two gradation voltages corresponding to the display data is applied from the image signal generating circuit 5 to each of the drain lines D1 to Dm every two horizontal periods. That is, in the partial display mode, the pixels of the display panel are scanned every two lines, and one voltage D(x) among the two grayscale voltages corresponding to the display data is applied.

FIG. 9( a ) is a non-partially displayed display screen (corresponding to FIG. 6 ) in Embodiment 1 of the present invention. And, FIG. 9( b ) is a partially displayed display screen (corresponding to FIG. 7 or FIG. 8 ) in Embodiment 1 of the present invention.

In the non-partial display mode, each pixel displays brightness corresponding to multi-grayscale display data (for example, 6 bits or 8 bits). In the partial display mode, every 2 rows of pixels display brightness corresponding to display data with few gray levels (for example, 1 bit). During partial display, the resolution in the vertical direction decreases due to simultaneous selection of two lines, but this is not a problem when performing special displays called "partial display" (for example, information that does not require resolution, such as a clock or receiving status of a mobile phone, etc.) (Especially if the panel resolution is as high as VGA).

[Example 2]

1 to 3 are shared with Embodiment 1.

FIG. 10 is a configuration diagram of a scanning circuit 6 according to Embodiment 2 of the present invention. 63 in FIG. 10 is a shift register, and 64 is a selection circuit. One selection circuit 64 is provided corresponding to four gate lines.

The shift register 63 inputs the ST signal, the SCK signal A, and the SCK signal B included in the control signal group output from the control circuit 3, and outputs SR signals 1 to s (s is, for example, n/4). The selection circuit 64 outputs the strobe signal to the four gates according to the time distribution according to the SR signal 1-s output from the shift register 63, the GCK signal A, the GCK signal B, the GCK signal C and the GCK signal D included in the control signal group. gate line.

Fig. 11 is a configuration diagram of a selection circuit according to Embodiment 2 of the present invention. 641-644 in FIG. 11 are logic circuits.

The logic circuit 641 inputs the SR signal and the GCK signal A, and applies a selection voltage to the gate line G1 for a period corresponding to the values of the SR signal 1 and the GCK signal A. Similarly, the logic circuit 642 inputs the SR signal and the GCK signal B, and applies a selection voltage to the gate line G1 for a period corresponding to the values of the SR signal and the GCK signal B. Similarly, the logic circuit 643 inputs the SR signal and the GCK signal C, and applies a selection voltage to the gate line G3 for a period corresponding to the values of the SR signal and the GCK signal C. Similarly, the logic circuit 644 inputs the SR signal and the GCK signal D, and applies a selection voltage to the gate line G4 for a period corresponding to the values of the SR signal and the GCK signal D.

Fig. 12 is a timing chart of non-partial display in Embodiment 2 of the present invention. The meanings of PSL, BIAS, Icnt, etc. are the same as in Example 1.

The ST signal is a signal that changes from low level to high level every one frame period. The SCK signal is a signal that repeatedly changes between low level and high level in every 4 horizontal periods. The SCK signal A is at high level in the first 4 horizontal periods of one frame period, and the SCK signal B is at high level in the following 4 horizontal periods. The GCK signal is a signal that is at a high level for one horizontal period within a period of four horizontal periods. GCK signal A is high level in the first horizontal period of a frame period, GCK signal B is high level in the next horizontal period, GCK signal C is high level in the next horizontal period, and GCK signal D is high level in the next horizontal period. It is a high level in a subsequent horizontal period. That is, the period in which the GCK signals A to D are at the high level is shifted every horizontal period. The SR signal is a signal at a high level for 4 horizontal periods. The SR signal 1 is at a high level for the first four horizontal periods of one frame period. SR signal 2 is high level in the next 4 horizontal periods. The SR signal 3 is at a high level for the next four horizontal periods. That is, the period during which the SR signals 1 to s are at the high level shifts every four horizontal periods. Also, the period of the SR signals 1 to s is synchronized with the period of the frame. The G signal (gate signal) is a signal that is at a high level for one horizontal period. The G signal 1 is at a high level for the first horizontal period of one frame period. G signal 2 is high level in the next horizontal period. The G signal 3 is at a high level in the next horizontal period. That is, the period during which the G signals 1 to n are at the high level shifts every horizontal period. Also, the cycle of the G signals 1 to n is synchronized with the cycle of the frame.

When the ST signal is high level, during the high level period of the SCK signal A (4 horizontal periods), the shift register 63 makes the SR signal 1 high level, and then during the high level period of the SCK signal B (4 horizontal periods). Horizontal period) make SR signal 2 high level, and then make SR signal 3 high level during the period when SCK signal A is high level (4 horizontal periods). When the SR signal 1 is at a high level, the logic circuit 641 of the selection circuit 64 makes the G signal 1 be at a high level while the GCK signal A is at a high level (one horizontal period). When the SR signal 1 is high level, the logic circuit 642 of the selection circuit 64 makes the G signal 2 high level while the GCK signal B is high level (one horizontal period). When the SR signal 1 is at a high level, the logic circuit 643 of the selection circuit 64 makes the G signal 3 be at a high level while the GCK signal C is at a high level (one horizontal period). When the SR signal 1 is at a high level, the logic circuit 644 of the selection circuit 64 makes the G signal 4 be at a high level while the GCK signal D is at a high level (one horizontal period). On the other hand, a grayscale voltage D(x) corresponding to the display data is applied from the image signal generating circuit 5 to the respective drain lines D1 to Dm every horizontal period. That is, in the non-partial display mode, the pixels of the display panel are scanned once per row, and the grayscale voltage corresponding to the display data is applied to each pixel.

Fig. 13 is a timing chart when the scan time is shortened in the partial display mode according to Embodiment 2 of the present invention. In FIG. 13, partial display is performed on the entire screen, that is, the display data is displayed on the entire screen. In order to simultaneously drive two rows, the period of the control signal (ST signal, SCK signal A, SCK signal B, and GCK signal) of the shift register 63 is 1/2, and GCK signal A=GCK among the four GCK signals Signal B, GCK signal C=GCK signal D). The same effect as that of Embodiment 1 can be obtained with respect to suppressing the output amplifier current during the scan period and stopping the output amplifier from outputting the current during the sleep period (non-scanning period) for partial display.

The ST signal changes from low level to high level every frame period. The SCK signal repeatedly changes between high level and low level every two horizontal periods in the first half of one frame period, and becomes low level in the second half of one frame period. SCK signal A is high level in the first two horizontal periods of a frame period, and SCK signal B is high level in the next two horizontal periods. During the second half of a frame period, SCK signal A and SCK signal B are low level. The GCK signal repeatedly changes between high level and low level every horizontal period in the first half of one frame period, and becomes low level in the second half of one frame period. Both the GCK signal A and the GCK signal B are at high level in the first horizontal period of one frame period. Both the GCK signal C and the GCK signal D are at high level in the next horizontal period. The SR signal is a high signal for two horizontal periods in the first half of one frame period, and is a low level in the second half of one frame period. The SR signal 1 is at a high level during the first two horizontal periods within one frame period. SR signal 2 is high level in the next two horizontal periods. The SR signal 3 is at a high level for the next two horizontal periods. That is, the period during which the SR signals 1 to s are at the high level is shifted every two horizontal periods. The G signal (gate signal) is at a high level for one horizontal period in the first half of one frame period, and is at a low level in the second half of one frame period. Both the G signal 1 and the G signal 2 are at a high level in the first horizontal period of one frame period. Both G signal 3 and G signal 4 are at high level in the next horizontal period. Both G signal 5 and G signal 6 are at high level in the next horizontal period. That is, the G signals 1 to n are set as a set of two adjacent G signals, and the periods during which they are at the high level are shifted every horizontal period.

When the ST signal is high level, during the high level period of the SCK signal A (2 horizontal periods), the shift register 63 makes the SR signal 1 high level, and then during the high level period of the SCK signal B (2 horizontal periods). Horizontal period) make SR signal 2 high level, and then make SR signal 3 high level during the period when SCK signal A is high level (two horizontal periods). When the SR signal 1 is at a high level, the logic circuit 641 of the selection circuit 64 makes the G signal 1 be at a high level while the GCK signal A is at a high level (one horizontal period). When the SR signal 1 is high level, the logic circuit 642 of the selection circuit 64 makes the G signal 2 high level while the GCK signal B is high level (one horizontal period). When the SR signal 1 is at a high level, the logic circuit 643 of the selection circuit 64 makes the G signal 3 be at a high level while the GCK signal C is at a high level (one horizontal period). When the SR signal 1 is at a high level, the logic circuit 644 of the selection circuit 64 makes the G signal 4 be at a high level while the GCK signal D is at a high level (one horizontal period). On the other hand, in each horizontal period, one voltage D(x) of the two grayscale voltages corresponding to the display data is applied from the image signal generating circuit 5 to each of the drain lines D1 to Dm, During the second half of the period, no gray scale voltage is applied.

Fig. 14 is another timing chart of the partial display mode in Embodiment 2 of the present invention. In FIG. 14 , the upper half area is partially displayed, and the remaining lower half area is not displayed (black display). In non-display (black display) areas, resolution reduction caused by simultaneous selection is not a problem. Therefore, the non-scanning period can be made longer by simultaneously selecting four rows. Accordingly, since the time for putting the output amplifier in the sleep state increases, low power consumption can be realized.

The ST signal changes from low level to high level every frame period. The SCK signal repeatedly changes between high level and low level in every 2 horizontal periods during the 2/3 period of the first half period of one frame period (scanning period of the entire display area) (as a binary writing area of the display area) , during the remaining 1/3 period of the first half period of the 1 frame period (the black writing area as the non-display area) repeatedly changes between high level and low level in each horizontal period, and during the second half period of the 1 frame period (period other than the scanning period of the entire display area) is low level. SCK signal A is high level in the first two horizontal periods of a frame period, and SCK signal B is high level in the next two horizontal periods. During the second half of a frame period, SCK signal A and SCK signal B are low level. The GCK signal repeatedly changes between high level and low level in each horizontal period during the 2/3 period (binary writing area) of the first half period of the 1 frame period, and the remaining 1/3 period of the first half period of the 1 frame period During the period (black writing area), the level is high, and the level is low during the second half of one frame period. Both the GCK signal A and the GCK signal B are at high level during the first horizontal period of one frame period, and are at low level during the second half period of one frame period. Both the GCK signal C and the GCK signal D are at a high level in the next horizontal period, and are at a low level in the second half of one frame period. The SR signal takes a frame as a cycle, and is at high level for 2 horizontal periods during the 2/3 period (binary writing area) of the first half period of a frame period, and is at a high level during the remaining 1/3 period of the first half period of a frame period ( black writing area) is high level in one horizontal period, and is low level in the latter half of one frame period. The SR signal 1 is at a high level for the first two horizontal periods in one frame period. SR signal 2 is high level in the next two horizontal periods. The SR signal 3 is at a high level for the next two horizontal periods. That is, the SR signals 1 to s are shifted every 2 horizontal periods during the 2/3 period (binary writing area) of the first half period of the 1 frame period, and the remaining 1 in the first half period of the 1 frame period The period during which the /3 period (black writing area) becomes high level shifts every horizontal period. The G signal (gate signal) is at high level for one horizontal period in the first half of one frame period, and is at low level for the second half of one frame period. Both the G signal 1 and the G signal 2 in the binary writing area are at high level in the first horizontal period of one frame period. The G signal 3 and the G signal 4 of the binary writing area are at a high level in the next horizontal period. Both the G signal 5 and the G signal 6 in the binary writing area are at high level in the subsequent horizontal period. G signal 9 , G signal 10 , G signal 11 , and G signal 12 in the black writing area are all at high level in the first horizontal period of the remaining 1/3 period of the first half period of one frame period. That is, G signals 1 to n are set to a group of two adjacent G signals during the 2/3 period (binary writing area) of the first half period of one frame period, and the period during which they become high level is every one horizontal period. For shifting, in the remaining 1/3 period (black writing area) of the first half period of one frame period, four adjacent G signals are used as a group, and the period during which the level becomes high is shifted every one horizontal period.

When the ST signal is high level, the shift register 63 makes the SR signal 1 high level during the high level period of the SCK signal A, and then makes the SR signal 2 high level during the high level period of the SCK signal B, Next, make the SR signal 3 be high while the SCK signal A is high. When the SR signal 1 is at a high level, the logic circuit 641 of the selection circuit 64 makes the G signal 1 be at a high level while the GCK signal A is at a high level (one horizontal period). When the SR signal 1 is high level, the logic circuit 642 of the selection circuit 64 makes the G signal 2 high level while the GCK signal B is high level (one horizontal period). When the SR signal 1 is at a high level, the logic circuit 643 of the selection circuit 64 makes the G signal 3 be at a high level while the GCK signal C is at a high level (one horizontal period). When the SR signal 1 is at a high level, the logic circuit 644 of the selection circuit 64 makes the G signal 4 be at a high level while the GCK signal D is at a high level (one horizontal period). On the other hand, in the 2/3 period (binary writing area) of the first half period of one frame period, the image signal generating circuit 5 applies a signal corresponding to the display data to each of the drain lines D1 to Dm every horizontal period. One of the two grayscale voltages D(x); in the remaining 1/3 period (black writing area) of the first half period of a frame period, apply the corresponding black data during each horizontal period Grayscale voltage; no grayscale voltage is applied during the second half of 1 frame period.

FIG. 15( a ) is a non-partially displayed display screen (corresponding to FIG. 12 ) in Embodiment 2 of the present invention. And, FIG. 15(b) is a display screen (corresponding to FIG. 13 ) in which the entire screen is partially displayed in Embodiment 2 of the present invention. Fig. 15(c) is a display screen (corresponding to Fig. 14 ) in which the upper half of the entire screen is partially displayed in Embodiment 2 of the present invention.

The low resolution of the entire screen in the partial display area ( FIG. 15( b )) and the upper half area in FIG. 15( c ) is the same as in the first embodiment.

The present invention can be used for a liquid crystal display of a mobile phone.

[Example 3]

FIG. 16 is a structural diagram of a display device of the present invention. In FIG. 16, the input signal INPUT_SIG and the control signal REG are input into the signal voltage generation circuit 11 from the outside, and the signal voltage generation circuit 11 generates and applies the signal line SIGn (n=1 to N, N is an integer) according to the input signal INPUT_SIG. signal voltage. Furthermore, the signal voltage generating circuit 11 generates an AC signal M to be supplied to the common scanning circuit 12 based on the input control signal REG.

Also, the signal voltage generating circuit 11 generates the scanning signal SFT_ST supplied to the common scanning circuit 12 and the gate scanning circuit 13 according to the synchronization signal in the input signal INPUT_SIG, and generates the high-level common voltage VCOMH and the low-level common voltage supplied to the common scanning circuit 12 . level common voltage VCOML.

The common scanning circuit 12 uses the input scanning signal SFT_ST and the AC signal M to select any one of the input high-level common voltage VCOMH and low-level common voltage VCOML, and drives the common line COMn (n=1～N, N is an integer).

The gate scanning circuit 13 generates a gate voltage using the input scanning signal SFT_ST, and drives the gate line Gn (n=1˜N, N is an integer).

The thin film transistor 14 is connected to the intersection of the gate line Gn and the signal line SIGn, and the display element 15 is driven by the thin film transistor 14 . The gate line Gn is scanned once per row, and the signal voltage of each row from the signal line SIGn and the common voltage of each row from the common line COMn are applied to the display elements, thereby driving the thin film transistor 14 and the display element 15 of each row , this process is repeated during one frame to display an image corresponding to the signal voltage.

FIG. 17 is an internal block diagram of the signal voltage generating circuit 11 shown in FIG. 16 . In FIG. 17 , the input signal INPUT_SIG is stored in the memory 22 through the control circuit 21 . The control circuit 21 controls the memory 22 and the DAC/output circuit 23, and the DAC/output circuit 23 converts the data read from the memory 22 into a signal voltage VSIG. Then, the control signal REG is stored in the register 24 and read by the control circuit 21 , and the control circuit 21 generates the AC signal M by the AC signal generating circuit 25 . Furthermore, the control circuit 21 generates the scan signal SFT_ST by the scan signal generation circuit 26 based on the synchronization signal in the input signal INPUT_SIG. In addition, the high-level common voltage VCOMH and the low-level common voltage VCOML are generated by the common voltage generating circuit 27 .

During partial display, the partial display area of the display unit or the AC signal M (frame inversion/row inversion) is controlled by the settings stored in the register 24 .

FIG. 18 is an internal block diagram of the gate scanning circuit 13 shown in FIG. 16 . In Fig. 18, the scan signal SFT_ST is input into the strobe shift register GSRn (n=1～N, N is an integer) the strobe shift register GSR1 in the initial stage, and is sequentially transmitted according to the strobe clocks SFT_GCK1 and SFT_GCK2 having a mutual inversion relationship, A gate voltage is output from each gate shift register GSRn to a gate line Gn. In addition, the gate clocks SFT_GCK1 and SFT_GCK2 are supplied from a signal voltage generation circuit.

FIG. 19 is an internal block diagram of the common scanning circuit 12 shown in FIG. 16 . In Fig. 19, the scanning signal SFT_ST is input into the public shift register CSRn (n=1～N, N is an integer) of the public shift register CSR1 of the first section, and is transmitted sequentially according to the public clocks SFT_CCK1 and SFT_CCK2 which have a mutual inversion relationship. The shift register CSRn outputs a common shift pulse. In addition, the common clocks SFT_CCK1 and SFT_CCK2 are supplied from the signal voltage generation circuit.

The common shift pulse from the common shift register CSRn is input to the common selector COM_SELn (n=1～N, N is an integer), and the common selector COM_SELn is synchronized with the common shift pulse. When the AC signal M is high level , select a high-level common voltage VCOMH to output to the common line COMn, and select a low-level common voltage VCOML to output to the common line COMn when the AC signal M is at a low level.

Fig. 20 is the display image of the display part, the figure (a) is the normal display when the display part displays multi-gray levels, and the figure (b) is the checkered pattern displayed on the part of the display part (Dot), and the The case where black squares are displayed on the non-display part, and (c) of the figure shows the case when white squares are displayed on part of the display part and black squares are displayed on the non-display part. Here, 4×8 dots are displayed on the display portion, 4×4 dots are displayed on the partial display portion, and 4×4 dots are displayed on the non-display portion, but the present invention is not limited thereto.

In FIG. 20( a ), corresponding to the selected gate line Gn, a multi-grayscale signal voltage VSIGn is applied to the normal display area, and the common voltage is frame-inverted to perform a display different from the grayscale at each dot. In FIG. 20( b ), the checkered pattern is displayed by row inversion in the display area, and black squares are displayed by frame inversion in the non-display area. In FIG. 20( c ), white squares are displayed with frame inversion in the display area, and black squares are displayed with frame inversion in the non-display area.

Fig. 21 shows the timing when the normal display shown in Fig. 20(a) is performed. In FIG. 21 , the scan signal SFT_ST representing one frame period is sequentially shifted in synchronization with the gate clocks SFT_GCK1 and SFT_GCK2 to generate gate voltages VGn (n=1 to 8). The multi-gray-scale signal voltage VSIGn (n=1˜4) of each row corresponding to each gate voltage VGn is displayed sequentially in a frame period.

At this time, a high-level common voltage VCOMH or a low-level common voltage VCOML is selected in synchronization with the common clocks SFT_CCK1 and SFT_CCK2 according to the level of the AC signal M to generate a common voltage VCOMn (n=1-8).

In FIG. 21 , the frame inversion of inversion every frame period causes the common voltage VCOMn to alternately become the high-level common voltage VCOMH and the low-level common voltage VCOML. In the first frame period, the common voltage VCOMn is at a high level, and in the next frame period, the common voltage VCOMn is at a low level.

Fig. 22 is a timing chart when the checkered display pattern shown in Fig. 20(b) is partially displayed. The difference between FIG. 22 and FIG. 21 is that the AC signal M in the partial display area (4×4 dots) in the first half is inverted every line. Therefore, the common voltages VCOM1˜VCOM4 are inverted every row. Therefore, by setting the signal voltages VSIG1 to VSIG4 at low level, high level, low level, and high level during the four-line scanning period, a checkered display pattern can be displayed. In the next frame period, by inverting the AC signal M, the signal voltages VSIG1 - VSIG4 are also inverted to high level, low level, high level, and low level.

That is, since the common voltage is inverted for each row, it is not necessary to make the signal voltage high or low for each row, and all four rows can be made high or low. This is because the frequency of the signal voltage becomes lower, and therefore the driving power of the signal voltage generating circuit that drives the signal line with the signal voltage of the lower frequency decreases, and the power consumption of the display device decreases.

In addition, in the second half of the non-display area (4×4 dot black square display), since common voltages VCOM5-VCOM8 are at high level, the frame is inverted, so signal voltages VSIG1-VSIG4 are at high level for black display. In the next frame period, since the common voltages VCOM5-VCOM8 are low-level frame inversion, the signal voltages VSIG1-VSIG4 are low-level for black display.

Here, as shown in FIG. 17, the AC signal M is set by the control circuit 21 based on the control signal stored in the register 24, and the control circuit 21 lowers the frequency of the signal voltage VSIG according to the display pattern.

Fig. 23 is a timing chart when the white square display pattern shown in Fig. 20(c) is partially displayed. The difference between FIG. 23 and FIG. 22 is that frame inversion is not performed in part of the display area. Therefore, in the first frame period in which the common voltage VCOMn is at the high level, the signal voltage VSIGn is at the low level in a part of the display area, and the signal voltage VSIGn is at the high level in the non-display area where black squares are displayed. In the next frame period, these voltages are inverted.

In this way, when a white square is partially displayed, as shown in FIG. 22 , when performing row inversion, the signal voltage VSIGn must also be inverted row by row. Therefore, the frequency of the signal voltage VSIGn is high, so frame inversion is used instead of row inversion.

[Example 4]

FIG. 24 is another block diagram of the signal voltage generation circuit 11 shown in FIG. 16 , and an AC judgment circuit 91 is provided in the signal voltage generation circuit 11 shown in FIG. 17 . The AC judging circuit 91 compares the data (Data) of 2 lines transmitted from the memory 22 under the control of the control circuit 21, and outputs to the AC signal generating circuit 25 whether or not to reverse the common voltage according to the reference value REF set in the register 24. The judgment signal MSEL. The AC signal generation circuit 25 inverts the AC signal M indicated by the control circuit 21 according to the judgment signal MSEL.

FIG. 25 is a block diagram of the AC judging circuit 91 shown in FIG. 24 . In FIG. 24, the data of the previous row transmitted from the memory 22 is stored in the data storage circuit 101, and the data of the previous row (DataR) is compared with the data of the current row (Data) by the data comparison circuit 102. The data comparison circuit 102 is composed of, for example, an EOR circuit. When each data of the previous row is the same as each data of the current row, each data outputs 0, and each data outputs 1 at the same time, and compares the output of each data of this row. Total value and reference value REF. When the comparison result is that the total value of the output is greater than or equal to the reference value REF, in order to suppress the charge and discharge power of the signal line, the common voltage is row-inverted, and when the total output value is less than the reference value REF, the common voltage is not row-inverted.

26 is a display image of the display unit for explaining the above-mentioned operation. The display unit is 4×8 dots, the partial display unit is 4×4 dots, and the non-partial display unit is 4×4 dots, but the present invention is not limited thereto.

27 is an output diagram of the judgment signal MSEL when the number of data in the horizontal direction is set to 4 and the reference value REF is set to 2, as shown in FIG. When the judgment signal MSEL is 0, row inversion is not performed on the common voltage, and when MSEL is 1, row inversion is performed on the common voltage.

FIG. 28 is a timing chart showing the operation of the AC judging circuit 91 with respect to the display patterns shown in FIG. 26 . In Fig. 28, starting from the second row, each data of the current row and each data of the previous row are added (Exor) bit by bit, and the result is accumulated (Sum). When the accumulation (Sum) is more than 2, the judgment signal is activated. MSEL is at a high level, and when the accumulation (Sum) is not less than 2, the judgment signal MSEL is at a low level.

That is, when the correlation between the respective data of the current row and the respective data of the previous row is low (Sum is above 2), the common voltage is row inverted, and when the correlation is high (Sum is less than 2), the common voltage is not row inverted, Proceed to frame flip. The frequency of the signal voltage can thus be reduced.

In addition, since the first row is subject to the AC inversion of the display element (liquid crystal) itself, the judgment signal MSEL is not used. That is, an AC inversion synchronized with a synchronizing signal in an input signal from the outside is formed. This point is also the same as in the alternating current reversal of the non-display portion from the fifth row. Therefore, as shown in FIG. 28, since the judgment signal MSEL affects the second to fourth rows, the other rows may be either high or low.

FIG. 29 is a timing chart showing the above-mentioned operation. Unlike the previous timing charts, the AC signal M is inverted using the judgment signal MSEL. In FIG. 29, the frequency of the signal voltage VSIn is reduced by performing row inversion on the common voltage VCOM3 of the third row.

Claims (29)

1. the display device with the 1st display mode and the 2nd display mode is characterized in that,

In above-mentioned the 1st display mode, during 1 image duration whole in, display panel of every n line scanning, n is the integer more than 1,

In above-mentioned the 2nd display mode, during the part in above-mentioned 1 image duration, the once above-mentioned display panel of every m line scanning is during other in above-mentioned 1 image duration, reduce to flow to the electric current of the driving circuit that is used to drive above-mentioned display panel, m is for being big integer than n.

2. display device as claimed in claim 1 is characterized in that,

Above-mentioned driving circuit comprises the output circuit to above-mentioned display panel output gray level level signal,

Reduce the electric current that flows through in the above-mentioned output circuit, as the electric current that flows to above-mentioned driving circuit.

3. display device as claimed in claim 1 is characterized in that,

Above-mentioned driving circuit comprises the amplifier of buffering to the gray shade scale signal of above-mentioned display panel output,

Reduce the steady current of above-mentioned amplifier, as the electric current that flows to above-mentioned driving circuit.

4. display device as claimed in claim 3 is characterized in that,

Above-mentioned driving circuit comprises the translation circuit that video data is transformed into the gray shade scale signal,

The above-mentioned gray shade scale signal of above-mentioned amplifier buffer after by above-mentioned translation circuit conversion.

5. display device as claimed in claim 1 is characterized in that,

When setting the dirty electric current to above-mentioned driving circuit of above-mentioned the 1st display mode is that the electric current that flows to above-mentioned driving circuit under Inml, above-mentioned the 2nd display mode during the part in above-mentioned 1 image duration is the electric current that flows to above-mentioned driving circuit under Ips, above-mentioned the 2nd display mode during other in above-mentioned 1 image duration when being Islp, Inml＞Ips＞Islp.

6. display device as claimed in claim 1 is characterized in that,

Display gray scale number of degrees under above-mentioned the 2nd display mode is less than the display gray scale number of degrees under above-mentioned the 1st display mode.

7. display device as claimed in claim 6 is characterized in that,

Display gray scale number of degrees under above-mentioned the 1st display mode is whole gray shade scale numbers,

Display gray scale number of degrees under above-mentioned the 2nd display mode is 2 gray shade scales of each color of red, green, blue.

8. display device as claimed in claim 1 is characterized in that,

The viewing area of the above-mentioned display panel under above-mentioned the 2nd display mode is less than the viewing area of the above-mentioned display panel under above-mentioned the 1st display mode.

9. display device as claimed in claim 8 is characterized in that,

The viewing area of the above-mentioned display panel under above-mentioned the 1st display mode is whole viewing areas of above-mentioned display panel,

The viewing area of the above-mentioned display panel under above-mentioned the 2nd display mode is the part viewing area of above-mentioned display panel.

10. display device as claimed in claim 8 is characterized in that,

Under above-mentioned the 2nd display mode, every m line scanning is the part viewing area of above-mentioned display panel once,

Under above-mentioned the 2nd display mode, per 1 line scanning is other viewing areas of above-mentioned display panel once, and 1 is the integer bigger than m.

11. display device as claimed in claim 1 is characterized in that,

Said n is 1,

Above-mentioned m is 2,

During the part in above-mentioned 1 image duration the scan period of rewriting the gray shade scale signal of above-mentioned viewing area in above-mentioned 1 image duration,

It during in above-mentioned 1 image duration other scan period of rewriting above-mentioned viewing area gray shade scale signal in addition in above-mentioned 1 image duration.

12. a display device has the 1st display mode and the 2nd display mode, it is characterized in that,

In above-mentioned the 1st display mode, during 1 image duration whole in, display panel of every n line scanning, n is the integer more than 1,

In above-mentioned the 2nd display mode, during the part in above-mentioned 1 image duration, the once above-mentioned display panel of every m line scanning is during other in above-mentioned 1 image duration, be used in the driving circuit that drives above-mentioned display panel and be in and stop or dormancy dormancy state, m is for being big integer than n.

13. a display device is characterized in that, comprising:

Display panel possesses and is arranged in rectangular a plurality of pixels;

Signal generating circuit is to above-mentioned display panel output and the corresponding gray shade scale signal of video data; And

Sweep circuit, scanning will receive the pixel column of above-mentioned gray shade scale signal successively;

Whole pixels of the above-mentioned display panel of scanning stop the scanning of pixel during the part of above-mentioned sweep circuit in 1 image duration during other in above-mentioned 1 image duration,

Above-mentioned signal generating circuit comprises above-mentioned video data is transformed into the translation circuit of above-mentioned gray shade scale signal and buffering by the amplifier of the above-mentioned gray shade scale signal after the above-mentioned translation circuit conversion,

During in above-mentioned 1 image duration other, reduce the steady current of above-mentioned amplifier.

14. a display device is characterized in that possessing:

Many gate lines;

Many signal wires intersect with above-mentioned gate line;

A plurality of display elements have been applied in the signal voltage from above-mentioned signal wire;

Concentric line applies the common electric voltage that frame overturns to each display element of going;

The gated sweep circuit, the once above-mentioned gate line of each line scanning;

Signal voltage generation circuit drives above-mentioned signal wire; And

The common scanning circuit scans above-mentioned concentric line;

Above-mentioned signal voltage generation circuit generates the AC signal that makes the capable upset of above-mentioned common electric voltage according to the control signal from the outside, make the capable upset of the common electric voltage that is applied on the concentric line with above-mentioned common scanning circuit, and the low signal voltage of generated frequency composition comes drive signal line.

15. display device as claimed in claim 14 is characterized in that,

Above-mentioned signal voltage generation circuit possesses:

Register, storage is from the control signal of outside;

The AC signal generative circuit is according to the setting value generation AC signal of this register; And

Control circuit, the signal voltage that the generated frequency composition is low.

16. display device as claimed in claim 15 is characterized in that,

Above-mentioned control circuit basis generates signal voltage from the display mode of the input signal of outside.

17. display device as claimed in claim 14 is characterized in that,

Above-mentioned signal voltage generation circuit generates the AC signal make above-mentioned common electric voltage frame upset when common display, when part showed, the display mode according to from the input signal of outside generated the AC signal that makes capable upset of above-mentioned common electric voltage or frame upset.

18. display device as claimed in claim 14 is characterized in that,

Above-mentioned common scanning circuit possesses public selector switch, and this public selector switch is selected high level common electric voltage or low level common electric voltage according to AC signal.

19. display device as claimed in claim 14 is characterized in that,

Above-mentioned signal voltage generation circuit has:

Storer, storage is from the input signal of outside;

Exchange decision circuitry, compare each data and generation judgement signal from adjacent 2 row of above-mentioned storer, when their relevance was hanged down, described judgement signal made the capable upset of above-mentioned common electric voltage, when their relevance was high, described judgement signal made above-mentioned common electric voltage frame upset; And

The AC signal generative circuit generates AC signal according to above-mentioned judgement signal.

20. display device as claimed in claim 19 is characterized in that,

Above-mentioned interchange decision circuitry has:

Data storage circuitry, storage is from the data of the delegation of above-mentioned storer; And

Data comparison circuit will compare from each data of the lastrow of above-mentioned data storage circuitry and each data when previous row from above-mentioned storer;

According to the result of above-mentioned data comparison circuit with from the reference value of outside, generate and judge signal.

21. display device as claimed in claim 20 is characterized in that,

Above-mentioned data comparison circuit has the EOR circuit, and this EOR circuit carries out XOR with each data of lastrow and each data of current line.

22. display device as claimed in claim 19 is characterized in that:

When above-mentioned interchange decision circuitry shows in part, generate the judgement signal that makes the capable upset of above-mentioned common electric voltage according to reference value from the outside.

23. a display device is characterized in that possessing:

A plurality of display elements are arranged in rectangular;

Signal voltage generation circuit applies and the corresponding signal voltage of importing from the outside of picture signal above-mentioned display element;

Sweep circuit, scanning will apply the row of the above-mentioned display element of above-mentioned signal voltage; And

Common voltage generation circuit applies common electric voltage to above-mentioned display element on the contrary with above-mentioned signal voltage;

Under non-part display mode, to each above-mentioned picture signal frame, be that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element with above-mentioned common electric voltage,

Under the part display mode, display element for the viewing area, to each above-mentioned picture signal frame or row, with above-mentioned common electric voltage is that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element, display element for non-display area, is that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element to each above-mentioned picture signal frame with above-mentioned common electric voltage

For the display element of the above-mentioned viewing area under the above-mentioned part display mode, selecting according to the displaying contents of above-mentioned picture signal is that each above-mentioned picture signal frame is switched the voltage that remains in the above-mentioned display element, or each above-mentioned picture signal row switched the voltage that remains in the above-mentioned display element.

24. display device as claimed in claim 23 is characterized in that:

Above-mentioned common electric voltage comprises the common electric voltage and the low level common electric voltage of high level,

Above-mentioned common voltage generation circuit switches the positive pole and the negative pole that remain on the voltage in the above-mentioned display element by switching the common electric voltage and the low level common electric voltage of above-mentioned high level.

25. display device as claimed in claim 23 is characterized in that:

Display element for the above-mentioned viewing area under the above-mentioned part display mode, when the frequency content of the displaying contents of above-mentioned picture signal is high, each above-mentioned picture signal row is switched the voltage that remains in the above-mentioned display element, when the frequency content of the displaying contents of above-mentioned picture signal is low, each above-mentioned picture signal frame is switched the voltage that remains in the above-mentioned display element.

26. display device as claimed in claim 23 is characterized in that:

The gray shade scale number of the picture signal that will show in above-mentioned viewing area under the above-mentioned part display mode is less than the gray shade scale number of the above-mentioned picture signal under the above-mentioned non-part display mode.

27. a display device is characterized in that possessing:

A plurality of display elements are arranged in rectangular;

Signal voltage generation circuit applies and the corresponding signal voltage of importing from the outside of picture signal to above-mentioned display element;

Sweep circuit, scanning will apply the row of the above-mentioned display element of above-mentioned signal voltage; And

Common voltage generation circuit applies common electric voltage to above-mentioned display element on the contrary with above-mentioned signal voltage;

Under the many multi-grayscale display modes of the gray shade scale of above-mentioned picture signal, to each above-mentioned picture signal frame, be that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element with above-mentioned common electric voltage,

Under the few few gray shade scale display mode of the gray shade scale of above-mentioned picture signal, to each above-mentioned picture signal frame or row, be that benchmark switches positive pole and the negative pole that remains on the voltage in the above-mentioned display element with above-mentioned common electric voltage,

Under above-mentioned few gray shade scale display mode, according to the displaying contents of above-mentioned picture signal, selection is that each above-mentioned picture signal frame is switched the voltage that remains in the above-mentioned display element, or each above-mentioned picture signal row switched the voltage that remains in the above-mentioned display element.

28. display device as claimed in claim 27 is characterized in that:

Above-mentioned common electric voltage comprises the common electric voltage and the low level common electric voltage of high level,

Above-mentioned common voltage generation circuit switches the positive pole and the negative pole that remain on the voltage in the above-mentioned display element by switching the common electric voltage and the low level common electric voltage of above-mentioned high level.

29. display device as claimed in claim 27 is characterized in that:

Under above-mentioned few gray shade scale display mode, when the frequency content of the displaying contents of above-mentioned picture signal is high, each above-mentioned picture signal row is switched the voltage that remains in the above-mentioned display element, when the frequency content of the displaying contents of above-mentioned picture signal is low, each above-mentioned picture signal frame is switched the voltage that remains in the above-mentioned display element.

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