CN101231551A - Multiprocessor system and efficiency adjusting method thereof - Google Patents

Abstract

A multiprocessor system and a performance adjusting method thereof are provided, wherein a plurality of processing units of the multiprocessor system at least comprise a first processing unit and a second processing unit, and the performance adjusting method comprises the following steps: first, the loads of the processing units are detected to obtain a plurality of corresponding detection results. Then, it is judged whether or not the load is concentrated on one of the processing units based on the detection results. Finally, if the load is concentrated on the first processing unit, the power supply of the first processing unit is increased or the efficiency of the first processing unit is improved.

Description

Multi-processor system and its performance adjustment method

technical field

The invention relates to a technology of a multiprocessor system, and in particular to a multiprocessor system and a performance adjustment method thereof.

Background technique

Please refer to FIG. 1 , which is a schematic diagram of a known multi-processor system. The multiprocessor system 100 is generally assembled on the motherboard of a computer device, and this multiprocessor system 100 usually includes more than two central processing units (CPU), such as: a first processing unit 110 and a second processing unit 120 , and respectively supply power to the first voltage regulator module (Voltage Regulator Module, VRM) VR1 and the second voltage regulator module VR2 of these processing units 110, 120.

All current voltage regulation modules can adjust the output voltage according to the core voltage level requirement of the processing unit. For example, the first voltage regulation module VR1 can generate a dynamic voltage identification code (Voltage Identification Code, VID for short) according to the state change of the related pins in the first processing unit 110, so as to generate a corresponding voltage (Vcorel) for the first processing unit 110. Unit 110. In this way, when the first processing unit 110 is under different operating loads, it can obtain proper power supply from the first voltage regulation module VR1, so as to increase processing performance or avoid unnecessary power consumption. Similarly, the second voltage regulation module VR2 also independently supplies power to the second processing unit 120 in the same manner, so details are not repeated here.

In addition, processors with multi-level working modes have also been developed on the market, which can be in normal mode (C0-Active), pause mode (C1-Halt), frequency stop mode (C2-Stop Clock), deep sleep mode (C3 -Deep Sleep), and ultra-deep sleep mode (C4-Deeper Sleep) to automatically change the core frequency and operating voltage of the processor to adapt to the system load situation. What's more, many desktop and notebook computers use EIST (Enhanced Intel Speed-Step Technology) technology (enhanced ultra-deep sleep technology) to improve the system's high heat and high power consumption problems. Other related performance adjustment technologies such as CPU Throttling or other major computer manufacturers for CPU will not be described in detail.

However, as we all know, even at the current hardware level of dual-CPU or multi-core processors, it is still rare to have correspondingly supported software programs. For example, due to the difficulty of program design, game developers almost still write game programs in a single thread (Single Thread) manner, causing the multiprocessor system 100 to use only one processing unit (such as the first processing unit 110) to The computer game software is executed while the unused second processing unit 120 is idle. Or, even if the above-mentioned processing units 110, 120 are allocated with a considerable amount of computing data, often because the program is not optimized for the multi-processor architecture when it is written or compiled, so that the data still has correlation rather than completely independent. At this time, the second processing unit 120 may have to wait for the output result of the first processing unit 110 before starting to perform the calculation it is responsible for, that is, the above-mentioned processing units 110 and 120 cannot fully exert their computing capabilities at the same time. Although the above-mentioned processing units 110, 120 theoretically have the computing power that is multiples of that of a single processor, when encountering the above-mentioned computing bottleneck, the improvement of the overall performance of the system is still limited, and it cannot show the expected multi-processing compared with a single processor. machine computing advantages.

Contents of the invention

In view of this, the object of the present invention is to provide a multi-processor system and its performance adjustment method, so as to avoid the computing bottleneck when the multi-processor system has concentrated load, and can improve the overall performance of the system (Throughput Improvement).

According to the object of the present invention, a performance adjustment method of a multi-processor system is proposed, and the multi-processor system includes a first processing unit and a second processing unit. The above performance adjustment method includes the following steps: (a) detecting the loads of the above processing units to obtain a plurality of corresponding detection results; (b) judging whether the load is concentrated on one of the processing units according to the above detection results a processing unit; and (c) if the load is concentrated on the above-mentioned first processing unit, increasing the power supply of the first processing unit, or increasing its computing capability at the same time.

In an embodiment of the present invention, step (c) further includes increasing the operating frequency or internal frequency multiplier of the first processing unit.

In an embodiment of the present invention, the multiprocessor system further includes a control unit and a frequency generator, the control unit is electrically connected to the above processing units and the frequency generator, and the frequency generator is electrically connected to the above processing units respectively. The control unit increases the operating frequency of the first processing unit by controlling the frequency generator.

In an embodiment of the present invention, the control unit controls the frequency generator through an inter-integrated circuit bus (I ² C Bus), so that the control unit can increase the operating frequency of the first processing unit through the inter-integrated circuit bus.

In an embodiment of the present invention, in step (c), it further includes reducing the power supply, operating frequency, internal frequency multiplier, or power state of the second processing unit.

In an embodiment of the present invention, in step (a), the loads of the above-mentioned processing units are detected by means of hardware monitoring or software monitoring.

According to the object of the present invention, a multi-processor system is proposed, and the multi-processor system includes a plurality of processing units, a frequency generator, a power supply device, a plurality of switching units, and a control unit. The above-mentioned frequency generators are respectively electrically connected to the above-mentioned processing units, and can respectively provide operating frequencies to the above-mentioned processing units. The above-mentioned power supply device can respectively provide the power required by the above-mentioned processing units. The aforementioned switching units are respectively electrically connected between the power supply device and the aforementioned processing units. The control unit is electrically connected to the processing units, the frequency generator, and the switching units, so that the control unit can adjust the power provided by the power supply device to the processing units by controlling the switching units, and The control unit can adjust the operating frequency provided to the above processing units by controlling the frequency generator.

In an embodiment of the present invention, the control unit uses hardware monitoring means or software monitoring means to detect the loads of the aforementioned processing units, so as to obtain a plurality of corresponding detection results.

In an embodiment of the present invention, the hardware monitoring means is implemented by using a detection unit, and the detection unit is electrically connected to the above-mentioned processing units and the control unit respectively.

In an embodiment of the present invention, the control unit judges whether the load is concentrated on one of the above processing units according to the above detection results. If the load is concentrated on the first processing unit, the control unit controls the operations of the switching units to increase the power supply of the first processing unit. The control unit can also control the frequency generator through the inter-integrated circuit bus to increase the operating frequency of the first processing unit. Alternatively, the control unit can also increase the internal frequency multiplier of the first processing unit.

In an embodiment of the present invention, the aforementioned switch units are transistor switches.

In an embodiment of the present invention, the software monitoring means uses an application program or an operating system to read the usage rates of the above processing units.

To sum up, the beneficial effect of the present invention is that it can flexibly allocate the power supply obtained by each processing unit in a multi-processor system, ensure that the high-load processing unit can operate at full speed to perform calculations and shorten the time of calculation bottlenecks

In order to make the above objects, features, and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of an existing multiprocessor system.

FIG. 2 is a schematic diagram of a multi-processor system according to a preferred embodiment of the present invention.

FIG. 3 is a flowchart of a performance adjustment method for a multi-processor system according to a preferred embodiment of the present invention.

Detailed ways

As mentioned above, in FIG. 1, when the load is concentrated on the first processing unit 110, the second processing unit 120 may always be idle or temporarily wait for the operation result of the first processing unit 110 in power-saving mode; While the second processing unit 120, the first processing unit 110 likewise does not contribute to shortening the processing time. That is to say, under the current lack of programming that supports multiple CPUs, the overall performance of the multi-processor system 100 is greatly limited by the respective performances of these processing units 110, 120, and it fails to perform simultaneous multi-tasking to improve efficacy. Therefore, improving the performance of each processing unit can be an improvement method without changing the software design.

Taking the first processing unit 110 as an example, traditionally, a higher CPU level (with higher power consumption) can be replaced to directly improve the computing power, but in fact, it usually needs to consume a higher power supply than the original rated power of the processor. , the high-level first processing unit 110 can fully operate at full speed. However, if the power supply of the corresponding first voltage regulation module VR1 is insufficient, it will face the dilemma that the first processing unit 110 cannot operate at full speed even with a variety of performance regulation techniques as mentioned above. The multi-processor system provided by the embodiment of the present invention can flexibly allocate the power supply obtained by each processing unit, so as to ensure that the processing unit with high load can operate at full speed to perform calculations and shorten the time of calculation bottlenecks. At the same time, there is no need to reserve additional power supply capacity for possible future CPU upgrade space when designing the voltage module.

Please refer to FIG. 2 , which is a schematic diagram of a multi-processor system according to a preferred embodiment of the present invention. The multiprocessor system 200 includes a first processing unit 210, a second processing unit 220, a power supply device 230, a plurality of switch units 241, 242, 243, 244, a control unit 250, a frequency generator frequency generator 260, and a detection unit 270. In this embodiment, the aforementioned processing units 210 and 220 are all central processing units (CPUs). In other embodiments, the detection unit 270 can be omitted, and instead implemented by software detection means, the detailed description will be described later.

The frequency generator 260 is electrically connected to the processing units 210 and 220 respectively, and the frequency generator 260 can provide operating frequencies (also called external frequency) to the processing units 210 and 220 respectively.

The power supply device 230 is used to provide the power required by the processing units 210 and 220 mentioned above. In this embodiment, the power supply device 230 includes a first voltage regulation module 231 and a second voltage regulation module 232, wherein the first voltage regulation module 231 and the second voltage regulation module 232 can respectively provide the above-mentioned processing units 210, 220 required power supply. It is worth mentioning that, under the initial setting, the power supply device 230 is as shown in FIG. processing unit 220 .

The switch units 241 - 244 are electrically connected between the power supply device 230 and the processing units 210 , 220 respectively. As shown in FIG. 2 , the switch unit 241 is electrically connected between the first voltage regulation module 231 and the first processing unit 210 to control the power supply path between the first voltage regulation module 231 and the first processing unit 210 . The switch unit 243 is electrically connected between the second voltage regulation module 232 and the first processing unit 210 to control another power supply path between the second voltage regulation module 232 and the first processing unit 210 . The switch units 242 and 244 respectively control the two power supply paths between the power supply device 230 and the second processing unit 220 by using an electrical connection manner similar to the switch units 241 and 243 . In this way, the power generated by the power supply device 230 can be output to the processing units 210 and 220 through the power supply paths controlled by the switch units 241 - 244 .

The control unit 250 is electrically connected to the processing units 210, 220, the frequency generator 260, and the switch units 241-244, so that the control unit 250 can adjust the power supply device 230 to provide to the processing unit 210 by controlling the switch units 241-244. , 220, and the control unit 250 can adjust the operating frequency provided to the processing units 210, 220 by controlling the frequency generator 260.

That is to say, the control unit 250 provided in this embodiment can control the switch units 241-244 according to the load of each processing unit 210, 220, so as to flexibly adjust the power supply or operating frequency required by each processing unit 210, 220, wherein the control The unit 250 detects the loads of the processing units 210 and 220 by means of hardware monitoring or software monitoring, so as to obtain a plurality of corresponding detection results. The description of how to detect the load of the processing units 210 and 220 will be described in detail later.

In addition, in this embodiment, it is worth mentioning that the control unit 250 can control the frequency generator 260 to generate the external signals of the above-mentioned processing units 210 and 220 through, for example, an inter-integrated circuit (Inter-integrated Circuit, I ² C) bus. frequency signal. In other embodiments, the control unit 250 can also control the external frequency signal generated by the frequency generator 260 through other interfaces.

In this embodiment, the switch units 241 - 244 are implemented by MOSFETs Q1 - Q4 . In other embodiments, the switch units 241 - 244 can also be implemented by bipolar junction transistor (BJT) transistors, or other electronic switches that can be controlled by voltage or current. Since it is a known technology to use a transistor as a switch circuit, it will not be repeated in this specification.

In this embodiment, the control unit 250 is a South Bridge chip (South BridgeChip) assembled on the motherboard, which can control the first processing unit 210, the second processing unit 220, the switch units 241-244, and the frequency generator 260 operation. In other embodiments, the control unit 250 can also be a Super IO Chip or other equivalent chip sets.

Compared with the known technology, although the above-mentioned voltage regulation modules 231 and 232 are also independently powered to the above-mentioned processing units 210 and 220 under the initial setting, but through the design of the switch units 241-244, the voltage regulation module 231 It can supply power to the second processing unit 220 , and the voltage regulation module 232 can also supply power to the first processing unit 210 . That is, the control unit 250 can control the power supply paths of the voltage regulation modules 231 , 232 to the processing units 210 , 220 by controlling the actions of the switch units 241 - 244 .

For example: the control unit 250 may control the switch unit 243 to turn on (Turn-ON), and control the switch unit 244 to turn off (Turn-Off), so that the second voltage regulation module 232 only supplies power to the first processing unit 210 . Similarly, the control unit 250 may control the switch unit 243 to turn off, and control the switch unit 244 to turn on, so that the second voltage regulation module 232 only supplies power to the second processing unit 220 . Similarly, the control unit 250 may control the switch unit 243 to be turned on, and control the switch unit 244 to be turned on, so that the second voltage regulation module 232 supplies power to the first processing unit 210 and the second processing unit 220 at the same time. Similarly, the control unit 250 can also control the operation of the switch units 241 , 242 to control the power supply path from the first voltage regulation module 231 to the first processing unit 210 and/or the second processing unit 220 .

In this way, for example, when the load is concentrated on the first processing unit 210 , the control unit 250 can appropriately control the switch units 241 - 244 in response to the situation, so that the voltage corresponding to the second processing unit 220 with low load The output power of the regulation module 232 is partly diverted to the first processing unit 210 with high load. That is, the above-mentioned voltage regulation modules 231 and 232 can supply power to the first processing unit 210 at the same time, so that the first processing unit 210 can obtain enough power to operate at full speed.

As the load of the processing unit increases, its load current will also increase accordingly. Therefore, a preferred embodiment of the present invention uses a hardware monitoring method to detect the load of the above-mentioned processing units 210, 220, as the adjustment of the control unit 250. A measure of the performance of multiprocessor systems. In this embodiment, the hardware monitoring means can be implemented by the detection unit 270 .

The detection unit 270 is electrically connected to the power input terminals of the processing units 210, 220 and the control unit 250 to detect the load current or voltage of the processing units 210, 220, so that the control unit 250 can judge the processing unit 210 , 220 load. Furthermore, the detection unit 270 can be implemented by using the working mode of the PWM controllers (PWMController) in the multiple voltage regulation modules 231, 232 or using a power amplifier (Operational Amplifier) and a comparison circuit implemented with multiple precision resistors. For example: the multiprocessor system 200 can use the duty cycle signal of the pulse width modulation controller or the comparison circuit design of the impedance component to detect the load current, and output the detection result to the control unit 250, so as to realize the monitoring by means of hardware monitoring CPU usage.

In addition, it is worth mentioning that the current operating system installed on the computer usually has a built-in task manager (Task Manager) to provide information such as CPU load (or called CPU utilization (CPUUtilization)). In addition, the user can also use a custom application program (Application, AP) to know the CPU load. Therefore, in other embodiments of the present invention, the multiprocessor system 200 can use a software monitoring method to monitor the CPU load, for example: use the above-mentioned operating system or AP to obtain CPU usage information in real time, so as to determine whether the above-mentioned processing units 210 , 20 loads, and then provide appropriate power to the above-mentioned processing units 210, 220.

For example, when the usage rate of the first processing unit 210 is higher than the usage rate of the second processing unit 220 to a default value, the control unit 250 can determine that the load is concentrated on the first processing unit according to the above CPU usage information. 210, this situation may be caused by the first processing unit 210 executing an application program with a single thread (Thread) feature, or the second processor 220 waiting for the operation result of the first processor 210. At this time, the control unit 250 can control the operation of the switch unit, so that the above-mentioned voltage regulation modules 231 , 232 change from the original initial settings to jointly output most of the power to the first processing unit 210 .

To sum up, in the embodiment of the present invention, a hardware monitoring means or a software monitoring means may be used to detect the loads of the processing units 210 and 220 mentioned above. In this way, the control unit 250 can adjust the power supply of the power supply device 230 according to the detection results of the loads of the processing units 210 and 220 mentioned above. In one embodiment, the control unit 250 can adjust the amount of power supplied by the power supply device 230 to the processing units 210 , 220 according to the load difference of the processing units 210 , 220 . For example: the control unit 250 adjusts the power supply ratio output by the second voltage regulation module 232 to the first processing unit 210 and the second processing unit 220 according to the degree of load difference between the above-mentioned processing units 210 and 220 (for example: the control unit 250 controls the switching unit 243, 244 use the switching design of the turn-on current of the transistor components Q3 and Q4 that can be adjusted by the control unit 250), so that the second processing unit 220 with low load can keep the minimum operation, and at the same time transfer the power supply to the first processing unit as much as possible. Unit 210.

In order to better understand the performance adjustment operation of the preferred embodiment of the present invention, please refer to FIG. 2 and FIG. 3 together, wherein FIG. 3 is a flow chart of the performance adjustment method of the multi-processor system according to the preferred embodiment of the present invention. In step S305, the detection unit 270 detects the load of each processing unit 210, 220 to generate at least one detection result, and the detection unit 270 transmits the detection result to the control unit 250, wherein the detection unit 270 can use hardware monitoring means or software Monitoring means to detect the load of the processing units 210,220.

In step S310, the control unit 250 determines whether the current system load is concentrated on a single processing unit according to the detection result. That is, the control unit 250 determines whether the difference between the load of the first processing unit 210 and the load of the second processing unit 220 is greater than a default value according to the detection result. For example, if the load of the first processing unit 210 is greater than the load of the second processing unit 220 and the load difference is greater than a default value, the control unit 250 determines that the load is concentrated on the first processing unit 210 . In step S310, if the control unit 250 determines that the system load is not concentrated on a single processing unit, that is, the system is under normal conditions, the control unit 250 maintains normal operation (the above-mentioned processing units 210, 220 can also maintain the initial settings) And the detection unit 270 continues to detect the loads of the processing units 210 and 220 . If the control unit 250 determines that the system load is concentrated on a single processing unit, step S313 is executed.

In step S313 , the control unit 250 may choose to combine the following steps to reduce the power consumption of the processing unit with low usage. These steps include: changing the power state (Power State) of other processing units with low usage rate; making the processing unit with low usage rate enter the EIST mode with low power consumption; frequency.

For example, the power states of the processing units 210, 220 may include normal mode (C0-Active), suspend mode (C1-Halt), frequency stop mode (C2-Stop Clock), deep sleep mode (C3-DeepSleep), and Super deep sleep mode (C4-Deeper Sleep). In this embodiment, the multiplication coefficients of the processing units 210 and 220 may range from 1.5 to 20 times. In step S313 , the low usage rate processing unit is, for example, the second processing unit 220 . The control unit 250 can change the power state of the second processing unit 220 from the C0 state to the C1 state. Of course, in other embodiments, the control unit 250 can also change the power state of the second processing unit 220 from a more power-consuming state to a state of C1. Go to other more power-saving states, for example: change C0 state to C4 state. Similarly, the control unit 250 can also adjust the internal frequency multiplier of the second processing unit 220 from a high multiple to a low multiple, for example, from 12 times to 8 times.

In addition, the control unit 250 can reduce the operating frequency (also known as external frequency) of the low-utilization processing unit through the I2C bus. That is, the control unit 250 controls the frequency generator 260 through the I2C bus, so that the operating frequency output from the frequency generator 260 to the low-utilization processing unit (eg, the second processing unit 220 ) is reduced. Generally speaking, the external frequency of the processing units 210, 220 can be 50, 60, 66.6, 75, 83.3, 95, 100, 112, 124, 133, . . . , 333 MHz and other speeds. Therefore, in the above example, the frequency generator 260 originally outputs a working frequency of 124 MHz to the second processing unit 210 , and the control unit 250 can control the frequency generator 260 to provide a working frequency of 100 MHz to the second processing unit 220 .

Then, in step S315 , the control unit 250 distributes the redundant power supply of other processing units with low load (low usage rate) to the processing unit with concentrated load (high usage rate) by controlling the switch units 241 - 244 .

In principle, the processing unit with load concentration will first obtain the maximum power supply, and the control unit 250 will control the voltage regulation modules and switch units 241-244 corresponding to other processing units with lower load according to the load concentration situation, so as to The power output to the corresponding processing unit is reduced, so that the processing unit with load concentration can obtain more power. In this way, it is possible to ensure that the high-load processing unit can operate at full speed to perform calculations, thereby shortening the time of load concentration. For example: if the control unit 250 determines that the load is concentrated on the first processing unit 210, the control unit 250 can supply most of the power provided by the second voltage regulation module 232 to the first processing unit by controlling the operation of the switch units 241-244. Unit 210.

It should be noted that, in this embodiment, step S313 is regarded as a subroutine coordinating with step S315. Before step S315 is executed, step S313 can be optionally executed. In other embodiments, step S325 and step S330 can also be executed by selecting one of them or in any combination, and FIG. 3 only shows a combination of one of the execution modes. In other embodiments, after step S315 is executed, only step S330 may be executed, and then step S335 is continued.

Next, step S325, step S335, and other subsequent steps will be continuously explained. In addition, the method and principle of adjusting the working frequency are as follows.

In step S325, the control unit 250 increases the operating frequency (also known as external frequency) of the processing unit with high usage rate through the I ² C bus. That is, the control unit 250 controls the frequency generator 260 through the I ² C bus, so that the operating frequency output from the frequency generator 260 to the processing unit with high usage rate (for example, the first processing unit 210 ) increases. For example: the frequency generator 260 originally outputs a working frequency of 124 MHz to the first processing unit 210 , and the control unit 250 controls the frequency generator 260 to provide a working frequency of 133 MHz to the first processing unit 210 .

In step S330 , the control unit 250 increases the internal frequency multiplier of the high-usage processing unit to improve system performance. For example: in this example, the high-usage processing unit is, for example, the first processing unit 210 . The control unit 250 can then adjust the internal multiplier of the first processing unit 210 from a low multiple to a high multiple, for example, from 12 to 14.

In step S335, the detection unit 270 continues to detect the load of each processing unit 210, 220, and outputs the detection result to the control unit 250, so that the control unit 250 can determine whether the computing bottleneck has been solved (step S340). If the computing bottleneck is not resolved, continue to execute step S335. If the computing bottleneck has been solved, execute step S345, and restore the initial settings through the control of the control unit 250, and then continue to execute step S305.

In other embodiments, if the computing bottleneck is not resolved, the control unit 250 may also determine whether the load difference between the processing units is greater than a default value, if the load difference between the processing units is less than the default value (indicating that the load is still concentrated situation, but improved compared to before adjustment), then the first adjusted power supply ratios for the processing units 210 and 220 mentioned above can be maintained, and step S335 can be continued. If the load difference between the processing units is still greater than the default value, continue to execute step S315 to adjust the power supply ratio again. For example: it is known from the detection result of the detection unit 270 that the load of the centralized power supply to the first processing unit 210 is not reduced or even higher, and the control unit 250 further reduces the power supplied by the second voltage regulation module 232 to the second processing unit 220, At the same time, the power supply of the second voltage regulation module 232 to the first processing unit 210 is further improved.

The multi-processor system and its performance adjustment method disclosed in the above-mentioned embodiments of the present invention can flexibly allocate the power supply obtained by each processing unit in the multi-processor system, and ensure that the high-load processing unit can operate at full speed to perform calculations and shorten the processing time. The time of computing bottlenecks.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (17)

1. A performance adjustment method for a multiprocessor system, wherein a plurality of processing units of the above multiprocessor system at least comprise a first processing unit and a second processing unit, and the above-mentioned performance adjustment method is characterized in comprising the following steps: (a) Detecting the loads of the aforementioned processing units to obtain a plurality of corresponding detection results; (b) According to the above-mentioned detection results, determine whether the load is concentrated on one of the above-mentioned processing units; and (c) If the load is concentrated on the first processing unit, increasing the power supply of the first processing unit. 2 . The performance adjustment method according to claim 1 , wherein in the step (c), it further includes increasing the operating frequency or internal frequency multiplier of the first processing unit. 3 . 3. The performance adjustment method according to claim 2, wherein said multiprocessor system further comprises a control unit and a frequency generator, and said control unit is electrically connected to said processing units and said frequency generator respectively , and the frequency generator is electrically connected to the processing units respectively, and the control unit increases the operating frequency of the first processing unit by controlling the frequency generator. 4. The performance adjustment method according to claim 3, wherein the control unit controls the frequency generator through an inter-integrated circuit bus. 5. The performance adjustment method according to claim 2, wherein in the step (c), the operating frequency of the first processing unit is increased through an inter-integrated circuit bus. 6 . The performance adjustment method according to claim 1 , further comprising reducing the power supply, operating frequency, internal frequency multiplier, or power state of the second processing unit in the step (c). 7 . 7. The performance adjustment method according to claim 1, characterized in that: in the step (a), a hardware monitoring means or a software monitoring means is used to detect the loads of the processing units. 8. A multiprocessor system comprising: multiple processing units; a frequency generator, electrically connected to the above-mentioned processing units respectively, and providing operating frequencies to the above-mentioned processing units respectively; A power supply device, which provides the power required by the above-mentioned processing units; a plurality of switch units, respectively electrically connected between the above-mentioned power supply device and the above-mentioned processing units; and A control unit, electrically connected to the above-mentioned processing units, the above-mentioned frequency generator, and the above-mentioned switching units, so that the above-mentioned control unit can adjust the power provided by the above-mentioned power supply device to the above-mentioned processing units by controlling the above-mentioned switching units power supply, and the control unit can adjust the operating frequency provided to the processing units by controlling the frequency generator. 9. The multi-processor system according to claim 8, wherein the control unit uses a hardware monitoring means or a software monitoring means to detect the loads of the processing units, so as to obtain a plurality of corresponding detection results. 10. The multi-processor system according to claim 9, wherein the hardware monitoring means is implemented by a detection unit, and the detection unit is electrically connected to the processing units and the control unit respectively. 11. The multi-processor system according to claim 9, wherein the control unit determines whether the load is concentrated on one of the processing units according to the detection results. 12. The multiprocessor system according to claim 11, wherein the processing units include a first processing unit and a second processing unit, and if the load is concentrated on the first processing unit, the control unit controls The operation of the aforementioned switching units is used to increase the power supply of the aforementioned first processing unit. 13. The multiprocessor system according to claim 11, wherein the processing units include a first processing unit and a second processing unit, and if the load is concentrated on the first processing unit, the control unit controls The above-mentioned frequency generator is used to increase the working frequency of the above-mentioned first processing unit. 14. The multi-processor system according to claim 13, wherein the control unit controls the frequency generator through an inter-integrated circuit bus. 15. The multiprocessor system according to claim 11, characterized in that: said processing units include a first processing unit and a second processing unit, if the load is concentrated on said first processing unit, said control unit increases The internal frequency multiplier of the above-mentioned first processing unit. 16. The multi-processor system according to claim 8, wherein said switch units are transistor switches. 17. The multi-processor system according to claim 8, wherein the software monitoring means uses an application program or an operating system to read the usage rates of the processing units.

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