CN101226213B - Method and apparatus for detecting electric machine phase current - Google Patents
Method and apparatus for detecting electric machine phase current Download PDFInfo
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- CN101226213B CN101226213B CN2008100187811A CN200810018781A CN101226213B CN 101226213 B CN101226213 B CN 101226213B CN 2008100187811 A CN2008100187811 A CN 2008100187811A CN 200810018781 A CN200810018781 A CN 200810018781A CN 101226213 B CN101226213 B CN 101226213B
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Abstract
A motor phase current measurement method comprises using a Hall current sensor to sense a phase current, converting the current signal output from the secondary band of the sensor into a voltage signal, integrating the voltage signal to be compared with a nominal voltage to obtain a pulse width signal, and digitalizing the pulse width signal in a FPGA/CPLD to obtain result, wherein the Hall current sensor senses the phase current, the secondary output of the sensor via a sampling resistance is connected with an integrating circuit which output is connected with one input of a comparator, another input of the comparator is connected with a normal potential, the output of the comparator is connected with the input of a digitalizing circuit, the current output from the secondary band of the sensor is converted into a voltage signal to be integrated by the integrating circuit and fed into the comparator to be compared with the normal potential, the output of the comparator and the pulse generated by a pulse generator are fed into the digitalizing circuit which outputs the sampling result, and the CPLD/FPGA is the core carrier of the digitalizing circuit.
Description
Technical field
The invention belongs to the machinery check and repair field, specifically a kind of electric machine phase current detection method and device.
Background technology
At present, the detection method of phase current is a lot of in electric machine control system, and for example Chinese patent 02129122.5 " a kind of detection method of motor phase current " comprises step 1: motor is stopped operating and with the A/D converter zero clearing; Step 2: phase current detector by the gap periods of 62.5us detect the simulation phase current values of N a certain phase of motor, A/D converter converts these simulation phase current values to digital phase current values; Step 3: these digital phase current values are added up, then adding up and, draw the mean deviation value of a certain mutually digital phase current values of motor and preserve with gained divided by detecting times N; Step 4: actuating motor and with the A/D converter zero clearing; Step 5: phase current detector by the gap periods of 62.5us detect the simulation phase current values of N a certain phase of motor, A/D converter converts these simulation phase current values to digital phase current values; Step 6: the digital phase current values of gained is added up, then with gained add up and divided by detecting times N, draw the mean value of a certain mutually digital phase current values of motor, the mean value with the digital phase current values of gained deducts the mean deviation value then, draws final measured value.Chinese patent 03129703.X " a kind of phase current detection method of motor " comprising: step 1: control device is the detected A of read current pick-up unit, B, C three-phase electricity flow valuve successively; Step 2: control device is abandoned the wherein C phase current values of duty ratio maximum in the A that reads, B, C three-phase electricity flow valuve, only selects A phase and B phase current values; Step 3: control device calculates the C phase current values according to formula Ic=-(IA/IB).
The detecting element of the phase current of the electric current detecting method that these are commonly used adopts A/D converter, does not exist poor stability, accuracy of detection high but adopt high-precision A/D can cause shortcomings such as cost rising again.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the present invention proposes a kind of electric machine phase current detection method and device, can realize accuracy of detection height, good stability, anti-interference, easy operating, concrete technical scheme is as follows:
A kind of electric machine phase current detection method comprises the steps: to respond to phase current with Hall current sensor, and the current signal of sensor secondary output converts voltage signal to; Again the gained voltage signal is carried out integration, and compare, obtain pulse width signal with normal potential; In FPGA/CPLD, the gained pulse width signal is carried out digitized processing then, obtain end value.
Hall current sensor induction phase current converts voltage signal to through sampling resistor, enters operational amplifier and electric capacity composition integrating circuit after this voltage signal process divider resistance dividing potential drop; Integrating circuit is used for the error voltage summation is shown as a low-pass filter for input signal, then shows as high-pass filtering for quantizing noise; Like this, most of quantizing noise just is pushed to higher frequency range, and total noise power does not change, but variation has taken place in the distribution of noise;
Then, the integrating circuit output signal enters comparer and zero potential compares, if the input voltage of comparer rises, comparer can produce the high level " 1 " of greater number, and vice versa; The output of comparer feeds back to operational amplifier through analog switch again, constitutes a feedback loop, and the effect of feedback loop is to make the average output voltage of integrating circuit approach the datum of comparer;
The result and the reference clock of comparer pass through analog switch, constitute a DAC, how decision feeds back: during comparer output " 0 ", one tunnel output positive electricity of analog switch is pressed onto integrating circuit, when comparer output " 1 ", analog switch output negative electricity is pressed onto integrating circuit; In like manner, when reference clock was " 0 ", another road output positive electricity of analog switch was pressed onto integrating circuit, and when reference clock was " 1 ", analog switch output negative electricity was pressed onto integrating circuit;
The output signal of comparer is with sampling rate output 1bit data stream, is loaded with digital filter and digital decimation device in the described FPGA/CPLD, extracts Useful Information from this data stream, and data rate is reduced to available level; Digital filter is asked on average the 1bit data stream, removes the outer quantizing noise of band; Use the high-frequency clock pulse pad count again, data pick-up is carried out in the output of digital filtering, obtain the sampled result digital value.
A kind of electric machine phase current pick-up unit of realizing said method comprises Hall current sensor, sampling resistor, integrating circuit, comparer and digitized processing circuit; Hall current sensor induction phase current, the secondary output of sensor connects integrating circuit by sampling resistor, the output of integrating circuit connects an input end of comparer, and another input end of comparer connects normal potential, and the output of comparer connects the input end of digitizing treatment circuit; The electric current of sensor secondary output converts the sampled voltage signal to through sampling resistor, this voltage signal enters comparer after the integrating circuit integral operation and normal potential compares, and the pulse width signal of comparer output is exported the sampled result digital value after the digitized processing processing of circuit.
Also be provided with divider resistance between described sampling resistor and integrating circuit, described sampled voltage signal imports integrating circuit again into after the divider resistance dividing potential drop.This device also comprises analog switch, and the output of described comparer connects the input end of analog switch; Import the input end of analog switch behind the frequency divider frequency division of described high-frequency clock pulse CLK in CPLD/FPGA into; Analog switch output connects the input end of integrating circuit, constitutes feedback loop, makes the average output voltage of integrating circuit approach the datum of comparer.The normal potential of described comparer input is a zero potential.The frequency range of described high-frequency clock pulse CLK is 20～400MHz, frequency is directly proportional with sampling precision, 20MHz sampled result scope is 0～2000,40MHz sampled result scope is 0～4000,60MHz sampled result scope is 0～6000,100MHz sampled result scope is 0～10000,400MHz sampled result scope is 0～40000, can select appropriate frequency according to design requirement and CPLD/FPGA device performance in the design process, if that use is the CPLD/FPGA of band phaselocked loop, then can select a low-frequency clock, at the high frequency clock of device inside through needing obtaining behind the phaselocked loop.
Compared with prior art, method of the present invention and device have good stability, are easy to characteristics such as realization, sampling precision height.This method is comparable to but is better than general ∑-Δ type AD.Current detection circuit+CPLD/FPGA program equivalence is an A/D converter.The A/D converter higher than performance from cost is cheap, and the anti-interference that detects and stable better than A/D converter.
Description of drawings
Fig. 1 is the circuit theory diagrams of electric machine phase current pick-up unit
Fig. 2 contains circuit diagram for the CPLD/FPGA of electric machine phase current pick-up unit
Fig. 3 is signal output waveform figure of the present invention
Among Fig. 1, the SC1 Hall element; The U1A differential operational amplifier; The U2A comparer; The U3 analog switch; U4CPLD; T3CMP clock reference (40KHz); CLK high frequency clock (40MHz)
Among Fig. 2, the U1 frequency divider; U2 logic maker; The U3D trigger; U4 digital decimation device; The U5 buffer register; The U6 reverser
Embodiment
The invention will be further described below in conjunction with embodiment.
A kind of electric machine phase current detection method comprises step: respond to phase current with Hall current sensor, the current signal of sensor secondary output converts voltage signal to; Again the gained voltage signal is carried out integration, and compare, obtain pulse width signal with normal potential; In CPLD/FPGA, the gained pulse width signal is carried out digitized processing then, obtain end value.
Its process is that Hall current sensor induction phase current converts voltage signal to through sampling resistor, enters operational amplifier and electric capacity composition integrating circuit after this voltage signal process divider resistance dividing potential drop; Integrating circuit is used for the error voltage summation is shown as a low-pass filter for input signal, then shows as high-pass filtering for quantizing noise; Like this, most of quantizing noise just is pushed to higher frequency range, and total noise power does not change, but variation has taken place in the distribution of noise;
Then, the integrating circuit output signal enters comparer and zero potential compares, if the input voltage of comparer rises, comparer can produce the high level " 1 " of greater number, and vice versa; The output of comparer feeds back to operational amplifier through analog switch again, constitutes a feedback loop, and the effect of feedback loop is to make the average output voltage of integrating circuit approach the datum of comparer;
The result and the reference clock of comparer pass through analog switch, constitute a DAC, how decision feeds back: during comparer output " 0 ", one tunnel output positive electricity of analog switch is pressed onto integrating circuit, when comparer output " 1 ", analog switch output negative electricity is pressed onto integrating circuit; In like manner, when reference clock was " 0 ", another road output positive electricity of analog switch was pressed onto integrating circuit, and when reference clock was " 1 ", analog switch output negative electricity was pressed onto integrating circuit;
The output signal of comparer is with sampling rate output 1bit data stream, is loaded with digital filter and digital decimation device in the described FPGA/CPLD, extracts Useful Information from this data stream, and data rate is reduced to available level; Digital filter is asked on average the 1bit data stream, removes the outer quantizing noise of band; Use the high-frequency clock pulse pad count again, data pick-up is carried out in the output of digital filtering, obtain the sampled result digital value.
A kind of electric machine phase current pick-up unit of realizing said method comprises Hall current sensor, sampling resistor, integrating circuit, comparer and digitized processing circuit; Hall current sensor induction phase current, the secondary output of sensor connects integrating circuit by sampling resistor, the output of integrating circuit connects an input end of comparer, and another input end of comparer connects normal potential, and the output of comparer connects the input end of digitizing treatment circuit; The electric current of sensor secondary output converts the sampled voltage signal to through sampling resistor, this voltage signal enters comparer after the integrating circuit integral operation and normal potential compares, and the pulse width signal of comparer output is exported the sampled result digital value after the digitized processing processing of circuit.
Also be provided with divider resistance between described sampling resistor and integrating circuit, described sampled voltage signal imports integrating circuit again into after the divider resistance dividing potential drop.This device also comprises analog switch, and the output of described comparer connects the input end of analog switch, and analog switch output connects the input end of integrating circuit, constitutes feedback loop, makes the average output voltage of integrating circuit approach the datum of comparer.The normal potential of described comparer input is a zero potential.The frequency of described high-frequency clock pulse is 20～400MHz, uses 40MHz in this design.
Detect motor U phase current by Hall current sensor SC1, the secondary output current signal IU of sensor converts voltage signal to after detecting resistance R 1.Enter operational amplifier after this voltage signal process resistance R 2, the R3 dividing potential drop, form integrating circuit with capacitor C 1, integrating circuit is used for the error voltage summation is shown as a low-pass filter for input signal, then shows as high-pass filtering for quantizing noise.Like this, most of quantizing noise just is pushed to higher frequency range.Compare with simple over-sampling, total noise power does not change, but variation has taken place in the distribution of noise.And then enter comparer U2A and compare with zero potential, if input voltage rises, comparer must produce the high level " 1 " of greater number, vice versa.The output of comparer U2A feeds back to operational amplifier U1A through analog switch U3 (function class is 1 DAC seemingly) again, constitutes a feedback loop.The effect of feedback DAC is to make the average output voltage of integrating circuit approach the datum of comparer.Feedback circuit herein is an important link, result of comparer (not being that " 0 " is exactly " 1 ") and reference clock T3CMP (being sampling rate) are by analog switch U3, constitute a DAC, how decision feeds back: during comparer output " 0 ", the 15 pin Y output+2.5V of U3, by feedback resistance R5 feedback+2.5V to integrating circuit, when comparer output " 1 ", the 15 pin Y output-2.5V of U3, by feedback resistance R5 feedback-2.5V voltage to integrating circuit; In like manner, when reference clock T3CMP is " 0 ", the 14 pin X output+2.5V of U3, by feedback resistance R6 feedback+2.5V to integrating circuit, when reference clock T3CMP is " 1 ", the 14 pin X output-2.5V of U3, by feedback resistance R6 feedback-2.5V voltage to integrating circuit.
The output signal of comparer is with sampling rate output 1bit data stream.The purpose of carrying out digital filtering and extraction in CPLD/FPGA U4 extracts Useful Information exactly from this data stream, and data rate is reduced to available level.Digital filter is asked on average the 1bit data stream, removes the outer quantizing noise of band.At CPLD/FPGA data pick-up is carried out in the output of digital filtering then---the method with high-frequency clock pulse CLK (40MHz) pad count obtains the sampled result digital value.
As Fig. 2, high-frequency clock pulse CLK (40MHz) obtains the needed reference clock T3CMP of analogue unit (40KHz) through frequency divider, CLK produces a clear signal Clear and a latch signal Latch through an every 100us of logic maker (10KHz), the clear signal Clear digital decimation device that is used for resetting, latch signal Latch is latched into register with the result of digital decimation device, in order successfully to latch the result of digital decimation device, promptly must latch afterwards earlier and remove, clear signal Clear must lag behind clock period of latch signal Latch.U3D trigger and U6 reverser have been combined into a digital filter spare, and the data stream CT1 that comparer among Fig. 1 is exported carries out digital filtering; Data pick-up device U4 is exactly one 16 digit counter, under the triggering of high-frequency clock pulse CLK, to carrying out digitized processing---digital decimation through the CT1 signal behind the digital filtering, the result behind the digital decimation is latched into buffer register U5 through latch signal Latch.Processor can promptly get sampled result by the data among the bus sense buffer U5.
Learn according to experiment, when R2, R3, R4 equal 3.32k Ω, the voltage that B is ordered be A order 1/3.The dutycycle of comparer output square wave is directly proportional with the size of Hall current sensor secondary output current, and the voltage of order as B reaches+and during 700mV, comparer output CT1 just all is a height; And the voltage of ordering as B reaches-during 700mV, comparer output CT1 is low all just.
Experimental data such as following table:
| U phase current effective value (A) | 2.5 | 5.0 | 7.5 | 10.0 |
| U phase current peak value (A) | 3.535 | 7.07 | 10.625 | 14.14 |
| Hall element output current peak value (mA) | 7.07 | 14.14 | 21.21 | 28.28 |
| Actual measurement A point voltage (V) | 0.522 | 1.041 | 1.560 | 2.082 |
| Actual measurement B point voltage (V) | 0.174 | 0.347 | 0.520 | 0.694 |
| The data value MA-4000 of IU | 992 | 1978 | 2960 | 3948 |
U phase current peak value (A)=U phase current effective value (A) * 1.414
Hall element output current peak value (mA)=U phase current peak value (A) * 24 (mA)/12 (A)
Desirable A point voltage (mV)=Hall element output current peak value (mA) * 75 (Ω)
Desirable B point voltage (mV)=desirable A point voltage (mV)/3
Current detection circuit+CPLD/FPGA program equivalence is an A/D converter.The A/D converter higher than performance from cost is cheap, and the anti-interference that detects and stable better than A/D converter.
Claims (7)
1. electric machine phase current detection method comprises step: respond to phase current with Hall current sensor, the current signal of sensor secondary output converts voltage signal to; Again the gained voltage signal is carried out integration, and compare, obtain pulse width signal with normal potential; In FPGA/CPLD, the gained pulse width signal is carried out digitized processing then, obtain end value, it is characterized in that
Hall current sensor induction phase current converts voltage signal to through sampling resistor, enters operational amplifier and electric capacity composition integrating circuit after this voltage signal process divider resistance dividing potential drop; Integrating circuit is used for the error voltage summation is shown as a low-pass filter for input signal, then shows as high-pass filtering for quantizing noise; Like this, most of quantizing noise just is pushed to higher frequency range, and total noise power does not change, but variation has taken place in the distribution of noise;
Then, the integrating circuit output signal enters comparer and zero potential compares, if the input voltage of comparer rises, comparer can produce the high level " 1 " of greater number, and vice versa; The output of comparer feeds back to operational amplifier through analog switch again, constitutes a feedback loop, and the effect of feedback loop is to make the average output voltage of integrating circuit approach the datum of comparer;
The result and the reference clock of comparer pass through analog switch, constitute a DAC, how decision feeds back: during comparer output " 0 ", one tunnel output positive electricity of analog switch is pressed onto integrating circuit, when comparer output " 1 ", analog switch output negative electricity is pressed onto integrating circuit; In like manner, when reference clock was " 0 ", another road output positive electricity of analog switch was pressed onto integrating circuit, and when reference clock was " 1 ", analog switch output negative electricity was pressed onto integrating circuit;
The output signal of comparer is with sampling rate output 1bit data stream, is loaded with digital filter and digital decimation device in the described FPGA/CPLD, extracts Useful Information from this data stream, and data rate is reduced to available level; Digital filter is asked on average the 1bit data stream, removes the outer quantizing noise of band; Use the high-frequency clock pulse pad count again, data pick-up is carried out in the output of digital filtering, obtain the sampled result digital value.
2. an electric machine phase current pick-up unit of realizing the described method of claim 1 is characterized in that comprising Hall current sensor, sampling resistor, integrating circuit, comparer, digitized processing circuit and pulse generating circuit; Hall current sensor induction phase current, the secondary output of sensor connects integrating circuit by sampling resistor, the output of integrating circuit connects an input end of comparer, and another input end of comparer connects normal potential, and the output of comparer connects the input end of digitizing treatment circuit; The electric current of sensor secondary output converts the sampled voltage signal to through sampling resistor, and this voltage signal enters comparer after the integrating circuit integral operation and normal potential compares; The high-frequency clock pulse that the pulse width signal of comparer output and pulse generating circuit produce imports the digitized processing circuit into, and signal is exported the sampled result digital value after the digitized processing processing of circuit; CPLD/FPGA is the kernel carrier of described digitized processing circuit.
3. electric machine phase current pick-up unit according to claim 2 is characterized in that described digitized processing circuit comprises digital filter, logic maker, digital decimation device and register; High-frequency clock pulse CLK produces a clear signal Clear and a latch signal Latch through the logic maker, and clear signal Clear connects digital withdrawal device, and the digital decimation device is used for resetting; Latch signal Latch connects register, and the result of digital decimation device is latched into register; The input of the output linking number character filter of described comparer, the trigger end of wave filter connects high-frequency clock pulse CLK, and the output terminal of wave filter connects the input end of data withdrawal device; The trigger end of data pick-up device connects high-frequency clock pulse CLK; The extraction result of digital decimation device output is latched into register through latch signal Latch; Data in the impact damper are sampled result.
4. electric machine phase current pick-up unit according to claim 3 is characterized in that also being provided with divider resistance between described sampling resistor and integrating circuit, described sampled voltage signal imports integrating circuit again into after the divider resistance dividing potential drop.
5. electric machine phase current pick-up unit according to claim 4 is characterized in that this device also comprises analog switch, and the output of described comparer connects the input end of analog switch; Import the input end of analog switch behind the frequency divider frequency division of described high-frequency clock pulse CLK in CPLD/FPGA into; Analog switch output connects the input end of integrating circuit, constitutes feedback loop.
6. electric machine phase current pick-up unit according to claim 4 is characterized in that the normal potential of described comparer input is a zero potential.
7. electric machine phase current pick-up unit according to claim 5, the scope that it is characterized in that the frequency CLK of described high-frequency clock pulse is 20～400MHz.
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Effective date of registration: 20181211 Address after: 528225 B3 Workshop, No. 40 Boai Middle Road, Shishan Town, Nanhai District, Foshan City, Guangdong Province Patentee after: Eston (Guangdong) Robot Co., Ltd. Address before: 211100 No. 155 General Avenue, Jiangning Development Zone, Jiangning District, Nanjing City, Jiangsu Province Patentee before: Nanjing Estun Automatic Control Technology Co., Ltd. |