CN101221717A - Flat panel display and driving method thereof - Google Patents

Abstract

A flat panel display comprises a substrate, a plurality of data lines, a plurality of scanning lines, a source electrode driving unit and a grid electrode driving unit. The substrate includes a pixel array. The data lines are electrically connected to the pixel array. The plurality of scanning lines comprise p groups of scanning lines which are electrically connected to the pixel array, and p is a positive integer. At least some of the scan lines in the same group of scan lines are not adjacent. The source driving unit is electrically connected to the data lines. The gate driving unit includes p shift register circuits for enabling the p groups of scan lines, respectively. In a first frame period, the p groups of scan lines are enabled in a first group order, and in a second frame period, the p groups of scan lines are enabled in a second group order, the first group order being different from the second group order.

Description

Flat panel display and driving method thereof

【Technical field】

The present invention relates to a flat-panel display and a driving method thereof, in particular to a flat-panel display capable of improving image quality and a driving method thereof.

【Background technique】

Nowadays, the technology of flat panel displays develops rapidly, and various technologies are continuously developed. In order to reduce the number of integrated circuit (Integrated Circuit, IC) signal lines to save costs, some non-traditional panel charging circuit architectures have emerged in the technical field of the present invention. However, in these panel charging architectures, since the circuit layout of each pixel is different from the traditional circuit layout, various traces (mura) will be generated on the picture, thereby affecting the image quality of the picture.

Figure 1 is a schematic diagram of a conventional liquid crystal display. As shown in FIG. 1, the liquid crystal display 100 includes a substrate (not shown in the figure), a plurality of data lines S1-Sm, a plurality of scan lines G1-G2n, a source driving unit 110 and a gate driving unit 120, m and n is a positive integer. The substrate (not shown in the figure) includes a pixel array, and the pixel array includes a plurality of pixels P(x, y), where x and y are positive integers. Each pixel P(x,y) includes a transistor T.

The first row of pixels in the pixel array is taken as an example for illustration. First, the scan line G1 is enabled, and the pixels P(1, 1), P(3, 1), P(5, 1), ..., P(2m-1, 1) are charged; then, the scan line G2 is activated When enabled, pixels P(2,1), P(4,1), P(6,1), . . . , P(2m,1) are charged. At this time, due to the existence of the capacitive coupling effect, the pixels P(1, 1), P(3, 1), P(5, 1), ..., P(2m-1, 1) are affected by the capacitive coupling effect and Change its pixel voltage. In this way, the charging coupling degree of the odd-numbered pixels and the even-numbered pixels are inconsistent, resulting in traces in the vertical direction of the image due to uneven brightness.

【Content of invention】

The invention relates to a flat-panel display and its driving method. A plurality of scanning lines of the flat-panel display are divided into different groups, and then in different frame periods, a plurality of shift register circuits are used to achieve different The order of the groups respectively enables the scan lines corresponding to the groups, so as to reduce the trace phenomenon of the image frame.

According to a technical aspect of the present invention, a flat panel display is provided, including a substrate, a plurality of data lines, a plurality of scan lines, a source driving unit, and a gate driving unit. The substrate includes a pixel array. Multiple data lines are electrically connected to the pixel array. A plurality of scan lines are electrically connected to the pixel array, and the scan lines include a plurality of odd scan lines and a plurality of even scan lines. The source driving unit is electrically connected to the data line. The gate drive unit includes a first shift register circuit and a second shift register circuit, the first shift register circuit is used to sequentially enable an odd number of scan lines, and the second shift register circuit It is used to enable even scan lines in sequence. In the first frame period, the odd scan lines are sequentially enabled before the even scan lines, and the odd scan lines and the even scan lines are enabled alternately. In the second frame period, the even scan lines are sequentially enabled before the odd scan lines, and the odd scan lines and the even scan lines are enabled alternately.

According to another technical aspect of the present invention, a flat panel display driving method is proposed. The flat panel display includes a substrate, a plurality of data lines, a plurality of scan lines, a source driving unit and a gate driving unit. The substrate includes a pixel array. A plurality of data lines and a plurality of scan lines are electrically connected to the pixel array, and the scan lines include a plurality of odd-numbered scan lines and a plurality of even-numbered scan lines. The source driving unit is electrically connected to the data lines. The gate drive unit includes a first shift register circuit and a second shift register circuit, the first shift register circuit is used to sequentially enable an odd number of scan lines, and the second shift register circuit It is used to enable even scan lines in sequence. The flat panel display driving method includes: firstly, in the first frame period, enabling the odd-numbered scanning lines and the even-numbered scanning lines alternately, wherein the odd-numbered scanning lines are sequentially enabled before the even-numbered scanning lines; In two frame periods, the odd-numbered scanning lines and the even-numbered scanning lines are enabled alternately, wherein the even-numbered scanning lines are sequentially enabled before the odd-numbered scanning lines.

According to yet another technical aspect of the present invention, a flat panel display is provided, including a substrate, a plurality of data lines, a plurality of scan lines, a source driving unit, and a gate driving unit. The substrate includes a pixel array. Multiple data lines are electrically connected to the pixel array. A plurality of scan lines, including p groups of scan lines, are electrically connected to the pixel array, and p is a positive integer. Within the same group of scan lines, at least some of the scan lines are not adjacent. The source driving unit is electrically connected to the data lines. The gate driving unit includes p shift register circuits for respectively enabling p groups of scan lines. In the first frame period, the scan lines of the p group are enabled in the order of the first group, and in the second frame period, the scan lines of the p group are enabled in the order of the second group, and the order of the first group is different in the second group order.

According to yet another technical aspect of the present invention, a flat panel display driving method is proposed. The flat panel display includes a substrate, a plurality of data lines, a plurality of scan lines, a source driving unit and a gate driving unit. The substrate includes a pixel array. A plurality of data lines and a plurality of scanning lines are electrically connected to the pixel array, and the scanning lines include p groups of scanning lines. Within the same group of scanning lines, at least some of the scanning lines are not adjacent, and p is a positive integer. The source driving unit is electrically connected to the data lines. The gate driving unit includes p shift register circuits for respectively enabling p groups of scan lines. The driving method of the flat panel display includes: firstly enabling the scanning lines of the p group in the order of the first group in the first frame period; and then enabling the scanning lines of the p group in the order of the second group in the second frame period , the second group order is different from the first group order.

According to another technical aspect of the present invention, a flat panel display is provided, including a substrate, a plurality of data lines, a plurality of scan lines, a source driving unit, and a gate driving unit. The substrate includes a pixel array. Multiple data lines are electrically connected to the pixel array. A plurality of scan lines are electrically connected to the pixel array, and the scan lines include a plurality of odd scan lines and a plurality of even scan lines. The source driving unit is electrically connected to the data lines. The gate driving unit includes a first shift register circuit and a second shift register circuit. The first shift register circuit is used to sequentially enable odd-numbered scan lines according to the first start signal, the first clock signal and the first delayed clock signal, and the second shift register circuit is used to enable the odd-numbered scan lines according to the second start signal, the second clock signal and the second delayed clock signal sequentially enable even scan lines. During the first frame period, the phases of the first start signal, the first clock signal and the first delayed clock signal are respectively ahead of the phases of the second start signal, the second clock signal and the second delayed clock signal. In the second frame period, phases of the second start signal, the second clock signal and the second delayed clock signal are respectively ahead of those of the first start signal, the first clock signal and the first delayed clock signal.

In order to make the above content of the present invention more obvious and understandable, the following preferred embodiments are specifically cited below, and in conjunction with the accompanying drawings, the detailed description is as follows:

【Description of drawings】

Figure 1 is a schematic diagram of a conventional liquid crystal display.

FIG. 2A is a schematic diagram of the first embodiment of the liquid crystal display of the present invention.

FIG. 2B is a waveform diagram of signals driving a shift register according to the first embodiment of the liquid crystal display of the present invention.

FIG. 2C is a waveform diagram of signals driving scanning lines according to the first embodiment of the liquid crystal display of the present invention.

2D is another signal waveform diagram for driving the shift register according to the first embodiment of the liquid crystal display of the present invention.

2E is another signal waveform diagram for driving scan lines according to the first embodiment of the liquid crystal display of the present invention.

FIG. 3 is a flow chart of the driving method of the first embodiment of the flat panel display of the present invention.

FIG. 4A is a schematic diagram of a second embodiment of the liquid crystal display of the present invention.

FIG. 4B is a waveform diagram of signals driving a shift register according to the second embodiment of the liquid crystal display of the present invention.

FIG. 4C is a waveform diagram of signals driving scanning lines according to the second embodiment of the liquid crystal display of the present invention.

4D is another signal waveform diagram for driving the shift register according to the second embodiment of the liquid crystal display of the present invention.

FIG. 4E is another signal waveform diagram for driving scan lines according to the second embodiment of the liquid crystal display of the present invention.

FIG. 5 is a flow chart of the driving method of the second embodiment of the flat panel display of the present invention.

【Detailed ways】

The present invention provides a flat-panel display and its driving method. Multiple scanning lines of the flat-panel display are divided into different groups, and then in different frame periods, multiple shift register circuits in the gate drive unit are used , enabling the scan lines of the corresponding groups sequentially in a plurality of different group sequences. The flat panel display in each embodiment of the present invention is described by taking a liquid crystal display as an example, but it is not limited thereto, and other types of displays are also applicable.

first embodiment

FIG. 2A is a schematic diagram of the first embodiment of the liquid crystal display of the present invention. As shown in FIG. 2A, the liquid crystal display 200 includes a substrate (not shown in the figure), a plurality of data lines S1-Sm, a plurality of scan lines G1-G2n, a source driving unit 210 and a gate driving unit 220, m and n is a positive integer. The substrate is, for example, a glass substrate, which includes the pixel array 230 . The pixel array 230 includes a plurality of pixels P(x, y), x and y are positive integers, and each pixel includes a transistor T. In the flat panel display 200 , each data line S1 -Sm is electrically connected to two transistors of two adjacent pixels in each row of pixels, for example.

A plurality of data lines S1˜Sm are electrically connected to the pixel array 230 . A plurality of scanning lines G1-G2n are electrically connected to the pixel array 230, and these scanning lines G1-G2n include a plurality of odd-numbered scanning lines G1, G3, G5, . . . , G2n-1 and a plurality of even-numbered scanning lines G2, G4, G6, ..., G2n. The source driving unit 210 is electrically connected to the data lines S1˜Sm.

The gate driving unit 220 can be disposed on the substrate, or directly formed on the substrate. The gate driving unit 220 includes a first shift register circuit 222 and a second shift register circuit 224. The first shift register circuit 222 is used to operate according to the first start signal ST1 and the first clock signal CK1. and the first delayed clock signal XCK1 sequentially enable the odd scan lines G1 , G3 , G5 , . The second shift register circuit 224 is used to sequentially enable the even-numbered scanning lines G2, G4, G6, . . . The phase of the second delayed clock signal XCK2 is delayed by 180 degrees compared to the phase of the second clock signal CK2 .

FIG. 2B is a waveform diagram of signals driving a shift register according to the first embodiment of the liquid crystal display of the present invention. It can be seen from FIG. 2B that by changing the timings of the multiple control signals ST1/CK1/XCK1 and ST2/CK2/XCK2, the purpose of sequentially enabling the corresponding groups of scan lines in different group orders can be achieved. For example, in FIG. 2B, in the first frame period, the phases of the control signals ST1/CK1/XCK1 are respectively ahead of the phases of the control signals ST2/CK2/XCK2; in the second frame period, the control signals ST2/CK2/XCK2 The phases of are respectively ahead of the phases of the control signals ST1/CK1/XCK1. In this way, multiple shift register circuits can use the same circuit, which simplifies the structure of the gate driving unit and reduces the cost.

FIG. 2C is a waveform diagram of signals driving scanning lines according to the first embodiment of the liquid crystal display of the present invention. As shown in FIG. 2C, in the first frame period, the odd scanning lines G1, G3, G5, . . . , G2n-1 and the even scanning lines G2, G4, G6, . That is, the scan line G1 , the scan line G2 , the scan line G3 , the scan line G4 , . . . , the scan line G2n−1 and the scan line G2n are enabled in sequence.

In the second frame period, the scan line G2 , the scan line G1 , the scan line G4 , the scan line G3 , . . . , the scan line G2n and the scan line G2n−1 are enabled in sequence. Since the odd scanning lines G1, G3, G5, ..., G2n-1 and the even scanning lines G2, G4, G6, ..., G2n are enabled in different group sequences in different frame periods, each pixel The charge coupling degree tends to be consistent, and the overall brightness becomes more uniform, which can reduce the trace (mura) phenomenon of the image screen.

The first row of pixels of the pixel array 230 is taken as an example for illustration. In the first frame period, when the scan line G1 is enabled, the pixels P(1,1), P(3,1), P(5,1), . . . , P(2m-1,1) are charged, At this time, the pixel voltages of the pixels P(2,1), P(4,1), P(6,1), . . . , P(2m,1) change due to the capacitive coupling effect. Next, the scanning line G2 is enabled, the pixels P(2,1), P(4,1), P(6,1), ..., P(2m,1) are charged, and the pixels P(2,1), The pixel voltages of P(4,1), P(6,1), . However, when the scan line G2 is enabled, the received pixel voltages of pixels P(1,1), P(3,1), P(5,1), . . . , P(2m-1,1) Will change due to capacitive coupling effect and maintain for one frame period.

In the second frame period, when the scan line G2 is enabled, the pixels P(2,1), P(4,1), P(6,1), ..., P(2m,1) are charged, so that the pixels The pixel voltages of P(1,1), P(3,1), P(5,1), . Next, the scan line G1 is enabled, the pixels P(1,1), P(3,1), P(5,1), ..., P(2m-1,1) are charged, and the pixels P(1,1 ), P(3,1), P(5,1), . However, when the scan line G1 is enabled, the pixel voltages of pixels P(2,1), P(4,1), P(6,1), . . . The effect changes, and maintains a frame cycle.

It can be deduced from the above that the pixels P(1, 1), P(3, 1), P(5, 1), ..., P(2m-1, 1) in the odd-numbered rows are affected by the capacitive coupling effect in the first frame period , while the even-numbered pixels P(2,1), P(4,1), P(6,1), . . . , P(2m,1) are affected by the capacitive coupling effect during the second frame period. Therefore, after the first frame period and the second frame period, the first row of pixels P(1,1)~P(2m,1) will be affected by the charging coupling effect, and the degree of influence is roughly the same . Similarly, the other columns of pixels are affected by the capacitive coupling effect similarly to the first column of pixels. Therefore, when the user watches, he will not perceive the trace phenomenon caused by the difference in the capacitive coupling effect between different rows and the difference in brightness.

In the conventional liquid crystal display 100, when the scan line G1 is enabled, the pixel voltages of the pixels P(2,1), P(4,1), P(6,1), . . . , P(2m,1) are due to affected by capacitive coupling effects. When the scan line G2 is enabled, the pixel voltages of pixels P(2,1), P(4,1), P(6,1), ..., P(2m,1) are updated to eliminate the capacitive coupling effect , but the pixel voltages of pixels P(1, 1), P(3, 1), P(5, 1), ..., P(2m-1, 1) are changed due to the capacitive coupling effect, and Maintain a frame period. In the traditional liquid crystal display 100, the pixel voltages affected by the capacitive coupling effect of only odd-numbered pixels will maintain the entire frame period, so only the odd-numbered pixels will have color shifting, resulting in the vertical direction of the liquid crystal display 100. There are traces. However, in this embodiment, since the pixels in each row of the liquid crystal display 200 are substantially uniformly affected by the charging coupling effect, there will be no traces in the vertical direction.

In addition, in addition to changing the enabling sequence of the odd-numbered scanning lines and the even-numbered scanning lines every adjacent frame period, the enabling order of the odd-numbered scanning lines and the even-numbered scanning lines can also be changed every two adjacent frame periods. enabling order, but is not limited to this.

2D is another signal waveform diagram for driving the shift register according to the first embodiment of the liquid crystal display of the present invention. The waveforms of the control signals ST1/CK1/XCK1 and ST2/CK2/XCK2 are substantially the same as those in FIG. 2B, but only change once every two frame periods.

2E is another signal waveform diagram for driving scan lines according to the first embodiment of the liquid crystal display of the present invention. The first frame period, the second frame period, the third frame period and the fourth frame period are arranged adjacently in sequence. In the first frame period, the scan line G1 , the scan line G2 , the scan line G3 , the scan line G4 , . . . , the scan line G2n−1 and the scan line G2n are enabled in sequence. Then, in the second frame period and the third frame period, the scan line G2 , the scan line G1 , the scan line G4 , the scan line G3 , . . . , the scan line G2n and the scan line G2n-1 are sequentially enabled. After that, in the fourth frame period, the scan line G1 , the scan line G2 , the scan line G3 , the scan line G4 , . . . , the scan line G2n−1 and the scan line G2n are enabled in sequence.

In addition, as shown in FIG. 2A , the liquid crystal display 200 utilizes the start signal (start pulse), the clock signal (clock pulse) and the delayed clock signal received by the control gate driving unit 220 to achieve multiple different groups. The purpose of sequentially enabling the scan lines of the corresponding group is respectively, but other methods can also be used, and the present invention is not limited thereto.

The invention also discloses a method for driving a flat panel display. The flat panel display includes a substrate, a plurality of data lines, a plurality of scanning lines, a source driving unit and a gate driving unit. The substrate is, for example, a glass substrate, including a pixel array. The pixel array includes a plurality of pixels, each pixel includes a transistor, and each data line is electrically connected to two transistors of two adjacent pixels in each row of pixels.

The data lines and the scan lines are electrically connected to the pixel array. The scan lines include a plurality of odd scan lines and a plurality of even scan lines. The source driving unit is electrically connected to the data line. The gate drive unit can be configured on the substrate or directly formed on the substrate. The gate drive unit includes a first shift register circuit and a second shift register circuit, and the first shift register circuit is used for To sequentially enable the odd scan lines, the second shift register circuit is used to sequentially enable the even scan lines.

FIG. 3 is a flow chart of the driving method of the first embodiment of the flat panel display of the present invention. First, in step 300, a plurality of odd-numbered scan lines and a plurality of even-numbered scan lines are enabled alternately within the first frame period, wherein the odd-numbered scan lines are enabled sequentially before the even-numbered scan lines . Afterwards, in step 310, within the second frame period, a plurality of odd-numbered scan lines and a plurality of even-numbered scan lines are enabled alternately, wherein the even-numbered scan lines are sequentially enabled prior to the odd-numbered scan lines .

Regarding the driving method of the flat panel display, its operating principle has been described in detail in the description of the liquid crystal display 200 , so it will not be repeated here.

second embodiment

FIG. 4A is a schematic diagram of a second embodiment of the liquid crystal display of the present invention. The liquid crystal display 400 includes a substrate (not shown in the figure), a plurality of data lines S1˜Sm, a plurality of scan lines G1˜G2n, a source driving unit 410 and a gate driving unit 420, where m and n are positive integers. The substrate is, for example, a glass substrate, which includes a pixel array 430 . The pixel array 430 includes a plurality of pixels, and each pixel includes a transistor (not shown in the figure). In the liquid crystal display 400 , each data line S1 ˜Sm is electrically connected to p transistors of each column of pixels, and p is a positive integer.

A plurality of data lines S1˜Sm are electrically connected to the pixel array 430 . A plurality of scan lines G1-G2n are electrically connected to the pixel array 430, and these scan lines G1-G2n include p groups of scan lines, wherein at least some of the scan lines are not adjacent. The source driving unit 410 is electrically connected to the data lines S1˜Sm. The gate driving unit 420 includes a first shift register circuit 421 to a p-th shift register circuit 42p, which are respectively used to enable p groups of scan lines.

During the first frame period, p groups of scan lines are enabled in the first group order. Then, in the second frame period following the first frame period, the p groups of scan lines are enabled in a second group order, and the first group order is different from the second group order. Or, in the third frame period after the second frame period, the scan lines of p groups are enabled in the order of the third group, and the order of the third group is different from the order of the first group and the second group order. In addition, it is also possible to change the order of the groups in which the p groups of scan lines are enabled sequentially every multiple adjacent frame periods.

Next, take p equal to 3 as an example to illustrate. Please refer to FIG. 4B and FIG. 4C. FIG. 4B is a signal waveform diagram for driving the shift register according to the second embodiment of the liquid crystal display of the present invention, and FIG. 4C is a diagram for driving the scanning lines according to the second embodiment of the liquid crystal display of the present invention. signal waveform diagram. In the first frame period, the three shift register circuits enable three groups of scan lines in the order of the first group, the second group and the third group. Then, in the second frame period following the first frame period, the three shift register circuits enable three groups of scan lines in the order of the second group, the third group and the first group. In the third frame period following the second frame period, the three shift register circuits enable three groups of scan lines in the order of the third group, the first group and the second group. Although this embodiment takes p=3 as an example, the present invention is not limited thereto, and p can also be other positive integers; in addition, the order in which the scanning lines are enabled within a frame period can also be changed arbitrarily, not only It is limited to the order listed in the above-mentioned embodiments.

In addition, the enabling sequence of different groups of scanning lines can also be changed every two adjacent frame periods. Please refer to FIG. 4D and FIG. 4E. FIG. FIG. 4E shows another signal waveform diagram for driving scanning lines according to the second embodiment of the liquid crystal display of the present invention. In the adjacent first frame period and the second frame period, the three shift register circuits enable three groups of scan lines in the order of the first group, the second group and the third group. Then, in the adjacent third frame period and the fourth frame period after the second frame period, the three shift register circuits are aligned in the order of the second group, the third group and the first group Can scan three groups of lines. In the fifth frame period and the sixth frame period adjacent to the fourth frame period, the three shift register circuits enable the three shift register circuits in the order of the third group, the first group and the second group. Group scan lines.

The detailed operation principle of the liquid crystal display 400 is similar to that of the liquid crystal display 200 , so it will not be repeated here.

The invention also discloses another method for driving a flat panel display. The flat panel display includes a substrate, a plurality of data lines, a plurality of scanning lines, a source driving unit and a gate driving unit. The substrate includes a pixel array. Multiple data lines and multiple scan lines are electrically connected to the pixel array. These scan lines include p groups of scan lines, in the same group of scan lines, at least some of the scan lines are not adjacent, and p is a positive integer. The source driving unit is electrically connected to the data lines. The gate driving unit includes p shift register circuits for respectively enabling p groups of scan lines.

FIG. 5 is a flow chart of the driving method of the second embodiment of the flat panel display of the present invention. First, in step 500, within a first frame period, p groups of scan lines are enabled in a first group order. Afterwards, in step 520 , within the second frame period, the p groups of scan lines are enabled in a second group order, the second group order being different from the first group order.

The operating principle of the above flat panel display driving method has been described in the description of the liquid crystal display 400 , so it will not be repeated here.

In addition, the enabling times of the pulses of the control signals ST1/CK1/XCK1 and ST2/CK2/XCK2 can also overlap, so that the pulses of the scanning signals of adjacent scanning lines partially overlap. In this way, the pixels in the pixel array will have a pre-charge time, so that each pixel can quickly display the desired brightness, so that the liquid crystal display 200 or 400 can have higher brightness.

The flat-panel display and its driving method disclosed in the above-mentioned embodiments of the present invention are essentially based on the charging circuit structure of the pixel array of the flat-panel display, divide the scanning lines of the flat-panel display into different groups, and divide the scanning lines in the gate drive unit into different groups. Configure multiple shift register circuits. In this way, within different frame periods, multiple shift register circuits in the gate drive unit can be used to sequentially enable corresponding groups of scan lines in different group sequences. , so that the charging coupling degree of each pixel tends to be consistent, and each pixel is affected by the capacitive coupling effect more evenly than the traditional method, so as to effectively reduce the trace phenomenon of the image screen.

In addition, multiple shift register circuits can also use the same circuit, and the above effect can be achieved by changing the timing of the clock signal and the start signal controlling the multiple shift register circuits. Therefore, the present invention has the advantages of simple circuit hardware design, simple control signals, and effective cost reduction.

To sum up, although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the present invention may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the scope of the appended patent application.

Claims (20)

1. flat-panel screens comprises:

One substrate comprises a pixel array;

Many data lines are electrically connected to this pixel array;

A plurality of sweep traces are electrically connected to this pixel array, and described sweep trace comprises a plurality of odd number bar sweep traces and a plurality of even number bar sweep trace;

The one source pole driver element is electrically connected to described data line; And

One drive element of the grid, comprise one first shift registor circuit and one second shift registor circuit, this first shift registor circuit is in order to the described odd number bar of activation in regular turn sweep trace, and this second shift registor circuit is in order to the described even number bar of activation in regular turn sweep trace;

Wherein, in the cycle, described odd number bar sweep trace is enabled in regular turn prior to described even number bar sweep trace in one first picture frame, and described odd number bar sweep trace and described even number bar sweep trace are enabled alternately;

Wherein, in the cycle, described even number bar sweep trace is enabled in regular turn prior to described odd number bar sweep trace in one second picture frame, and described odd number bar sweep trace and described even number bar sweep trace are enabled alternately.

2. flat-panel screens according to claim 1, it is characterized in that, described sweep trace comprise this article one sweep trace, this second sweep trace ..., this 2n bar sweep trace, in this first picture frame cycle, this article one sweep trace, this second sweep trace ..., this 2n-1 bar sweep trace and this 2n bar sweep trace be enabled in regular turn, and in this second picture frame cycle, this second sweep trace, this article one sweep trace ... the 2nd n bar sweep trace, this 2n-1 bar sweep trace are enabled in regular turn.

3. flat-panel screens according to claim 1, it is characterized in that, in one the 3rd picture frame in the cycle, this even number bar sweep trace is enabled in regular turn prior to this odd number bar sweep trace, and described odd number bar sweep trace and described even number bar sweep trace are enabled alternately, and in one the 4th picture frame in the cycle, this odd number bar sweep trace is enabled in regular turn prior to this even number bar sweep trace, and described odd number bar sweep trace and described even number bar sweep trace are enabled alternately, this first, this second, the 3rd, and adjacent in regular turn arrangement of the 4th picture frame cycle.

4. flat-panel screens according to claim 1 is characterized in that this pixel array comprises a plurality of picture elements, and each picture element comprises a transistor, and two transistors of adjacent two picture elements of each bar data line and each row picture element electrically connect.

5. planar display driving method, this flat-panel screens comprises a substrate, many data lines, a plurality of sweep traces, an one source pole driver element and a drive element of the grid, this substrate comprises a pixel array, described data line and described sweep trace are electrically connected to this pixel array, described sweep trace comprises a plurality of odd number bar sweep traces and a plurality of even number bar sweep trace, this source drive unit is electrically connected to described data line, this drive element of the grid comprises one first shift registor circuit and one second shift registor circuit, this first shift registor circuit is in order to the described odd number bar of activation in regular turn sweep trace, this second shift registor circuit is in order to the described even number bar of activation in regular turn sweep trace, and this planar display driving method comprises:

In one first picture frame in the cycle, described odd number bar sweep trace of activation alternately and described even number bar sweep trace, wherein said odd number bar sweep trace is enabled in regular turn prior to described even number bar sweep trace; And

In one second picture frame in the cycle, described odd number bar sweep trace of activation alternately and described even number bar sweep trace, wherein said even number bar sweep trace is enabled in regular turn prior to described odd number bar sweep trace.

6. planar display driving method according to claim 5, it is characterized in that, described sweep trace comprise this article one sweep trace, this second sweep trace ..., this 2n bar sweep trace, in this first picture frame cycle, this article one sweep trace of activation in regular turn, this second sweep trace ..., this 2n-1 bar sweep trace and this 2n bar sweep trace, and in this second picture frame cycle, this second sweep trace of activation in regular turn, this article one sweep trace ... this 2n bar sweep trace and this 2n-1 bar sweep trace.

7. planar display driving method according to claim 5 is characterized in that other comprises:

In one the 3rd picture frame in the cycle, described odd number bar sweep trace of activation alternately and described even number bar sweep trace, wherein said even number bar sweep trace is enabled in regular turn prior to described odd number bar sweep trace; And

In one the 4th picture frame cycle, described odd number bar sweep trace of activation alternately and described even number bar sweep trace, wherein said odd number bar sweep trace is enabled in regular turn prior to described even number bar sweep trace;

Wherein, this first, this second, the 3rd, and the 4th picture frame cycle arrange in regular turn.

8. planar display driving method according to claim 5 is characterized in that this pixel array comprises a plurality of picture elements, and each picture element comprises a transistor, and two transistors of adjacent two picture elements of each bar data line and each row picture element electrically connect.

9. flat-panel screens comprises:

One substrate comprises a pixel array;

Many data lines are electrically connected to this pixel array;

A plurality of sweep traces comprise p group scan line, are electrically connected to this pixel array, and are non-conterminous to the sweep trace of small part in the same group scan line, and p is a positive integer;

The one source pole driver element is electrically connected to described data line; And

One drive element of the grid comprises p shift registor circuit, respectively in order to this p group scan line of activation;

Wherein, in the cycle, this p group scan line is enabled in proper order with first group in one first picture frame, and in the cycle, this p group scan line is enabled in proper order with one second group in one second picture frame, and this first group is different from this second group order in proper order.

10. flat-panel screens according to claim 9 is characterized in that, this first picture frame cycle and this second picture frame cycle arrange in regular turn.

11. flat-panel screens according to claim 9 is characterized in that, in every adjacent two picture frame cycles, the order that this p group scan line is enabled does not change.

12. flat-panel screens according to claim 9 is characterized in that, this pixel array comprises a plurality of picture elements, and each picture element comprises a transistor, and p transistor of each bar data line and each row picture element electrically connects.

13. planar display driving method, this flat-panel screens comprises a substrate, many data lines, a plurality of sweep traces, an one source pole driver element and a drive element of the grid, this substrate comprises a pixel array, described data line and described sweep trace are electrically connected to this pixel array, described sweep trace comprises p group scan line, in the same group scan line, sweep trace to small part is non-conterminous, p is a positive integer, this source drive unit is electrically connected to described data line, this drive element of the grid comprises p shift registor circuit, and in order to this p group scan line of activation, this planar display driving method comprises respectively:

In one first picture frame in the cycle, with first group this p group scan line of order activation; And

In cycle, with one second group this p group scan line of order activation, this second group is different from this first group order in proper order in one second picture frame.

14. planar display driving method according to claim 13 is characterized in that, this first picture frame cycle and this second picture frame cycle arrange in regular turn.

15. planar display driving method according to claim 13 is characterized in that, in every adjacent two picture frame cycles, the order that this p group scan line is enabled does not change.

16. planar display driving method according to claim 13 is characterized in that, this pixel array comprises a plurality of picture elements, and each picture element comprises a transistor, and p transistor of each bar data line and each row picture element electrically connects.

17. planar display driving method according to claim 13 is characterized in that, other comprises:

In cycle, with one the 3rd group this p group scan line of order activation, the 3rd group is different from this first group order and this second group order in proper order in one the 3rd picture frame.

18. a flat-panel screens comprises:

One substrate comprises a pixel array;

Many data lines are electrically connected to this pixel array;

A plurality of sweep traces are electrically connected to this pixel array, and described sweep trace comprises a plurality of odd number bar sweep traces and a plurality of even number bar sweep trace;

The one source pole driver element is electrically connected to described data line; And

One drive element of the grid, comprise one first shift registor circuit and one second shift registor circuit, this first shift registor circuit is in order to foundation one first start signal, one first clock signal and the described odd number bar of one first delay clock signals activation in regular turn sweep trace, and this second shift registor circuit is in order to foundation one second start signal, a second clock signal and the described even number bar of one second delay clock signals activation in regular turn sweep trace;

Wherein, in the cycle, the phase place of this first start signal, this first clock signal and this first delay clock signals is led over the phase place of this second start signal, this second clock signal and this second delay clock signals respectively in one first picture frame;

Wherein, in the cycle, the phase place of this second start signal, this second clock signal and this second delay clock signals is led over the phase place of this first start signal, this first clock signal and this first delay clock signals respectively in one second picture frame.

19. flat-panel screens according to claim 18 is characterized in that, the phase place of this first delay clock signals is than phase delay 180 degree of this first clock signal, and the phase place of this second delay clock signals is than phase delay 180 degree of this second clock signal.

20. flat-panel screens according to claim 18 is characterized in that, this first shift registor circuit and this second shift registor circuit have identical circuit.

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