CN101221716A - Data driver using gamma selection signal, flat panel display and driving method thereof - Google Patents

Abstract

The invention relates to a data driver using gamma selection signals, a flat panel display and a driving method. The first to fourth data lines are respectively and electrically connected to the first left sub-pixel, the first right sub-pixel, the second right sub-pixel and the second left sub-pixel. The data driver includes first to fourth gray scale voltage generating units for respectively outputting a first group of positive gray scale voltages, a second group of negative gray scale voltages, a second group of positive gray scale voltages and a first group of negative gray scale voltages. The data driver drives the sub-pixels according to the first group of positive gray scale voltages, the second group of negative gray scale voltages, the second group of positive gray scale voltages and the first group of negative gray scale voltages under the control of a polarity inversion signal and a gamma selection signal.

Description

Data driver using gamma selection signal, flat panel display and driving method

technical field

The present invention relates to a data driver, a flat display panel and a driving method, in particular to a data driver using a gamma selection signal and a flat display panel using the data driver and a driving method.

Background technique

Due to the advantages of thin, light, small, low radiation, and space-saving, flat-panel displays have gradually become the mainstream of the display market in recent years. Increasing the viewing angle is one of the main factors affecting the image quality of a flat panel display.

For liquid crystal displays, the traditional driving method is to allow a pixel to receive two different pixel voltages sequentially within one frame time, so that the liquid crystal molecules are arranged in different directions, so as to increase the viewing angle of the liquid crystal display. One of the ways to achieve the above effect is: within one frame time, the timing controller sequentially transmits two pieces of data corresponding to the same pixel to the data driver, so that the data driver generates two different pixel voltages corresponding to this pixel , to increase the viewing angle of the LCD display.

However, compared with the liquid crystal display in which the timing controller transmits a piece of data corresponding to one pixel to the data driver within one frame time, the timing controller and the clock signal of the data driver used in the above-mentioned liquid crystal display for improving the viewing angle The frequency must be doubled to complete the transmission or reception of the data to be transmitted. In this way, the complexity of the circuit design of the timing controller and the data driver will be increased, and the required cost will be increased.

Contents of the invention

In view of this, the object of the present invention is to provide a data driver using a gamma selection signal, a flat panel display and a driving method using the data driver. The present invention can achieve the effect of improving the viewing angle without increasing the clock signal frequency of the timing controller and the data driver. At the same time, the present invention has excellent flexibility and can be applied to flat-panel displays with various driving methods.

According to the purpose of the present invention, a data driver is proposed, including: first, second, third and fourth grayscale voltage generation units; first, second, third and fourth digital-to-analog converters; and first , Second, third and fourth buffers. The first to fourth grayscale voltage generating units are used to respectively output the first group of positive grayscale voltages, the second group of negative grayscale voltages, the second group of positive grayscale voltages and the first group of negative grayscale voltages. When a gamma selection signal has a first state, the input terminals of the first, second, third and fourth digital-to-analog converters are respectively electrically connected to the first, second, third and fourth grayscale voltage generation output of the unit. When the gamma selection signal has the second state, the input terminals of the first, second, third and fourth digital-to-analog converters are electrically connected to the third, fourth, first and second grayscale voltage generation units respectively output terminal. When a polarity inversion signal is in the third state, the input ends of the first to the fourth buffers are respectively electrically connected to the output ends of the first to the fourth digital-to-analog converters. When the polarity inversion signal is in the fourth state, the input terminals of the first to fourth buffers are respectively electrically connected to the output terminals of the second, first, fourth and third digital-to-analog converters.

According to another object of the present invention, a flat panel display is provided, including a flat display panel, a timing controller, and a data driver. The plane display panel includes: first pixels and second pixels; first scanning lines; and first, second, third and fourth data lines. The first pixel includes a first left sub-pixel and a first right sub-pixel, and the second pixel includes a second left sub-pixel and a second right sub-pixel. The first scan line is used to control the first and second pixels. The first, second, third and fourth data lines are electrically connected to the first left sub-pixel, the first right sub-pixel, the second right sub-pixel and the second left sub-pixel respectively. The timing controller is used to output a polarity inversion signal and a gamma selection signal. The data driver includes first, second, third and fourth gray-scale voltage generating units, which are used to respectively output the first group of positive gray-scale voltages, the second group of negative gray-scale voltages, the second group of positive gray-scale voltages and the first group of gray-scale voltages. A set of negative grayscale voltages. The data driver is under the control of the polarity inversion signal and the gamma selection signal, according to the first group of positive gray-scale voltages, the second group of negative gray-scale voltages, the second group of positive gray-scale voltages and the first group of negative gray-scale voltages to drive these sub-pixels.

The present invention also provides a driving method of a flat display panel, the flat display panel has a first and a second pixel, and a first, a second, a third and a fourth data line, the first pixel includes a The first left sub-pixel and a first right sub-pixel, the second pixel includes a second left sub-pixel and a second right sub-pixel, the first, second, third and fourth data lines are respectively electrically connected to the first A left sub-pixel, a first right sub-pixel, a second right sub-pixel and a second left sub-pixel, the driving method includes: receiving a first pixel data, a second pixel data, a polarity inversion signal and a gamma Selection signal; generate a first group of positive gray-scale voltages, a second group of negative gray-scale voltages, a second group of positive gray-scale voltages and a first group of negative gray-scale voltages; the gamma selection signal has a first state , a first, a second, a third and a fourth digital-to-analog converter are respectively based on the first set of positive gray-scale voltages, the second set of negative gray-scale voltages, the second set of positive gray-scale voltages and the first set of Negative gray-scale voltages for digital-to-analog conversion of the first pixel data, the first pixel data, the second pixel data, and the second pixel data; when the gamma selection signal has a second state, the first, second , the third and the fourth digital-to-analog converters are respectively based on the second group of positive gray-scale voltages, the first group of negative gray-scale voltages, the first group of positive gray-scale voltages, and the second group of negative gray-scale voltages, respectively to the first The pixel data, the first pixel data, the second pixel data, and the second pixel data are converted from digital to analog; when the polarity inversion signal is in a third state, a first, a second, a third, and a first The four buffers respectively receive the output signals of the first, second, third and fourth digital-to-analog converters; when the polarity inversion signal is a fourth state, the first, second, third and fourth buffers Respectively receive the output signals of the second, first, fourth and third digital-to-analog converters; and the first, second, third and fourth buffers respectively via the first, second, third and fourth data lines The first left sub-pixel, the first right sub-pixel, the second right sub-pixel and the second left sub-pixel are driven.

Description of drawings

FIG. 1 is a schematic diagram of a first embodiment of a flat panel display using a dot inversion driving method according to the present invention.

FIG. 2 is an example of a block diagram of the data driver shown in FIG. 1 .

FIG. 3 is an example of the pixel array shown in FIG. 1 .

FIG. 4 illustrates an example of a charge-discharge start signal STB, a gamma selection signal Gamma_SL, a frame start signal YDIO, and a polarity inversion signal POL according to an embodiment of the present invention.

5A and 5B are respectively the equivalent circuit diagrams of the data driver shown in FIG. 2 in the first line period LT1 and the second line period LT2 of the Nth frame period shown in FIG. 4 .

FIG. 6 is a graph showing the relationship between the gray scale value and brightness of the left sub-pixel PL(1,1), the right sub-pixel PR(1,1) and the pixel P(1,1) according to an embodiment of the present invention.

FIG. 7 is a schematic diagram of a second embodiment of a flat panel display using a dual column inversion driving method according to the present invention.

FIG. 8 is an example of the pixel array shown in FIG. 7 .

Fig. 9 shows an example of charge and discharge start signal STB', gamma selection signal Gamma_SL', frame start signal YDIO' and polarity inversion signal POL' according to an embodiment of the present invention.

Fig. 10A is an equivalent circuit diagram of the data driver shown in Fig. 7 in the first line period LT1' and the second line period LT2' of the Nth frame period shown in Fig. 9 .

FIG. 10B is an equivalent circuit diagram of the data driver in FIG. 7 in the third line period LT3' and the fourth line period LT4' of the Nth frame period shown in FIG. 9 .

Figure number:

100, 700: flat panel display

102, 702: flat display panel

104, 704: timing controller

106, 706: data driver

108, 708: scan driver

110, 710: pixel array

202(1)～202(4): gray scale voltage generation unit

204(1)～204(4): digital-to-analog converter

206(1)～206(4): Buffer

208, 218: Inverter

210, 212, 214, 206: switch

Detailed ways

In order to make the above-mentioned purpose, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

The data driver of the present invention generates multiple sets of positive gray-scale voltages and multiple sets of negative gray-scale voltages, so that multiple sub-pixels in a pixel respectively receive the pixels generated according to the corresponding set of positive gray-scale voltages and the set of negative gray-scale voltages. Voltage. In this way, for a pixel, the timing controller can only provide one piece of pixel data, and multiple sub-pixels in a pixel can be driven by different pixel voltages, which can effectively improve the viewing angle of the pixel. At the same time, the present invention has excellent adaptability and can be applied to flat-panel displays with various driving modes.

first embodiment

Please refer to FIG. 1 , which is a schematic diagram of a flat panel display using a dot inversion driving method according to a first embodiment of the present invention. The flat panel display 100 includes a flat display panel 102 , a timing controller 104 , a data driver 106 and a scan driver 108 . The flat display panel 102 includes a pixel array 110 composed of n rows and m columns of pixels P, a plurality of scan lines S1-Sn, and a plurality of data lines L1-L2m, where n and m are positive integers.

A pixel P(1,1) and a pixel P(1,2) are taken as an example for illustration. The pixel P(1,1) includes a left sub-pixel PL(1,1) and a right sub-pixel PR(1,1). The pixel P(1,2) includes a left sub-pixel PL(1,2) and a right sub-pixel PR(1,2). The scan line S1 is used to control the pixel P(1,1) and the pixel P(1,2). The data lines L1˜L4 are electrically connected to the left sub-pixel PL(1,1), the right sub-pixel PR(1,1), the right sub-pixel PR(1,2) and the left sub-pixel PL(1,2) respectively.

The timing controller 104 is used to output a charging and discharging start signal STB, a gamma selection signal Gamma_SL, a frame start signal YDIO, a polarity inversion signal POL, and pixel data Data to the data driver 106 . The data driver 106 drives the pixel array 110 through the data lines L1-L2m, and the scan driver 108 controls the pixel array through the scan lines S1-Sn.

Please refer to FIG. 2 , which shows an example of a block diagram of the data driver 106 in FIG. 1 . The data driver 106 includes a first grayscale voltage generation unit 202(1), a second grayscale voltage generation unit 202(2), a third grayscale voltage generation unit 202(3), and a fourth grayscale voltage generation unit 202(4). ) for respectively outputting the first group of positive gray-scale voltages G1P, the second group of negative gray-scale voltages G2N, the second group of positive gray-scale voltages G2P and the first group of negative gray-scale voltages G1N. The first group of positive gray-scale voltages G1P and the first group of negative gray-scale voltages G1N correspond to the left sub-pixels PL(1,1) and PL(1,2), the second group of positive gray-scale voltages and the second group of negative gray-scale voltages The voltages correspond to the right sub-pixels PR(1,1) and PR(1,2).

The data driver 106 may further include a first DAC 204(1), a second DAC 204(2), a third DAC 204(3), and a fourth DAC 204(4). When the gamma selection signal Gamma_SL has the first state, the input terminals of the first, second, third and fourth digital-to-analog converters 204(1)˜204(4) are electrically connected to the first, second, Output terminals of the third and fourth grayscale voltage generating units 202(1)˜202(4). When the gamma selection signal Gamma_SL has the second state, the input ends of the first to fourth digital-to-analog converters 204(1)˜204(4) are respectively electrically connected to the third, fourth, first and second gray output terminals of the step voltage generating units 202(3), 202(4), 202(1) and 202(2).

Preferably, in the data driver 106, the gamma selection signal Gamma_SL controls a plurality of switches 210, so that the input terminals of the first, second, third and fourth digital-to-analog converters 204(1)-204(4) Selectively and electrically connected to the output terminals of the first, second, third and fourth grayscale voltage generating units 202(1)˜202(4) respectively. The gamma selection signal Gamma_SL processed by the inverter 208 controls a plurality of switches 212, so that the input terminals of the first, second, third and fourth digital-to-analog converters 204(1)-204(4) selectively are electrically connected to the output terminals of the third, fourth, first and second grayscale voltage generating units 202(3), 202(4), 202(1) and 202(2) respectively.

The data driver 106 may further include first to fourth buffers 206(1)-206(4). When the polarity inversion signal POL is in the third state, the input ends of the first, second, third, and fourth buffers 206(1)˜206(4) are electrically connected to the first, second, and second buffers, respectively. Output terminals of the third and fourth digital-to-analog converters 204(1)-204(4). When the polarity inversion signal POL is in the fourth state, the input ends of the first, second, third, and fourth buffers 206(1)˜206(4) are electrically connected to the second, first, and second buffers, respectively. Output terminals of the fourth and third digital-to-analog converters 204(2), 204(1), 204(4) and 204(3). Output terminals of the first, second, third and fourth buffers 206(1)-206(4) are electrically connected to the first, second, third and fourth data lines L1-L4, respectively.

Preferably, in the data driver 106, the polarity inversion signal POL controls a plurality of switches 214, so that the input terminals of the first, second, third and fourth buffers 206(1)˜206(4) are selected are electrically connected to the output terminals of the first, second, third and fourth digital-to-analog converters 204(1)˜204(4), respectively. The polarity inversion signal POL processed by the inverter 218 controls a plurality of switches 216, so that the input terminals of the first, second, third and fourth buffers 206(1)-206(4) selectively are electrically connected to the output terminals of the second, first, fourth and third digital-to-analog converters 204(2), 204(1), 204(4) and 204(3) respectively.

The operation mode of this embodiment is described as follows. Please refer to FIG. 3, FIG. 4, FIG. 5A and FIG. 5B at the same time, wherein FIG. 3 shows an example of the pixel array 110 in FIG. 1, and FIG. , an example of the picture start signal YDIO and the polarity inversion signal POL, Fig. 5A and Fig. 5B are respectively in the first line period LT1 and the second line period LT2 of the Nth picture period shown in Fig. 4, the figure 2 is an equivalent circuit diagram of the data driver 106. N is a positive integer.

As shown in FIG. 5A , during the first line period LT1 , the data driver 106 will drive the first row of pixels of the pixel array 110 . Take the pixels P(1,1) and P(1,2) of the first row of pixels as an example for illustration. The timing controller 106 outputs the pixel data DATA(1,1) corresponding to the pixel P(1,1) to the first and second DACs 204(1) and 204(2), and outputs the pixel data corresponding to the pixel P( 1, 2) pixel data DATA(1, 2) to the third and fourth DACs 204(3) and 204(4).

At this time, the gamma selection signal Gamma_SL has a first state, such as a high level, and the polarity inversion signal POL has a third state, such as a high level. In this way, the first group of positive gray-scale voltages G1P output by the first gray-scale voltage generating unit 202(1) is transmitted to the first digital-to-analog converter 204(1), and the first digital-to-analog converter 204(1) will The set of positive grayscale voltages G1P converts the pixel data DATA(1,1) into a positive polarity pixel voltage VPL(1,1). The second group of negative gray-scale voltages G2N, the second group of positive gray-scale voltages G2P and the first group of negative gray-scale voltages G1N output by the second, third and fourth gray-scale voltage generating units 202(2)-202(4) and sent to the second, third and fourth digital-to-analog converters 204(2)-204(4). The second digital-to-analog converter 204(2) converts the pixel data DATA(1,1) into a negative polarity pixel voltage VPR(1,1) according to the second group of negative grayscale voltages G2N. The third digital-to-analog converter 204(3) converts the pixel data DATA(1,2) into a positive polarity pixel voltage VPR(1,2) according to the second set of positive grayscale voltages G2P. The fourth digital-to-analog converter 204(4) converts the pixel data DATA(1,2) into a negative polarity pixel voltage VPL(1,2) according to the first set of negative grayscale voltages G1N.

Then, the positive polarity pixel voltage VPL(1, 1), the negative polarity pixel voltage VPR(1, 1), the positive polarity pixel voltage VPR(1, 2) and the negative polarity pixel voltage VPL(1, 2) respectively pass through the first , the second, third and fourth buffers 206(1)-206(4) transmit to the data lines L1-L4. The positive polarity pixel voltage VPL(1,1), the negative polarity pixel voltage VPR(1,1), the positive polarity pixel voltage VPR(1,2) and the negative polarity pixel voltage VPL(1,2) will be sent to the The data lines L1˜L4 are electrically connected to the left sub-pixel PL(1,1), the right sub-pixel PR(1,1), the right sub-pixel PR(1,2) and the left sub-pixel PL(1,2). The polarity distribution of these sub-pixels is shown in Figure 3.

Next, as shown in FIG. 5B , during the second line period LT2 , the data driver 106 will drive the pixels in the second row of the pixel array 110 . Take the pixels P(2,1) and P(2,2) of the second row of pixels as an example for illustration. The pixel P(2,1) includes a left sub-pixel PL(2,1) and a right sub-pixel PR(2,1). The pixel P(2,2) includes a left sub-pixel PL(2,2) and a right sub-pixel PR(2,2). The first, second, third and fourth data lines L1-L4 are respectively electrically connected to the right sub-pixel PR(2,1), the left sub-pixel PL(2,1), and the left sub-pixel PL(2,2) with the right sub-pixel PR(2,2). The scan line S2 is adjacent to the scan line S1 for controlling the pixels P(2,1) and P(2,2).

During the second line period LT2, the timing controller 106 outputs the pixel data DATA(2,1) corresponding to the pixel P(2,1) to the first and second DACs 204(1) and 204(2 ), and output the pixel data DATA(2,2) corresponding to the pixel P(2,2) to the third and fourth DACs 204(3) and 204(4).

At this time, the gamma selection signal Gamma_SL has a second state, such as a low level, and the polarity inversion signal POL also has a third state (high level). In this way, the first group of positive gray-scale voltages G1P output by the first gray-scale voltage generating unit 202(1) is transmitted to the third digital-analog converter 204(3), and the third digital-analog converter 204(3) will The group positive grayscale voltage G1P converts the pixel data DATA(2,2) into a positive polarity pixel voltage VPL(2,2). The second group of negative gray-scale voltages G2N, the second group of positive gray-scale voltages G2P and the first group of negative gray-scale voltages G1N output by the second, third and fourth gray-scale voltage generating units 202(2)-202(4) Sent to the fourth, first and second DACs 204(4), 204(1) and 204(2). The fourth digital-to-analog converter 204(4) converts the pixel data DATA(2,2) into a negative polarity pixel voltage VPR(2,2) according to the second group of negative grayscale voltages G2N. The first DAC 204(1) converts the pixel data DATA(2,1) into a positive polarity pixel voltage VPR(2,1) according to the second set of positive gray scale voltages G2P. The second DAC 204(2) converts the pixel data DATA(2,1) into a negative polarity pixel voltage VPL(2,1) according to the first set of negative gray scale voltages G1N.

Then, the positive polarity pixel voltage VPR(2,1) and the negative polarity pixel voltage VPL(2,1), the positive polarity pixel voltage VPL(2,2), and the negative polarity pixel voltage VPR(2,2) respectively pass through the first , the second, third and fourth buffers 206(1)-206(4) transmit to the data lines L1-L4. The positive polarity pixel voltage VPR(2,1) and the negative polarity pixel voltage VPL(2,1), the positive polarity pixel voltage VPL(2,2), and the negative polarity pixel voltage VPR(2,2) are sent to the respective data The lines L1-L4 are electrically connected to the right sub-pixel PR(2,1), the left sub-pixel PL(2,1), the left sub-pixel PL(2,2) and the right sub-pixel PR(2,2). The polarity distribution of these sub-pixels is shown in Figure 3.

As shown in FIG. 4 , when the pixels P( 1 , 1 ) and P( 1 , 2 ) are driven during the Nth frame time, the state of the polarity inversion signal POL is the third state (high level). When the pixels P(1,1) and P(1,2) are driven for the N+1th frame time, the state of the polarity inversion signal POL is the fourth state (low level). The Nth picture time is adjacent to the N+1th picture time. In this way, the effect of inverting the polarities of two adjacent frames can be achieved.

It can be seen from Fig. 3 that the polarity of the left sub-pixel PL(1,1) is opposite to that of the left sub-pixel PL(1,2), and the polarity of the left sub-pixel PL(1,1) is opposite to that of the left sub-pixel PL(2,1). The polarity is also reversed, and at the next frame time, the polarities of all sub-pixels are opposite to those of the corresponding sub-pixels at the previous frame time. Therefore, the driving method according to the waveform shown in FIG. 4 can indeed achieve the effect of dot inversion driving.

In addition, although the polarity of the sub-pixels in the same row is opposite to that of the sub-pixels in the adjacent row, the pixel voltages transmitted by the same data line are of the same polarity. For example, the data line L1 transmits the positive polarity pixel voltage VPL(1,1) in the first line period LT1, and transmits the positive polarity pixel voltage VPR(2,1) in the second line period LT2. Since the polarity of the voltage transmitted by the same data line is the same, the magnitude of the voltage change of the data line can be reduced, and the energy loss of the data line can be reduced.

Preferably, as shown in FIG. 3 , the pixel electrodes PEL(1,1) and PEL(1,2) of the left sub-pixels PL(1,1) and PL(1,2) have substantially the same area, and The pixel electrodes PER(1,1) and PER(1,2) of the right sub-pixels PR(1,1) and PR(1,2) also have substantially the same area. Similarly, the pixel electrodes PEL(2,1) and PEL(2,2) of the left sub-pixels PL(2,1) and PL(2,2) have substantially the same area, and the right sub-pixel PR(1, 2) The pixel electrodes PER(1,2) and PER(2,2) of PR(2,2) also have substantially the same area.

The first grayscale voltage generation unit 202(1), the second grayscale voltage generation unit 202(2), the third grayscale voltage generation unit 202(3) and the fourth grayscale voltage generation unit 202(4) are for example Each is realized by a resistor string, or the first grayscale voltage generating unit 202(1) and the fourth grayscale voltage generating unit 202(4) are realized by a resistor string, and the second grayscale voltage generating unit 202(2) And the third grayscale voltage generating unit 202(3) is realized by another resistor string.

Please refer to FIG. 6 , which shows the relationship curves between the gray scale value and brightness of the left sub-pixel PL(1,1), the right sub-pixel PR(1,1), and the pixel P(1,1). The relationship curve 602 shows an example of the relationship between the gray scale value of the left sub-pixel PL (1, 1) and the brightness, and the relationship curve 604 shows an example of the relationship between the gray scale value of the right sub-pixel PR (1, 1) and the brightness, The relationship curve 606 shows an example of the relationship between the gray scale value and the brightness of the pixel P(1,1). The brightness of the pixel P(1,1) is the sum of the brightness of the left sub-pixel PL(1,1) and the right sub-pixel PR(1,1).

Since all the pixel voltages used to drive the left sub-pixel PL(1,1) are generated with reference to the first group of positive gray-scale voltages G1P and the first group of negative gray-scale voltages G1N, and all the pixel voltages used to drive the right sub-pixel PR( 1, 1) The pixel voltages are all generated with reference to the second group of positive gray-scale voltages G2P and the second group of negative gray-scale voltages G2N, therefore, under the pixel data of the same gray-scale value, they are transmitted to the left sub-pixel PL (1 , 1) and the pixel voltage of the right sub-pixel PR(1, 1) will be different. That is to say, the liquid crystal molecules of the left sub-pixel PL( 1 , 1 ) and the right sub-pixel PR( 1 , 1 ) are arranged differently, so that the viewing angle of the pixel P( 1 , 1 ) increases.

In this embodiment, by providing two sets of positive gray-scale voltages and two sets of negative gray-scale voltages, the pixel voltages of all left sub-pixels PL are referenced to the first set of positive gray-scale voltages G1P and the first set of negative gray-scale voltages. The voltage G1N is generated, and the pixel voltages of all the right sub-pixels PR are generated with reference to the second group of positive gray-scale voltages G2P and the second group of negative gray-scale voltages G2N. In this way, the timing controller 104 only needs to provide the same pixel data for the left sub-pixel PL and the right sub-pixel PR, instead of providing different pixel voltages for the left sub-pixel PL and the right sub-pixel PR as in the conventional method. Therefore, the clock frequencies of the timing controller 104 and the data driver 106 in this embodiment do not need to be doubled. Therefore, this embodiment does not increase the complexity of the circuit design of the timing controller and the data driver, and can save costs.

second embodiment

Please refer to FIG. 7 , which shows a schematic diagram of a flat panel display 700 using a 2-line inversion driving method according to a second embodiment of the present invention. The flat panel display 700 includes a flat display panel 702 , a timing controller 704 , a data driver 706 and a scan driver 708 . The flat display panel 702 includes a pixel array 710 composed of n rows and m columns of pixels P, a plurality of scan lines S1'-Sn', and a plurality of data lines L1'-L2m'.

Different from the first embodiment, in the pixel array 710, the sub-pixels in two adjacent rows are connected to the data lines in the same way, and the gamma selection signal Gamma_SL' changes state only after two line periods. In this way, the driving effect of dual column inversion can be achieved.

Based on the pixels P'(1,1), P'(1,2), P'(2,1), P'(2,2), P'(3,1), P' of the pixel array 710 (3,2), P'(4,1) and P'(4,2) are illustrated as examples. Each pixel includes a left sub-pixel and a right sub-pixel. The data line L1 is electrically connected to the left sub-pixel PL'(1,1), the left sub-pixel PL'(2,1), the right sub-pixel PR'(3,1) and the right sub-pixel PR'(4,1) . The data line L2 is electrically connected to the right sub-pixel PR'(1,1), the right sub-pixel PR'(2,1), the left sub-pixel PL'(3,1), and the left sub-pixel PL'(4,1 ). The data line L3 is electrically connected to the right sub-pixel PR'(1,2), the right sub-pixel PR'(2,2), the left sub-pixel PL'(3,2), and the left sub-pixel PL'(4,2 ). The data line L4 is electrically connected to the left sub-pixel PL'(1,2), the left sub-pixel PL'(2,2), the right sub-pixel PR'(3,2), and the right sub-pixel PR'(4,2 ).

The scan lines S1 to S4 are arranged in sequence. The scan line S1 is used to control the pixels P'(1,1) and P'(1,2). The scan line S2 is used to control the pixels P'(2,1) and P'(2,2). The scan line S3 is used to control the pixels P'(3,1) and P'(3,2). The scan line S4 is used to control the pixels P'(4,1) and P'(4,2).

The operation mode of this embodiment is described as follows. Please refer to FIG. 8 , FIG. 9 , FIG. 10A and FIG. 10B at the same time. FIG. 8 is an example of the pixel array 710 in FIG. 7 . Fig. 9 is an example of the charge and discharge start signal STB', the gamma selection signal Gamma_SL', the frame start signal YDIO', and the polarity inversion signal POL' in this embodiment. FIG. 10A is an equivalent circuit diagram of the data driver 706 in FIG. 7 in the first line period LT1' and the second line period LT2' of the Nth frame period shown in FIG. 9 . FIG. 10B is an equivalent circuit diagram of the data driver 706 in FIG. 7 in the third line period LT3' and the fourth line period LT4' of the Nth frame period shown in FIG. 9 .

As shown in FIG. 10A , in the first line period LT1' and the second line period LT2', the data driver 706 will drive the first row of pixels and the second row of pixels of the pixel array 710 respectively. During the first line period LT1', the timing controller 706 outputs the pixel data DATA'(1,1) corresponding to the pixel P'(1,1) to the first and second DACs 204(1) and 204(2), and output the pixel data DATA'(1,2) corresponding to the pixel P'(1,2) to the third and fourth DACs 204(3) and 204(4). In the second line period LT2', the timing controller 706 outputs the pixel data DATA'(2,1) corresponding to the pixel P'(2,1) to the first and second DACs 204(1) and 204(2), and output the pixel data DATA'(2,2) corresponding to the pixel P'(2,2) to the third and fourth DACs 204(3) and 204(4).

During the first line period LT1', the gamma selection signal Gamma_SL has a first state, such as a high level, and the polarity inversion signal POL has a third state, such as a high level. Therefore, in the first line period LT1', the positive polarity pixel voltage VPL'(1,1), the negative polarity pixel voltage VPR'(1,1), the positive polarity pixel voltage VPR'(1,2) and the negative polarity The pixel voltage VPL'(1, 2) is respectively output by the buffers 206(1)-206(4) of the data driver 706, and sent to the left sub-pixel PL'(1, 1), the right sub-pixel PR'( 1,1), the right sub-pixel PR'(1,2), and the left sub-pixel PL'(1,2).

Similarly, during the second line period LT2', the gamma selection signal Gamma_SL is also maintained at the first state, and the polarity inversion signal POL is still maintained at the third state. Therefore, in the second line period LT2', the positive polarity pixel voltage VPL'(2,1), the negative polarity pixel voltage VPR'(2,1), the positive polarity pixel voltage VPR'(2,2) and the negative polarity The pixel voltage VPL'(2, 2) is respectively output by the buffers 206(1)-206(4) of the data driver 706, and sent to the left sub-pixel PL'(2, 1), the right sub-pixel PR'( 2,1), the right sub-pixel PR'(2,2), and the left sub-pixel PL'(2,2).

As shown in FIG. 10B , in the third line period LT3' and the fourth line period LT4', the data driver 706 will drive the third row of pixels and the fourth row of pixels of the pixel array 710 respectively. In the third line period LT3', the timing controller 706 outputs the pixel data DATA'(3,1) corresponding to the pixel P'(3,1) to the first and second DACs 204(1) and 204(2), and output the pixel data DATA'(3,2) corresponding to the pixel P'(3,2) to the third and fourth DACs 204(3) and 204(4). During the fourth line period LT4', the timing controller 706 outputs the pixel data DATA'(4,1) corresponding to the pixel P'(4,1) to the first and second DACs 204(1) and 204(2), and output the pixel data DATA'(4,2) corresponding to the pixel P'(4,2) to the third and fourth DACs 204(3) and 204(4).

At this time, the gamma selection signal Gamma_SL turns into a second state, such as a low level, and the polarity inversion signal POL also has a third state (high level). In this way, the positive polarity pixel voltage VPR'(3,1), the negative polarity pixel voltage VPL'(3,1), the positive polarity pixel voltage VPL'(3,2), and the negative polarity pixel voltage VPR'(3,2) will be are respectively output from the first, second, third and fourth buffers 206(1)-206(4), and are respectively sent to the right sub-pixel PR'(3,1), the left sub-pixel PL'(3 , 1), the left sub-pixel PL'(3,2) and the right sub-pixel PR'(3,2).

Similarly, in the fourth line period LT4', the gamma selection signal Gamma_SL is also maintained in the second state, and the polarity inversion signal POL is still maintained in the third state. Therefore, in the fourth line period LT4', the positive polarity pixel voltage VPR'(4,1) and the negative polarity pixel voltage VPL'(4,1), the positive polarity pixel voltage VPL'(4,2), and the negative polarity pixel voltage VPR'(4,2), The pixel voltage VPR'(4, 2) will be respectively output from the first, second, third and fourth buffers 206(1)-206(4), and sent to the respective right sub-pixels PR'(4, 1 ), the left sub-pixel PL'(4,1), the left sub-pixel PL'(4,2) and the right sub-pixel PR'(4,2).

The polarity of these subpixels is shown in Figure 8. It can be seen from FIG. 8 that the polarities of adjacent sub-pixels in the first row and the second row of pixels are the same. Adjacent subpixels of the third and fourth rows of pixels have the same polarity, but different polarity than the subpixels of the second row. Therefore, the driving mode according to the waveform shown in FIG. 9 can indeed achieve the effect of dual column inversion driving.

This embodiment also has the advantages of increasing the viewing angle, reducing the variation of the data line voltage to reduce energy consumption, and not needing to increase the clock frequency of the timing controller 704 and the data driver 706 .

It can be known from the above that the data driver using the gamma selection signal of the present invention can be applied to various flat panel displays driven by inversion. The data driver of the present invention can be applied to dot inversion driving (such as the first embodiment), and can also be used for double column inversion driving (such as the second embodiment), but it is not limited to these two driving methods, as long as it is appropriate By changing the waveforms of the gamma selection signal and the polarity inversion signal, the left sub-pixel and the right sub-pixel can receive positive or negative pixel voltages to achieve different inversion driving effects. Therefore, the data driver of the present invention has excellent adaptability.

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field of the present invention can make various changes and modifications without departing from the spirit and scope of the present invention. Modifications, and other different embodiments can be conceived, so the protection scope of the present invention should be defined by the claims.

Claims (18)

1. a data driver, is characterized in that, described data driver comprises: A first, a second, a third, and a fourth gray-scale voltage generation unit, for respectively outputting a first group of positive gray-scale voltages, a second group of negative gray-scale voltages, and a second group of positive gray-scale voltages voltage and a first set of negative gray scale voltages; A first, a second, a third and a fourth digital-to-analog converter, when a gamma selection signal has a first state, the first, the second, the third and the input ends of the fourth digital-to-analog converter are electrically connected to the output ends of the first, the second, the third, and the fourth grayscale voltage generation units, respectively, When the gamma selection signal has a second state, the input terminals of the first, the second, the third and the fourth digital-to-analog converters are respectively electrically connected to the output terminals of the third, the fourth, the first and the second grayscale voltage generation units; and A first, a second, a third and a fourth buffer, when a polarity inversion signal is in a third state, the first, the second, the third and the The input ends of the fourth buffer are respectively electrically connected to the output ends of the first, the second, the third and the fourth digital-to-analog converters, and the When the polarity inversion signal is in a fourth state, the input terminals of the first, the second, the third and the fourth buffers are respectively electrically connected to the second , the output terminals of the first, the fourth and the third digital-to-analog converters. 2. The data driver according to claim 1, wherein the data driver is used to drive a flat display panel, and the flat display panel has a first pixel and a second pixel, and a first, A second, a third and a fourth data line, the first pixel includes a first left sub-pixel and a first right pixel, the second pixel includes a second left sub-pixel and a first Two right sub-pixels, the first, the second, the third and the fourth data lines are respectively electrically connected to the first left sub-pixel, the first right a sub-pixel, the second right sub-pixel and the second left sub-pixel; Wherein, the output terminals of the first, the second, the third and the fourth buffers are respectively electrically connected to a first, a second, a third and a fourth data line; Wherein, the first and second digital-to-analog converters are additionally used to receive a first pixel data corresponding to the first pixel, and the third and fourth digital-to-analog converters are additionally used to to receive a second pixel data corresponding to the second pixel; Wherein, the first group of positive gray-scale voltages and the first group of negative gray-scale voltages correspond to the first left sub-pixel and the second left sub-pixel, and the second group of positive The gray scale voltage and the second group of negative gray scale voltages correspond to the first right sub-pixel and the second right sub-pixel. 3. A flat panel display, characterized in that said flat panel display comprises: A flat display panel, comprising: A first pixel and a second pixel, the first pixel includes a first left sub-pixel and a first right sub-pixel, and the second pixel includes a second left sub-pixel and a second right sub-pixel pixel; a first scan line, used to control the first and the second pixels; A first, a second, a third and a fourth data line are respectively electrically connected to the first left sub-pixel, the first right sub-pixel, the second right sub-pixel and The second left sub-pixel; a timing controller for outputting a polarity inversion signal and a gamma selection signal; and a data driver, comprising: A first, a second, a third, and a fourth gray-scale voltage generation unit, for respectively outputting a first group of positive gray-scale voltages, a second group of negative gray-scale voltages, and a second group of positive gray-scale voltages voltage and a first group of negative gray-scale voltages, the data driver is controlled by the polarity inversion signal and the gamma selection signal, according to the first group of positive gray-scale voltages, The second set of negative grayscale voltages, the second set of positive grayscale voltages and the first set of negative grayscale voltages are used to drive the sub-pixels. 4. The flat panel display as claimed in claim 3, wherein said data driver further comprises a first, a second, a third and a fourth digital-to-analog converter, and in said gamma selection When the signal has a first state, the input terminals of the first, the second, the third and the fourth digital-to-analog converters are respectively electrically connected to the first and the The output terminals of the second, the third and the fourth grayscale voltage generation units, when the gamma selection signal has a second state, the first, the first 2. The input terminals of the third and the fourth digital-to-analog converters are respectively electrically connected to the third, the fourth, the first and the second gray scales The output terminal of the voltage generating unit. 5. The flat-panel display as claimed in claim 4, wherein said data driver further comprises a first, a second, a third and a fourth buffer, for said polarity inversion signal In a third state, the input terminals of the first, the second, the third and the fourth buffers are respectively electrically connected to the first, the first 2. The output terminals of the third and the fourth digital-to-analog converters, when the polarity inversion signal is in a fourth state, the first, the second, and the The input terminals of the third and the fourth buffers are electrically connected to the output terminals of the second, the first, the fourth and the third digital-to-analog converters respectively , the output terminals of the first, the second, the third and the fourth buffers are respectively electrically connected to the first, the second, the first Three and the fourth data line. 6. The flat panel display as claimed in claim 5, wherein when the first pixel and the second pixel are driven for a first frame time, the state of the polarity inversion signal is the Either one of the third state and the fourth state, when the first pixel and the second pixel are driven for a second frame time, the state of the polarity inversion signal is In the other of the third state and the fourth state, the first frame time is adjacent to the second frame time. 7. The flat panel display as claimed in claim 4, wherein the timing controller is further used to output a first pixel data corresponding to the first pixel to the first and second digital an analog converter, and output a second pixel data corresponding to the second pixel to the third and the fourth digital-to-analog converters, the first set of positive grayscale voltages and the The first group of negative gray-scale voltages corresponds to the first left sub-pixel and the second left sub-pixel, and the second group of positive gray-scale voltages and the second group of negative gray-scale voltages correspond to to the first right sub-pixel and the second right sub-pixel. 8. The flat panel display according to claim 7, wherein the pixel electrodes of the first left sub-pixel and the second left sub-pixel have substantially the same area, and the first right The sub-pixel and the pixel electrode of the second right sub-pixel also have substantially the same area. 9. The flat panel display according to claim 7, wherein the panel further comprises: A third pixel and a fourth pixel, the third pixel includes a third left sub-pixel and a third right sub-pixel, and the fourth pixel includes a fourth left sub-pixel and a fourth right sub-pixel pixel, the first, the second, the third and the fourth data lines are respectively electrically connected to the third right sub-pixel, the third left sub-pixel, The fourth left sub-pixel and the fourth right sub-pixel; a second scan line adjacent to the first scan line and used to control the third pixel and the fourth pixel; Wherein, the timing controller is also used to output a third pixel data corresponding to the third pixel to the first and second digital-to-analog converters, and output a third pixel data corresponding to the fourth pixel a fourth pixel data to said third and said fourth digital-to-analog converters; Wherein, when driving the first pixel and the second pixel, the state of the gamma selection signal is one of the first state and the second state, and driving the For the third pixel and the fourth pixel, the state of the gamma selection signal is the other of the first state and the second state. 10. The flat panel display according to claim 9, wherein the pixel electrodes of the third left sub-pixel and the fourth left sub-pixel have substantially the same area, and the third right The sub-pixel and the pixel electrode of the fourth right sub-pixel also have substantially the same area. 11. The flat panel display according to claim 7, wherein said panel further comprises: A third to an eighth pixel, each pixel includes a left sub-pixel and a right sub-pixel, the first data line is electrically connected to the left sub-pixel of the third pixel, the fifth The right sub-pixel of the pixel and the right sub-pixel of the seventh pixel, the second data line is electrically connected to the right sub-pixel of the third pixel and the left sub-pixel of the fifth pixel , and the left sub-pixel of the seventh pixel, the third data line is electrically connected to the right sub-pixel of the fourth pixel, the left sub-pixel of the sixth pixel, and the The left sub-pixel of the eighth pixel, the fourth data line is electrically connected to the left sub-pixel of the fourth pixel, the right sub-pixel of the sixth pixel, and the right sub-pixel of the eighth pixel sub-pixel; and A second to a fourth scanning line, the first to the fourth scanning line are arranged in sequence, the second scanning line is used to control the third pixel and the fourth pixel , the third scanning line is used to control the fifth pixel and the sixth pixel, and the fourth scanning line is used to control the seventh pixel and the eighth pixel; Wherein, the timing controller is further used to output a third pixel data corresponding to the third pixel, a fifth pixel data of the fifth pixel, and a first pixel data of the seventh pixel seven pixel data to the first and second digital-to-analog converters, and output a fourth pixel data corresponding to the fourth pixel, a sixth pixel data corresponding to the sixth pixel, and the an eighth pixel data of the eighth pixel to the third and the fourth digital-to-analog converters; Wherein, when driving the first pixel to the fourth pixel, the state of the gamma selection signal is one of the first state and the second state, and the state of driving the From the fifth pixel to the eighth pixel, the state of the gamma selection signal is the other of the first state and the second state. 12. A driving method of a flat display panel, the flat display panel has a first and a second pixel, and a first, a second, a third and a fourth data line, the first A pixel includes a first left sub-pixel and a first right sub-pixel, the second pixel includes a second left sub-pixel and a second right sub-pixel, the first, the second, The third and the fourth data lines are respectively electrically connected to the first left sub-pixel, the first right sub-pixel, the second right sub-pixel and the second For the left sub-pixel, the driving method includes: receiving a first pixel data, a second pixel data, a polarity inversion signal and a gamma selection signal; generating a first group of positive grayscale voltages, a second group of negative grayscale voltages, a second group of positive grayscale voltages and a first group of negative grayscale voltages; When the gamma selection signal has a first state, a first, a second, a third and a fourth digital-to-analog converter are respectively based on the first group of positive gray scale voltages, the The second group of negative gray-scale voltages, the second group of positive gray-scale voltages, and the first group of negative gray-scale voltages are respectively used for the first pixel data, the first pixel data, and the performing digital-to-analog conversion on the second pixel data and the second pixel data; When the gamma selection signal has a second state, the first, the second, the third and the fourth digital-to-analog converters are respectively based on the second group The positive grayscale voltages, the first set of negative grayscale voltages, the first set of positive grayscale voltages, and the second set of negative grayscale voltages are used for the first pixel data, performing digital-to-analog conversion on the first pixel data, the second pixel data, and the second pixel data; When the polarity inversion signal is in a third state, a first, a second, a third and a fourth buffer respectively receive the first, the second, the output signals of the third and said fourth digital-to-analog converters; When the polarity inversion signal is in a fourth state, the first, the second, the third and the fourth buffers respectively receive the second, the output signals of said first, said fourth and said third digital-to-analog converters; and The first, the second, the third and the fourth buffers respectively pass through the first, the second, the third and the fourth The data lines drive the first left sub-pixel, the first right sub-pixel, the second right sub-pixel and the second left sub-pixel. 13. The driving method according to claim 12, wherein the first group of positive gray-scale voltages and the first group of negative gray-scale voltages correspond to the first left sub-pixel and the first left sub-pixel For two left sub-pixels, the second group of positive grayscale voltages and the second group of negative grayscale voltages correspond to the first right subpixel and the second right subpixel. 14. The driving method according to claim 13, wherein the pixel electrodes of the first left sub-pixel and the second left sub-pixel have substantially the same area, and the first right sub-pixel and the The pixel electrodes of the second right sub-pixel also have substantially the same area. 15. The driving method according to claim 12, wherein said panel further comprises a third pixel, a fourth pixel and a second scanning line, said third pixel comprises a third left sub-pixel and a The third right sub-pixel, the fourth pixel includes a fourth left sub-pixel and a fourth right sub-pixel, the first, the second, the third and the fourth The data lines are respectively electrically connected to the third right sub-pixel, the third left sub-pixel, the fourth left sub-pixel and the fourth right sub-pixel, and the second scanning line Adjacent to the first scan line and used for controlling the third pixel and the fourth pixel, the method further includes: receiving a third pixel data and a fourth pixel data; When the gamma selection signal has the first state, the first, the second, the third and the fourth digital-to-analog converters are respectively based on the first A group of positive gray-scale voltages, the second group of negative gray-scale voltages, the second group of positive gray-scale voltages and the first group of negative gray-scale voltages, respectively for the third pixel data , performing digital-to-analog conversion on the third pixel data, the fourth pixel data, and the fourth pixel data; When the gamma selection signal has the second state, the first, the second, the third and the fourth digital-to-analog converters are respectively based on the first Two sets of positive gray-scale voltages, the first set of negative gray-scale voltages, the first set of positive gray-scale voltages, and the second set of negative gray-scale voltages, respectively for the third pixel data, the third pixel data, the fourth pixel data, and the fourth pixel data are digital-to-analog conversion; from the first, the second, the third and the fourth buffers respectively via the first, the second, the third and the Four data lines drive the third right sub-pixel, the third left sub-pixel, the fourth left sub-pixel and the fourth right sub-pixel; Wherein, when driving the first pixel and the second pixel, the state of the gamma selection signal is one of the first state and the second state, and driving the For the third pixel and the fourth pixel, the state of the gamma selection signal is the other of the first state and the second state. 16. The driving method according to claim 13, wherein the pixel electrodes of the third left sub-pixel and the fourth left sub-pixel have substantially the same area, and the third right sub-pixel and the The pixel electrodes of the fourth right sub-pixel also have substantially the same area. 17. The driving method according to claim 12, wherein said panel further comprises a third to an eighth pixel, and a second to a fourth scanning line, each pixel comprises a left sub-pixel and a right sub-pixels, the first data line is electrically connected to the left sub-pixel of the third pixel, the right sub-pixel of the fifth pixel, and the right sub-pixel of the seventh pixel, the The second data line is electrically connected to the right sub-pixel of the third pixel, the left sub-pixel of the fifth pixel, and the left sub-pixel of the seventh pixel, and the third data line Electrically connected to the right sub-pixel of the fourth pixel, the left sub-pixel of the sixth pixel, and the left sub-pixel of the eighth pixel, the fourth data line is electrically connected to the The left sub-pixel of the fourth pixel, the right sub-pixel of the sixth pixel, and the right sub-pixel of the eighth pixel, the first to the fourth scanning lines are arranged in sequence, The second scan line is used to control the third pixel and the fourth pixel, the third scan line is used to control the fifth pixel and the sixth pixel, the The fourth scan line is used to control the seventh pixel and the eighth pixel, and the method further includes: Wherein, when driving the first to the fourth pixels, the state of the gamma selection signal is one of the first state and the second state, and driving the first For the fifth to eighth pixels, the state of the gamma selection signal is the other of the first state and the second state. 18. The driving method according to claim 12, wherein, when the first pixel and the second pixel are driven for a first frame time, the state of the polarity inversion signal is the Either the third state or the fourth state, when the first pixel and the second pixel are driven for a second frame time, the state of the polarity inversion signal is the The other of the third state and the fourth state, the first frame time is adjacent to the second frame time.

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