CN101216932A - Graphics processing apparatus, unit and method for performing triangle configuration and attribute configuration - Google Patents

Abstract

The invention discloses a graphics processing device, a unit and a method for executing triangle configuration and attribute configuration. One embodiment includes at least one execution unit operable for multi-threaded operation. The execution unit may also execute at least one thread for triangle configuration operations and attribute configuration operations and threads for pixel shader, geometry shader, and vertex shader operations. The graphics processing apparatus, unit and method for performing triangle configuration and attribute configuration according to the present invention can remove at least part of hardware components, thereby reducing the number of gates in the system and resulting in more efficient graphics pipeline, and have flexibility and extensibility for modification of program errors, addition of new features or adjustment of algorithms.

Description

Graphics processing device, unit, and method for executing triangle configuration and attribute configuration

technical field

The present invention relates to computer graphics systems, and more particularly to systems and methods for the triangle configuration and attribute configuration stages of a graphics pipeline.

Background technique

As is well known, the art and science of three-dimensional ("3-D") computer graphics is concerned with the generation or reproduction of two-dimensional ("2-D") images of 3-D objects for display or representation on display devices or monitors, Such as cathode ray tube (CathodeRay Tube, CRT) or liquid crystal display (Liquid Crystal Display, LCD). Objects can be simple geometric primitives such as points, line segments, triangles or polygons. By representing an object as a series of connected planar polygons, such as by representing an object as a series of connected planar triangles, more complex objects can be rendered on the display device. All geometric primitives can ultimately be described by a vertex or a set of vertices (eg, coordinates (X, Y, Z) that define a point (eg, an endpoint of a line segment or a corner of a polygon).

To produce a data set displayed on a computer monitor or other display device as a 2-D projection representing a 3-D primitive, the primitive's vertices may be processed through a series of operations or processing stages in the graphics rendering pipeline. A graphics pipeline is simply a series of processing units, or stages, where output from previous stages can be used as input to subsequent stages. For example, in the content operation phase of a graphics processor, these phases include per-vertex operations, primitive component operations, pixel operations, texture component operations, rendering processing operations, and fragment operations.

In a typical graphics display system, an image database (eg, a command list) may store descriptors for objects of a scene. Objects are described by a number of small polygons that can cover the surface of the object in the same way that small bricks cover a wall or other surface. Each polygon is described as a list of vertex coordinates (X, Y, Z in "model" coordinates) and some specification of material surface properties (i.e., color, texture, glossiness, etc.), and at each vertex The normal vector relative to the surface. For 3D objects with complex curved surfaces, polygons must generally be either triangles or quadrilaterals, with the latter always decomposed into pairs of triangles.

A transformation engine may transform object coordinates corresponding to a viewing angle selected by the user from the user input. In addition, the user can specify the field of view, the size of the image to be generated, and the back end of the field of view volume to include or eliminate the background as desired.

Once the viewing area has been selected, clipping logic eliminates polygons (i.e., triangles) that are outside the viewing area and "clipping" polygons that are partially inside the viewing area and partially outside the viewing area . These clipped polygons correspond to the portion of the polygon that is within the viewport, where the new edges correspond to the edges of the viewport. The polygon vertices are then passed to the next stage with coordinates corresponding to the viewing screen (X, Y coordinates) and the corresponding depth value (Z coordinate) for each vertex. In a typical system, an illumination model is next applied according to the light source, and the polygons and their color values are then passed to the rendering processor.

For each polygon, the rendering processor determines which pixel locations are covered by the polygon, and attempts to write the associated color and depth values (Z values) into the frame buffer. The rendering processor compares the depth value (Z) of the polygon being processed to the depth value of a pixel (which may have been written into the frame buffer). If the new polygon pixel has a lower depth value, indicating that it is in front of the polygon already written to the framebuffer, its value will replace the value in the framebuffer, because the new polygon will obscure the previously processed And write to the polygon in the framebuffer. This process is repeated until all polygons have been reproduced. At this point, the video controller displays the contents of the frame buffer on the display one scan line at a time in reproduction order.

The default method for performing instant rendering is usually to display polygons as pixels that lie inside or outside the polygon. The edges bounding the polygon may appear to have a jagged appearance in static displays and a dragging appearance in animated displays. The underlying problem that creates this effect is called aliasing, and the methods applied to reduce or eliminate the problem are called anti-aliasing techniques.

The demisting method for screen rendering does not need to know what is being rendered, since it only uses the pipeline output samples. A typical demigration method utilizes a linear demigration technique known as Multi-Sample Anti-Aliasing (MSAA), which samples more than one sample per pixel in a single transmission. The number of samples or sub-pixels required for each pixel is called the sampling rate, and in theory, as the sampling rate increases, the associated amount of memory information also increases.

While the foregoing has briefly outlined the operation of the various processing components, those skilled in the art will recognize that processing with respect to graphics data requires considerable enhancement. Therefore, improvements in processing, design, and manufacturing efficiencies are desired, wherever possible. Fixed-function stages of the graphics pipeline, such as triangle configuration and attribute configuration, are necessary for the processing of geometric primitives and pixels in the graphics pipeline. Such fixed-function stages included in known graphics processing units are implemented in fixed-function hardware components or in dedicated hardware. The individual triangle configurations and attribute configuration cells typically used require a considerable number of gates, communication lines, and hardware costs. Additionally, changing the triangle configuration and attribute configuration stages of the graphics pipeline requires changes to such expensive hardware components. Accordingly, there is a heretofore unaddressed need to overcome the deficiencies of the prior art.

Contents of the invention

The present invention relates to systems and methods for implementing the triangle configuration and attribute configuration stages of a graphics pipeline. In short, the architecture of a system embodiment of the present invention can be implemented as follows: the system includes at least one execution unit, and the execution unit can be used for multi-threaded operations, wherein the execution unit can perform triangle configuration operations and attribute configuration operations at least one thread of . The execution unit is programmable to execute at least one thread for at least one selected from: vertex shader operations, pixel shader operations, and geometry shader operations. The execution unit is further capable of stopping at least one thread established for the triangle configuration operation and the attribute configuration operation. The execution unit can further output data from triangle configuration operations (from at least one thread), the programmable triangle configuration operations from the at least one thread, to at least one hardware component outside the execution unit. The execution unit may further resume the suspended thread when data corresponding to at least one thread is received. Finally, the execution unit may store result data from threads in at least one buffer within the execution unit for use by subsequent threads created by the execution unit.

The present invention further provides a graphics processing unit, including: at least one execution unit, the at least one execution unit can be used for multi-thread operation, wherein the at least one execution unit can execute at least one of the triangle configuration operation and the attribute configuration operation threads, and the execution units are operable to perform programmable shader operations; and an execution unit pool control system for scheduling and managing the at least one thread of the at least one execution unit; wherein the execution unit set The region control system may simultaneously initiate the at least one thread for the triangle configuration operation, the attribute configuration operation, and a programmable shader operation.

An embodiment of the method of the present invention includes the step of receiving vertex data corresponding to geometric primitives. This embodiment further includes creating a thread within an execution unit that can be used for multi-threaded operations, wherein the execution unit can perform programmable shader operations. This embodiment further includes performing triangle configuration operations on the vertex data within the execution thread. Finally, this embodiment includes performing attribute configuration operations within the thread to generate pixel attributes identified by the associated vertex data and terminating the thread.

The graphics processing device, the unit and the method for performing triangle configuration and attribute configuration according to the present invention can remove at least part of the hardware components, thereby reducing the number of gates in the system, and leading to a more efficient graphics pipeline, and correcting for program errors , the addition of new features or the adjustment of algorithms, with flexibility and scalability.

Description of drawings

Figure 1 depicts a functional flow diagram of certain components within a graphics pipeline in a computer graphics system.

Figure 2 depicts a block diagram illustrating the fixed-function as well as programmable components of a graphics system.

3 depicts a functional block diagram illustrating a graphics processing unit and certain internal components of the graphics processing unit.

FIG. 4 depicts a block diagram illustrating certain fixed functions as well as programmable components of a graphics system.

5 depicts a functional block diagram illustrating a graphics processing unit and certain internal components of the graphics processing unit.

Figure 6 depicts a flowchart of a method according to an embodiment of the present disclosure.

Detailed ways

Various embodiments of the invention, as illustrated in the drawings, are described in detail below. While the drawings depict several embodiments, they are not intended to limit the disclosure to the one or more embodiments disclosed herein. On the contrary, the scope of the present invention may cover all alternatives, modifications and equivalents thereof.

As above, the present invention relates to a system and method for integrating triangle configuration and attribute configuration operations into a programmable execution unit. Before discussing implementation details of various embodiments, reference is first made to FIG. 1 , which illustrates a block diagram of certain components in a graphics pipeline 100 that may be utilized by or used in embodiments of the present invention. middle. The main components shown in FIG. 1 are a vertex shader 110, a geometry shader 120, a triangle configuration unit 130, a span and tile generator 140, an attribute configuration unit 150, a pixel shader 160, and a frame buffer 170. Those skilled in the art should know and understand the general functions and operations of these components, and thus need not be described in detail herein. In brief, however, a graphics primitive may be defined by positional data (eg, X, Y, Z, and W coordinates), as well as lighting and texture information. All of this information may be passed to the vertex shader 110 . As is known, vertex shader 110 may perform various transformations on the graphics data received from the command manifest. In this regard, data can be converted from World coordinates to Model View coordinates, to Projection coordinates, and finally to Screen coordinates. The functional processing performed by vertex shader 110 is known to those skilled in the art and requires no further description herein. Vertex shader 110 outputs the geometry primitives to geometry shader 120 .

The geometry data generated by the geometry shader 120 and other graphics data are passed to the triangle configuration unit 130 to perform triangle configuration operations. The specific functions and implementation details of the triangle configuration unit 130 may vary in different embodiments. In general, the associated vertex information of the triangle primitives may be passed to the triangle configuration unit 130 , and operations may be performed on the various primitives defined by the graphics data passed to the triangle configuration unit 130 . Among other operations, certain geometric transformations may be performed within triangle configuration unit 130 .

For a given vertex, geometric data such as x, y, z, and w information may be provided (where x, y, and z are geometric coordinates, and w is a homogeneous coordinate). Various transformations can be performed as known to those skilled in the art, for example, from model space to world space, to eye space, to projective space, to homogeneous space, to normalized device coordinates ( or NDC), and finally to screen space (performed by video port conversion). It should be understood that the description herein omits some components of the graphics pipeline for ease of description and clarity, but those skilled in the art should know. As a non-limiting example, certain stages of the rendering processing pipeline of the graphics pipeline have been omitted for clarity, but those of ordinary skill in the art will appreciate that the graphics pipeline may include other stages.

Referring now to FIG. 2 , a block diagram of certain components or stages of a graphics pipeline 200 is illustrated. The first component is the command stream processor 252, which basically receives or reads vertices from memory 250, which are used to form geometric primitives and build work items for the pipeline. In this regard, the command stream processor 252 reads data from memory, and from this data generates triangles, lines, points, or other primitives to be introduced into the pipeline. Once assembled, this geometry information is passed to vertex shader 254 . Vertex shader 254 is shown here as having rounded edges, which are used in this disclosure to indicate that the graphics pipeline executes instructions in a programmable execution unit or pool of execution units (as depicted in FIG. 3 ). said stage of realization. As is known, a vertex shader 254 processes vertices by performing operations such as transformation, scanning, and lighting. Vertex shader 254 then passes the data to geometry shader 256 . Geometry shader 256 receives as input the vertices of a complete primitive, and can output multiple vertices forming a single topology (such as a triangle strip, line, point list, etc.). The geometry shader 256 may also perform various algorithms, such as tessellation, shadow volume generation, and the like.

Geometry shader 256 outputs information to triangle configuration unit 257, which performs operations such as triangular exclusion, determinant computation, refinement, pre-attribute configuration KLMN, edge function computation, and seat belt clipping, as is known. Generally, those skilled in the art should understand the necessary operation of the triangle configuration unit, and no further elaboration thereof is required. The triangle configuration unit 257 outputs the information to the stride and tile generator 258 . This stage of the graphics pipeline is known in the art and need not be discussed in further detail. However, in summary, if the triangle does not have to be rendered to the screen, the stride and tile generator 258 performs a triangle repelling operation. It should be appreciated that other elements of the rendering processing pipeline may operate, such as the Z-test or other fixed function elements of the graphics pipeline. For example, a Z test can be performed to determine the depth of a triangle to further determine whether the triangle should be excluded from rendering to the screen. However, these elements are not further discussed herein as they would be known to those of ordinary skill in the art.

The attribute configuration unit 259 of the graphics pipeline will perform attribute configuration operations if the triangles processed by the triangle configuration unit 257 are not excluded by the stride and tile generator 258 or other stages of the graphics pipeline. The attribute configuration unit 259 generates a list of interpolated variables for known and required attributes to be determined in subsequent stages of the pipeline. Furthermore, as is known, attribute configuration unit 259 handles various attributes associated with geometric primitives being processed by the graphics pipeline.

Each pixel covered by the primitives output by the attribute configuration unit 259 needs to be processed by the pixel shader 260 . Pixel shader 260 performs interpolation to determine the color of pixels output to frame buffer 262, among other operations, as is well known. The operation of the various components illustrated in FIG. 2 is well known to those skilled in the art and requires no further description herein. Therefore, the specific implementation and operation inside these units need not be described herein.

Referring now to FIG. 3 , a graphics processing unit (GPU) 300 of an embodiment is depicted. The graphics system has the ability to create programmable shaders such as geometry shaders, pixel shaders, vertex shaders or other known shaders. The shader is created by a program and is executable by at least one of a plurality of programmable execution unit pools 306 (hereinafter referred to as execution unit pools 306 ). It should be appreciated that execution unit pool 306 may include processing cores capable of multi-threaded operations. Accordingly, execution unit pool 306 may launch more than one thread assigned to a particular type of shader. For example, execution unit pool 306 may launch and execute a thread for geometry shader 310 on one set of data while simultaneously launching another thread for vertex shader 308 on another set. See co-pending US Application Serial No. 11/406,543, filed April 19, 2006, for an example of the structure and operation of the pool of execution units.

However, to summarize the above structure, each execution unit in the execution unit pool 306 is capable of processing multiple instructions within a single clock cycle. Therefore, each execution unit can process multiple threads simultaneously. For example, as mentioned above, an execution unit may concurrently process threads for geometry shader operations and threads for pixel shader operations. The scheduler receives incoming tasks from multiple shader stages to perform shader-related computations and dispatches them to capable execution units. Threads within the execution units of the execution unit pool 306 are individually scheduled to perform shader-related computations so that a given thread can be scheduled over time to perform shader operations for different shader stages . Furthermore, within a given execution unit, certain threads may be assigned to tasks of one shader, while other threads may be assigned to tasks of other shader units. In this way, the load can be balanced among the execution units in the system to achieve flow optimization. Similarly, the load among available threads within the pool of execution units can be balanced to maximize the throughput of the system. Since prior art graphics systems use dedicated shader hardware, robust and dynamic thread management such as in the above architecture cannot be used with graphics systems. Therefore, the flexibility and scalability of the graphics system of this structure cannot be realized.

Execution unit pool control and caching subsystem 304 contains level 2 cache memory for execution unit pool 306 and a system (not shown) for scheduling execution unit pool 306 . In this graphics processing unit, communication between the execution unit pool 306 and its external components is through the execution unit pool control and caching subsystem 304, however, other lines and/or communication lines may be used as is known. Links are established directly to the pool of execution units to facilitate execution of the graphics pipeline. Specifically, the triangle configuration unit 314 , the attribute configuration unit 316 , and the stride and tile generator 318 are fixed-function hardware logic components that communicate with the execution unit pool 306 via the execution unit pool control and cache subsystem 304 .

As mentioned above with reference to FIG. 2, certain components of the graphics pipeline have been omitted from the diagram for clarity. Similarly, certain components of graphics processing unit 300 are omitted from FIG. 3 for clarity; however, those of ordinary skill in the art will appreciate that other components may be required. The operations for triangle configurations, attribute configurations, and span generators/tile generators are known to those of ordinary skill in the art and need not be discussed in further detail. As an example, the triangle configuration unit 314 performs operations such as triangular exclusion, determinant calculation, bounding box calculation, refinement, pre-attribute configuration KLMN, edge function generation, clipping, and belt clipping. Similarly, the attribute configuration unit 316 performs processing operations such as corresponding to attributes of pixels in preparing a pixel shader and in pixel shader operations.

Referring now to FIG. 4, a graphics pipeline 400 of one embodiment of the present invention is depicted. The graphics pipeline 400 depicted in FIG. 4 has different innovations than graphics pipelines in the prior art. Data generally moves down the pipeline from command stream processor 452 . As mentioned above, vertex shader 454 has rounded edges, which indicates that it is a stage of the graphics pipeline implemented by executing instructions in a programmable execution unit or pool of execution units. Similarly, geometry shader 456 is also a programmable stage of the graphics pipeline, and thus is implemented by executing instructions in a programmable execution unit or pool of execution units.

As mentioned above, the delta configuration 457 stage of the graphics pipeline is typically a fixed function stage, which means that this stage is not user programmable. The triangle configuration 457 stages accept data and perform predetermined operations on the data and output results. Previous implementations of the triangle configuration 457 stage typically included separate hardware components from the programmable execution units for the programmable stages of the graphics pipeline 400 , such as geometry shader 456 or vertex shader 454 . According to an embodiment of the invention, the delta configuration 457 stage may be implemented within a programmable execution unit or pool of execution units, although the delta configuration 457 stage is typically not a user-programmable stage of a graphics pipeline. As mentioned above, triangle configuration operations may include triangular exclusion, determinant calculation, bounding box calculation, refinement, pre-attribute configuration KLMN, edge function generation, clipping, and belt clipping.

Similarly, according to this embodiment, the attribute configuration 459 stage can also be implemented in a programmable execution unit, although the attribute configuration 459 stage is generally not a user-programmable stage of the graphics pipeline 400 . Attribute configuration operations may include processing attributes corresponding to pixels in preparing a pixel shader and in pixel shader operations. In accordance with the teachings of the present invention, the operations for the triangle configuration 457 and attribute configuration 459 stages may be implemented in software rather than in fixed-function hardware components. In other words, software interacting with the pool of execution units can issue a set of instructions that operate on a set of data to perform triangle configuration or attribute configuration operations.

According to FIG. 4, stride and tile generator 458 is a fixed-function hardware component rather than a stage of a graphics pipeline implemented within a programmable execution unit. However, those of ordinary skill in the art will appreciate that stride and pixel tile generators or other stages of the graphics pipeline (including, but not limited to, fixed-function stages of the rendering processing pipeline not shown) may also be implemented via the programmable execution unit Executing software instructions in the implementation.

Referring now to FIG. 5, a graphics processing unit 500 of an embodiment of the present invention is depicted. As mentioned above, certain components of the graphics processing unit 500 have been omitted for clarity; The GPU 500 includes a plurality of programmable execution unit pools 506 (hereinafter referred to as execution unit pools 506 ) and an execution unit pool control and cache subsystem 504 . Execution unit pool control and caching subsystem 504 may control thread management of processing cores of execution unit pool 506 and communication between users of the system and other components within GPU 500 . The cache subsystem for one or more cache memories used by the execution unit pool may also reside in the execution unit pool 506 control and cache subsystem 504 . For example, the cache subsystem may be used by the vertex shader thread 508 to store data for use by subsequent threads performing triangle configuration operations, or for typical memory transfers. Alternatively, each execution unit in execution unit pool 506 may include an execution unit buffer for storage of data used by subsequent threads executing within the same execution unit.

As mentioned above, user-programmable stages of the graphics pipeline, such as geometry shader 510 , vertex shader 508 , or pixel shader 512 , may execute within execution unit pool 506 . Since the execution unit pool 506 is usually a processing core capable of multi-threaded operation, the execution unit pool control and cache subsystem 504 is generally responsible for the scheduling of threads within the execution unit pool 506 . When the execution unit pool control and cache subsystem 504 receives an execution request of a programmable shader, it will instruct the execution units in the execution unit pool 506 to create a new thread for execution of the shader. The execution unit pool control and caching subsystem 504 can manage the load on the execution unit pool 506 and transfer resources from one type of shader to another type of shader to efficiently manage the traffic of the graphics pipeline. Such thread management techniques are known and need not be discussed in further detail herein. However, the execution unit pool control and caching subsystem 504 can allocate more execution unit resources to the pixel shader 512 if, for example, the pixel shader 512 is the bottleneck source (in terms of GPU 500 traffic) in order to improve flow.

According to an embodiment of the present invention, when the execution of the graphics pipeline requires triangle allocation 520 or attribute allocation 522 operations, additional threads may be established to perform triangle allocation or attribute allocation operations. Compared with the graphics processing unit in FIG. 3 (the triangle configuration unit and attribute configuration unit in FIG. 3 are separate hardware components in the GPU), the triangle configuration 520 and attribute configuration 522 stages of this embodiment can be implemented in the execution unit pool 506 in the software executed within. In other words, in addition to threads performing programmable shader operations as mentioned above, the execution unit pool 506 can be enabled to perform triangle configuration and attribute configuration by creating threads within the execution units capable of performing triangle configuration and attribute configuration operations operate.

The software instructions for performing triangle configuration and attribute configuration operations may be stored in the execution unit itself, the execution unit pool control and cache subsystem 504, and may originate from the execution unit itself, the execution unit pool control and cache subsystem 504, Alternatively, the software instructions to implement triangle configuration and attribute configuration operations may originate from a software device driver or other location as would be understood by one of ordinary skill in the art.

In order to execute triangle configuration 520 and attribute configuration 522 operations, threads may be created within execution unit pool 506 . Triangle configuration 520 and attribute configuration 522 operations may be performed within threads rather than within separate hardware components from execution unit pool 506 . Since the execution unit pool 506 is capable of multi-threading, a thread for performing triangle configuration 520 and attribute configuration 522 operations may be created while additional threads may be executing other shader operations or even triangle and attribute configuration operations concurrently.

In the GPU 500 of this embodiment, the stride and tile generator 518 may be implemented as an external hardware component of the execution unit pool 506 . As is known, after the triangle configuration 520 operation is complete, at least some of the resulting data from the triangle configuration 520 operation, including edge functions, computed determinants, bounding boxes, and Z differences, can be output to the span and tile generator 518 and possibly other stages of the graphics pipeline not shown (such as Z-test). The thread performing the triangle configuration 520 operation may be suspended between the time the stride and tile generator 518 is performing operations after the triangle configuration 520 operation is complete. After the stride and tile generator 518 or other graphics pipeline operations are complete, the thread may be terminated if the geometry primitive being manipulated by the graphics pipeline is repelled.

In other words, if the geometry primitive does not have to be rendered to the screen, such as if the geometry primitive is covered by other primitives, it may not be necessary to continue processing the primitive in the graphics pipeline. If geometry primitives are not repelled in this portion of the graphics pipeline, the thread may continue executing by performing attribute configuration 522 operations. As is known, an attribute configuration 522 operation in the graphics pipeline may include processing a plurality of attributes corresponding to a plurality of pixels, each of the plurality of pixels including the described Part of multiple properties. After the attribute configuration 522 operation is completed within a thread, the resulting data can be stored in level two cache memory within the execution unit pool control and cache subsystem 504 for use by subsequent threads (including pixel shader threads). Alternatively, the resulting data from the threads can be stored in buffers within each execution unit and made available to the next thread established within the execution unit if the thread needs to use the data. For example, a pixel shader 512 corresponding to the pixel attributes processed by the attribute configuration 522 stage may be established within the execution unit after the thread executing the triangle configuration 520 and attribute configuration 522 operations terminates, wherein after execution of the previous thread , pixel attributes and other data needed for the pixel shader thread resides in the buffer. Other embodiments may include specialized logic modules within the execution unit to enhance the performance of certain triangle configuration or attribute configuration operations. For example, specific logic circuits may be incorporated within the execution units to perform tasks such as triangular triangle repulsion for the operations of the triangle configuration stage.

Embodiments of the present invention provide advantages over graphics processing units implemented in separate hardware components in conjunction with the triangle configuration and attribute configuration stages. Specifically, with respect to the triangle configuration unit 520 and/or the attribute configuration 522 unit implemented as separate hardware components from the execution unit pool, the triangle configuration 520 and the graphics pipeline are implemented in software instructions executed within the execution unit pool. The attribute configuration 522 stage can reduce the number of gates of the GPU 500 . As is known, graphics application programming interfaces require execution unit pool 506 to allow the GPU to execute various programmable stages of the graphics pipeline, such as geometry shaders, vertex shaders, or pixel shaders. Implementing at least the triangle configuration and attribute configuration stages within the existing execution unit pool 506 in the GPU can remove at least the hardware components, thereby reducing the number of gates in the system. It should be appreciated that reducing the gate count of a graphics processing unit according to embodiments of the present invention can reduce the cost of designing and/or producing the GPU. In addition, the cost of the system may also be reduced by removing the need for the GPU to pass data to and/or hardware lines from the triangle hive or attribute hive as a separate hardware component. This is especially useful in low end graphics processing units or computer systems where cost is an important consideration in the design and manufacture of hardware components.

In addition, embodiments of the present invention may result in a more efficient graphics pipeline because triangle configuration 520 and attribute configuration 522 are executed within pool 506 of execution units capable of multi-threading. It should be appreciated that efficient execution of the graphics pipeline can be achieved through thread control and scheduling of pools of execution units. For example, if the triangle allocation operation is the cause of the graphics pipeline bottleneck, resource allocation from the execution unit pool to the triangle allocation operation may be increased to alleviate the bottleneck or mitigate the reduced performance. Alternatively, if another stage of the graphics pipeline, such as the pixel shader, is the cause of the bottleneck in the GPU, resource allocation from the execution unit pool to the pixel shader thread can be increased to increase the throughput of the system. In addition, by implementing the attribute configuration and triangle configuration operations in threads in the execution unit pool 506, a design can create a system that is less dependent on a single bottleneck point. By utilizing thread management and scheduling conventions known in the art to manage the load on the pool of execution units 506, the graphics pipeline can be more efficient.

Another advantage provided by embodiments of the present invention is flexibility and scalability resulting from the elimination of separate hardware components for triangle configuration and attribute configuration operations. For example, embodiments of the present invention may modify the triangle configuration 520 or attribute configuration 522 stage in a graphics processing unit by modifying the software instructions used to perform triangle configuration or attribute configuration operations within the execution unit. Conversely, triangle configuration and attribute configuration hardware components separate from the execution unit pool may require new hardware components to change the triangle configuration or attribute configuration stages of the graphics pipeline. This flexibility may be useful for bug fixes, addition of new features, or adjustments to the algorithms used for the implementation of the triangle configuration 520 or attribute configuration 522 stages.

Referring now to FIG. 6, depicted is a flowchart of a method embodiment 600 of the present invention. In step 602, vertex data representing geometric primitives are received for processing by the triangle configuration and attribute configuration stages of the graphics pipeline. Vertex data for geometry primitives being processed by the graphics pipeline is typically output from the geometry shader for processing by the triangle configuration stage. In step 604, threads are created within the execution units via software instructions to perform triangle configuration operations (step 606). As mentioned above, triangle configuration operations in the graphics pipeline may include (but are not limited to): Triangle Rejection, Determinant Computation, Bounding Box Computation, Refinement, Pre-Attribute Configuration KLMN, Edge Function Generation, Clipping, and Seatband Clipping .

In step 608, after the triangle configuration operation is completed, the bounding box is output to the span and tile generator. The Z difference values are also output to the Z test stage (ZL1, ZL2) of the graphics pipeline. Other elements of the graphics pipeline linked to the output of the triangle configuration stage are not discussed herein, but are known to those of ordinary skill in the art. For example, the triangle configuration stage may output data to other elements of the rendering processing pipeline for processing. After the triangle configuration operation is complete and at least the above output is produced, the thread is suspended until data is returned to the execution unit. For example, if a thread outputs data to a stride and tile generator, Z test, or other stage in the rendering pipeline, the thread must wait until the operations performed in that stage are complete before continuing with the attribute configuration operation. In step 610, the thread is terminated.

In step 612, if the triangle or geometry primitive is not rejected by the stride and tile generator or the Z test, the thread is resumed (step 614), and in step 616, attribute configuration operations are performed within the thread to Pixel attributes associated with the vertex data are generated. For example, a triangle or geometry primitive may be rejected if other elements of the graphics pipeline, such as a Z test, determine that there is no need to output the triangle to a frame buffer in a later stage of the graphics pipeline. In this case, attribute configuration operations are unnecessary. After performing the attribute configuration operation, in step 618, the data from the thread is stored. As mentioned above with reference to the embodiment of FIG. 6, data from threads may be stored in buffers within the execution unit for use by subsequent threads created by the execution unit. Alternatively, data may also be stored in a cache subsystem accessible by other execution units for use by threads created in other execution units. Wherein, the subsequent thread is at least one selected from the following: a pixel shader thread, a vertex shader thread, and a thread capable of performing the triangle configuration operation and the attribute configuration operation. In step 620, the thread is terminated, and execution units may then be allocated to threads dedicated to other stages of the graphics pipeline.

Embodiments of the invention may be implemented in hardware, software, firmware or a combination thereof. In some embodiments, the compression of color data may be performed by software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in an alternate embodiment, the triangle configuration and property configuration stages may be implemented by any one or combination of the following known techniques: Discrete logic circuits with logic gates for implementing logic functions on data signals (discrete logic circuit), application specific integrated circuit (ASIC), programmable gate array (programmable gate array, PGA), field programmable gate array (field programmable gate array, FPGA) etc. with appropriate combinations of logic gates.

As those skilled in the present invention should understand, any process description or block in the flowchart should be understood as representing a module, section, or one or more executable instructions including specific logical functions or steps for implementing the process and alternative implementations are included within the scope of the preferred embodiment of the invention, where functions may be performed in an order different from that disclosed or discussed, including substantially simultaneously or in the reverse order , depending on the functionality involved.

The above description is only a preferred embodiment of the present invention, but it is not intended to limit the scope of the present invention. Any person familiar with this technology can make further improvements on this basis without departing from the spirit and scope of the present invention. Improvements and changes, so the protection scope of the present invention should be defined by the claims of the present application.

A brief description of the symbols in the drawings is as follows:

110: Vertex Shader

120: Geometry Shader

130: Triangular hive

140: Span and Pixel Slice Generator

150: Properties hive

160: Pixel Shader

170: Frame buffer

200: graphics pipeline

250: memory

252: Command Stream Processor

254: Vertex shader

256: Geometry Shader

257: Triangular hive

258: Span and Pixel Slice Generator

259: Attributes Hive

260: Pixel Shader

262: frame buffer

300: Graphics Processing Unit (GPU)

304: Execution unit pool control and cache subsystem

306: Multiple Programmable Execution Unit Pools

310: Geometry Shaders

312: Pixel Shader

314: Triangular hive

316: Attributes Hive

318: Span and Pixel Slice Generator

400: Graphics pipeline

450: memory

452: Command Stream Processor

454: Vertex Shader

456: Geometry Shaders

457: Triangular configuration

458: Span and Pixel Slice Generator

460: Pixel Shader

462: Framebuffer

500: Graphics Processing Unit

504: Execution Unit Pool Control and Cache Subsystem

506: Multiple Programmable Execution Unit Pools

508: Vertex Shader

510: Geometry Shader

512: Pixel Shader

518: Span and Pixel Slice Generator

520: Triangular configuration

522: attribute configuration.

Claims (10)

1. a graphic processing facility is characterized in that, comprising:

At least one performance element, described at least one performance element can be used for multithreading operation, and wherein said at least one performance element can be carried out at least one thread that is used for operation of able to programmeization triangular arrangement and the operation of able to programmeization attribute configuration by software instruction; Wherein

Described at least one performance element is that able to programmeization is selected from following at least one thread with execution: vertex shader operation, pixel coloring device operation and geometric coloration operation;

Described at least one performance element can end to be used for described at least one thread of described able to programmeization triangular arrangement operation and the operation of described able to programmeization attribute configuration;

Described at least one performance element can export the data from described able to programmeization triangular arrangement operation to the outer at least one nextport hardware component NextPort of described performance element, and described able to programmeization triangular arrangement operation is from described at least one thread;

When the data corresponding to described at least one thread were received, described at least one performance element can recover described suspended at least one thread; And

Described at least one performance element can be stored in the result data from described at least one thread in the impact damper in described at least one performance element, and the thread subsequently that is used for being set up by described at least one performance element uses.

2. a Graphics Processing Unit is characterized in that, comprising:

At least one performance element, described at least one performance element can be used for multithreading operation, wherein said at least one performance element can be carried out at least one thread that is used for triangular arrangement operation and attribute configuration operation, and described performance element can be in order to carry out tinter operation able to programme; And

One performance element collection zone control system is in order to the described at least one thread of scheduling with the described at least one performance element of management;

Wherein said performance element collection zone control system can simultaneously initially be used for described at least one thread of described triangular arrangement operation, the operation of described attribute configuration and a tinter operation able to programme.

3. Graphics Processing Unit according to claim 2 is characterized in that, described attribute configuration operation comprises a plurality of attributes of processing corresponding to a plurality of pixels, and each in wherein said a plurality of pixels comprises the part of described a plurality of attributes.

4. Graphics Processing Unit according to claim 2 is characterized in that, described at least one performance element is operating to carry out described triangular arrangement operation and described attribute configuration via software instruction of able to programmeization.

5. Graphics Processing Unit according to claim 2 is characterized in that,

Described at least one performance element can be in order to end to be used for described at least one thread of described triangular arrangement operation and the operation of described attribute configuration;

Described at least one performance element can export the data from described triangular arrangement operation to the outer at least one nextport hardware component NextPort of described at least one performance element, and described triangular arrangement operation is from described at least one thread; And

When the data corresponding to described at least one thread were received, described at least one performance element can recover described suspended at least one thread.

6. Graphics Processing Unit according to claim 2 is characterized in that, described at least one performance element more comprises:

One impact damper is in order to store the result of described at least one thread of carrying out described triangular arrangement operation and the operation of described attribute configuration.

7. a method of carrying out triangular arrangement and attribute configuration in graphic system is characterized in that, comprises the following steps:

Receive vertex data, described vertex data is corresponding to a geometric primitive,

Set up a thread in being used for a performance element of multithreading operation, described performance element can be carried out tinter operation able to programme,

In described thread, described vertex data is carried out the triangular arrangement operation,

In described thread, carry out the attribute configuration operation with the generation pixel property relevant with described vertex data, and

Stop described thread.

8. the method for carrying out triangular arrangement and attribute configuration in graphic system according to claim 7 is characterized in that, more comprises the following steps:

End described thread,

Export the described result of described triangular arrangement operation to a span and pixel sheet generator,

Receive deal with data from described span and pixel sheet generator,

Carry out the attribute configuration operation producing described pixel property from described treated data, and

Recover described thread.

9. the method for carrying out triangular arrangement and attribute configuration in graphic system according to claim 7 is characterized in that, described performance element can be carried out pixel coloring device, geometric coloration and vertex shader operation by software instruction.

10. the method for carrying out triangular arrangement and attribute configuration in graphic system according to claim 7 is characterized in that, more comprises:

Produce another thread by another performance element that can be used for multithreading operation, described another thread can be in order to carry out described triangular arrangement operation with the described thread parallel ground of described performance element;

Wherein said another thread can be carried out simultaneously with described thread.

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