CN101213641A - MIM capacitor in semiconductor device and method for same - Google Patents

Abstract

The present invention provides a planar MIM capacitor formed over one or more metal interconnect layers in a semiconductor device (10). The capacitor has a bottom plate electrode (36) and a top plate electrode (40). An insulator (38) is formed between the plate electrodes. Before forming the first plate electrode, a first insulating layer (28) is deposited over the metal interconnection layer. The first insulating layer (28) is planarized using a chemical mechanical polishing (CMP) process. A second insulating layer (32) is then deposited on the planarized first insulating layer. The first plate electrode (36) is formed above the second insulating layer (32). An insulator (38) is formed on the first plate electrode as a dielectric for the capacitor. A second plate electrode (40) is formed over the insulator (39). Planarizing the first insulating layer and depositing a second insulating layer on top reduces defects and produces more reliable capacitance.

Description

MIM capacitor in semiconductor device and method for same

technical field

The invention relates to the field of semiconductor devices, and more specifically, to metal-insulator-metal (MIM) capacitors in semiconductor devices.

Background technique

One type of capacitor used in integrated circuits is the planar metal-insulator-metal (MIM) capacitor. A flat MIM capacitor consists of a MIM dielectric body between top and bottom plate electrodes. MIM capacitors are commonly used for decoupling and bypass purposes.

In general, flat MIM capacitors are unreliable and may break down early when integrated over copper using typical back-end lithography process integration due to the interlayer dielectric (ILD) between the copper and flat MIM capacitors defects in. Defects such as surface topography, roughness, grain instability, and copper oxidation have been identified as possible causes of reliability failures. To avoid such problems, MIM layout directly over copper structures is ruled out. Unfortunately, this is a severe loss of available on-chip MIM area; this limits the manufacturable capacitors for decoupling and bypass applications. Thus, there is a need to control MIM capacitive defects formed over copper.

Description of drawings

The present invention is illustrated by way of example, but not limitation; wherein like reference numerals indicate similar elements, wherein:

FIG. 1 is a cross-sectional view of a portion of a semiconductor device that can be used to form a MIM capacitor according to one embodiment of the present invention.

FIG. 2 is the device of FIG. 1 after forming a barrier layer and a first insulating layer.

FIG. 3 is the device of FIG. 2 after planarizing the first insulating layer and depositing the second insulating layer.

FIG. 4 is the device of FIG. 3 after formation of the MIM stack.

FIG. 5 is the device of FIG. 4 after patterning the MIM stack to form a MIM capacitor.

FIG. 6 is the device of FIG. 5 after forming an insulating layer over the MIM capacitor.

FIG. 7 is the device of FIG. 6 after forming vias in the insulating layer.

FIG. 8 is the device of FIG. 7 after forming contacts in vias and top interconnect layers.

Those skilled in the art will understand that the illustrations of elements in the figures are for the purpose of simplicity and clarity only and are not necessarily drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the invention.

Detailed ways

In general, the present invention provides a method of forming a semiconductor device with flat MIM capacitance. A planar MIM capacitor is formed over one or more metal interconnect layers. Each metal interconnect layer is separated by an interlevel dielectric layer. The capacitor has a bottom plate electrode and a top plate electrode. An insulator is formed between the plate electrodes. Before forming the first plate electrode, a first insulating layer is deposited on the metal interconnection layer. The first insulating layer is planarized using a chemical mechanical polishing (CMP) process to remove defects such as transfer from the underlying metal. A second insulating layer is then deposited over the planarized first insulating layer to remove additional portions of defects such as smaller defects caused by the CMP process. The bottom plate electrode is formed on the second insulating layer. An insulator serving as a dielectric for the capacitor is formed over the underlying plate electrode. Finally, a top plate electrode is formed on top of the insulator.

By planarizing the first insulating layer and depositing the second insulating layer over the first insulating layer, a surface over the metal is formed that has substantially fewer defects than in the prior art. In this way, the early breakdown of the insulating layer due to defects of the planarized MIM capacitor is reduced and thus more reliable.

1-8 provide illustrations of a portion of a semiconductor device 10 that has undergone a series of processing steps in accordance with the present invention to form a planar MIM capacitor.

FIG. 1 shows a cross-sectional view of a portion of a semiconductor device 10 that can be used to form a planar MIM capacitor. A semiconductor substrate 12 is provided. In a preferred embodiment, semiconductor substrate 12 is silicon. However, other semiconductor materials such as gallium arsenide and silicon-on-insulator (SOI) may also be used. Typically, substrate 12 includes a large number of different active and passive semiconductor devices, such as metal-oxide semiconductor (MOS) transistors, bipolar transistors, resistors, and capacitors. However, for the purpose of understanding the present invention, an understanding of these devices is not necessary and therefore they are not described. A number of interconnect layers may be formed over semiconductor substrate 12 and connected to active circuitry. Typically, there may be as few as one interconnection layer or more than nine interconnection layers depending on the complexity of the integrated circuit. Each interconnect layer includes a plurality of metal conductors separated by an ILD layer. Figure 1 shows two interconnect layers.

ILD layer 14 is deposited on semiconductor substrate 12 . ILD layer 14 may be a combination of layers of dielectric material formed by any process. For example, it can be silicon dioxide (SiO2), carbon-doped silicon dioxide (such as SiCOH), tetraethylorthosilicate (TEOS), boron/phosphorus-doped TEOS (BPTEOS), silicon-rich oxynitride (SRON ), plasma-enhanced nitride (PEN), phosphosilicate glass (PSG), silicon carbonitride (SiCN), or silicon-rich oxide (SRO). Preferably, ILD layer 14 is deposited to a thickness of about 4000 to 10000 Angstroms using plasma enhanced chemical vapor deposition (PECVD). The first conductive layer 16 is formed over the ILD 14 using physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), electroplating, etc., and combinations thereof. In a preferred embodiment, first conductive layer 16 is primarily copper. However, in other embodiments, the first conductive layer 16 may be aluminum or an aluminum-copper alloy. In addition, the first semiconductor layer 16 may be formed of a plurality of material layers. For example, in copper damascene metallization schemes, a diffusion barrier layer comprising tantalum or tantalum nitride is often formed prior to forming the copper layer.

After the second ILD layer 18 is formed on the conductive layer 16 using the same material as the first ILD layer 14 and the first conductive layer 6 , the second conductive layer 20 is formed. In the illustrated embodiment, two interconnect layers are presented. In other embodiments, there may be as few as one or more than nine interconnect layers. The conductors of the interconnection layers are connected to each other and to circuitry on substrate 12 as desired using contacts formed through vias, such as contacts 22 and 24 .

FIG. 2 shows the device of FIG. 1 after barrier layer 26 and insulating layer 28 have been formed. Barrier layer 26 acts as a diffusion barrier to copper in subsequently formed layers. In the embodiment shown, barrier layer 26 is PEN or SICN deposited to a thickness of 300 to 500 Angstroms. An insulating layer 28 is then deposited on barrier layer 26 to a thickness of about 3000 to 6000 Angstroms using a dielectric capping film such as TEOS, fluorinated TEOS (FTEOS), or SIOH. The deposition of layers 26 and 28 can transfer defects from the copper in the second conductive layer and create additional defects. Presently, the surface of the insulating layer 28 may be relatively rough as shown in FIG. 2 . The presented embodiment reduces surface defects and smoothes the roughness of the insulating layer 28 by planarization using a CMP process during wafer processing. The preferred CMP process is conventional, utilizing relatively hard pads and flue gas-treated silica to disperse the usual flow rates of the slurry. Alternatively, rinse the wafer with deionized water, followed by a typical post-polish ammonium hydroxide mechanical scrub. In other embodiments, different CMP processes may be used.

FIG. 3 shows the device of FIG. 2 after planarizing the insulating layer 28 . The thickness of the planarizing insulating layer 28 can be up to about 3000 Angstroms. Note that in some embodiments, nearly all of insulating layer 28 may be removed during the CMP process. The second insulating layer 32 is deposited after the CMP process. The insulating layer 32 is a dielectric capping film such as TEOS, FTEOS or SICOH deposited to a thickness of about 500 to about 3000 Angstroms. The insulating layer 32 further reduces residual defects after CMP.

FIG. 4 shows the device of FIG. 3 after forming a MIM stack 34 on the insulating layer 32 . The MIM stack 34 includes a bottom plate electrode layer 36 , an insulator 38 and a top plate electrode layer 40 . The bottom plate electrode layer 36 is formed of one of tantalum nitride (TaN), titanium nitride (TiN), aluminum (Al), copper (Cu), ruthenium (Ru), iridium (Ir), and the like. In one embodiment, the underlying plate electrode layer 36 is about 100 to 1000 Angstroms thick. The insulator 38 is formed on the underlying plate electrode layer 36 using CVD, PVD, ALD, etc., or a combination thereof. In one embodiment, insulator 38 comprises metal oxides such as tantalum oxide and hafnium oxide that have high linearity (eg, normalized capacitance change typically less than 100 ppm volts). However, for general applications where linearity is less critical, other oxides such as zirconia, barium strontium titanate (BST) and strontium titanate (STO) are also suitable. Alternatively, an insulator 38 other than a high dielectric constant material, such as silicon dioxide, may also be used. The high dielectric constant material used here is a material having a higher dielectric constant than silicon dioxide. Insulator 38 may also be plasma enhanced nitride (PEN), _Six N _y . The top plate electrode layer 40 is formed on the insulator 38 and may have the same composition and thickness as the bottom plate electrode layer 36 .

Figure 5 shows the device of Figure 4 after patterning the MIM stack to form a flat MIM capacitor. A photoresist layer (not shown) is deposited and patterned for subsequent etching of the top plate electrode layer 40 to the desired size and shape. The underlying plate electrode layer 36 and insulator 38 are then patterned with another layer of photoresist (not shown), as is well known in the art, resulting in a flat MIM capacitor 41 as shown in FIG. 5 .

FIG. 6 shows the device of FIG. 5 after an insulating layer 42 has been formed over the MIM capacitor. The insulating layer 42 is an ILD deposited over the semiconductor device 10 . The insulating layer 42 may be any dielectric material such as TEOS, FTEOS, SICOH, and the like. The insulating layer may be about 100-1000 Angstroms thick. Subsequent metal interconnect layers may be formed over insulating layer 42 if desired.

FIG. 7 shows the device of FIG. 6 after vias 44 , 46 and 48 have been formed in insulating layer 42 . A layer of photoresist (not shown) is deposited and patterned to etch insulating layer 42 to form via openings 44 , 46 and 48 . The chemistry of the via etch is conventional and is selective so that the etch stops over the plate electrodes and over the conductors in the interconnect layer 20 .

FIG. 8 shows the device of FIG. 7 after forming contacts 50 , 52 and 54 within the vias and forming a final interconnect layer 56 . After the via openings are formed, a conductive material is filled to form contacts 50 , 52 and 54 . Note that contacts 50 , 52 , 54 represent multiple contacts formed in semiconductor device 10 . Contacts 50 represent electrical connections between conductors of final interconnect layer 56 and conductors in interconnect layer 20 . Contact 52 represents an electrical connection between a conductor in interconnect layer 56 and underlying plate electrode 36 . Similarly, contact 54 represents an electrical connection between a conductor in interconnect layer 56 and top plate electrode 40 . Note that in one application, the flat MIM capacitor 41 is used as a decoupling capacitor. In this case, the interconnect layer 56 can be used to provide power or ground connections. In addition, the contacts for the top and bottom plate electrodes are usually connected to the same interconnect layer.

Generally, in a flat MIM capacitor, the top plate electrode is smaller than the bottom plate electrode. Therefore, the top plate electrode defines the active area of the capacitor, which should be as defect-free as possible for high reliability. However, for larger flat MIM capacitors, the top and bottom plate electrodes have similar dimensions.

According to the given embodiment, large area planar MIM capacitors of about 1 square centimeter or larger can be formed on an integrated circuit (IC). In one embodiment, the flat MIM capacitor can cover 50% or more of the integrated circuit, in another embodiment it covers nearly the entire integrated circuit surface. In addition, planar MIM capacitors can have higher capacitance densities above 10 fF/μm ² by using low-K, medium-K, or high-K insulators deposited using conventional methods such as ALD, CVD, PVD, etc.

The embodiment shown in the figure is a MIM capacitor formed below the final interconnect layer. However, those skilled in the art will appreciate that planar MIM capacitors can be formed anywhere on the substrate 12 . For example, planar MIM capacitors can be formed below the first interconnect layer, above the final interconnect layer, or anywhere in between. There are also related structures not clearly shown in the figure, these are usually present on-chip as a necessary part of the IC's interconnection circuitry.

The benefits, other advantages and solutions to the problems of the present invention have been described above in conjunction with the specific implementation manners. However, benefits, advantages, solutions to problems, and any element that may cause any benefit, advantage, or solution to appear or be more pronounced, are not to be construed as key, essential, or essential features or elements of any or all claims. As used herein, the term "comprising" or any other variation thereof means a non-exclusive inclusion such that a process, method, article or apparatus comprising a series of elements does not contain only those elements, but may also include others not expressly listed or included in the process. An inherent element, method, article, or device.

In the above description, the present invention has been described in conjunction with specific embodiments. However, those skilled in the art appreciate that various modifications and changes can be made without departing from the scope of the present invention as set forth in the appended claims. For example, MIM capacitors can be formed using inlay integration. Accordingly, the description and drawings are to be regarded as illustrative rather than restrictive and all such modifications are deemed to be included within the scope of the present invention.

Claims (20)

1. A method of forming a semiconductor device with flat metal-insulator-metal (MIM) capacitance, comprising the steps of: Provide semiconductor substrates; forming a first insulating layer over the semiconductor substrate; planarizing the first insulating layer; forming a second insulating layer over the first insulating layer; forming a first plate electrode of a flat MIM capacitor on the second insulating layer; forming a third insulating layer above the first plate electrode; A second plate electrode of the flat MIM capacitor is formed on the third insulating layer. 2. The method of claim 1, wherein, The step of planarizing the first insulating layer includes planarizing the first insulating layer using a chemical mechanical polishing process. 3. The method of claim 1, wherein, The second plate electrode is electrically coupled to the interconnection layer. 4. The method of claim 1, wherein, The first insulating layer includes tetraethylorthosilicate (TEOS). 5. The method of claim 1, wherein, The third insulating layer includes a high-K dielectric formed with a thickness of 20 to 1000 angstroms. 6. The method of claim 1, wherein, MIM capacitors are formed directly over the conductors of the interconnection layer. 7. The method of claim 1, wherein, The MIM capacitor covers at least 50% of the surface area of the semiconductor device. 8. The method of claim 1, Also included is the step of forming an interconnect layer having a plurality of conductors over the third insulating layer. 9. The method of claim 8, wherein, The interconnect layer is selected from the group consisting of aluminum and copper. 10. A method of forming a semiconductor device having a metal-insulator-metal (MIM) capacitance, comprising: Provide semiconductor substrates; forming an interconnect layer over the semiconductor substrate; forming a first insulating layer over the interconnect layer; planarizing the first insulating layer; forming a second insulating layer over the first insulating layer; forming the first plate electrode of the MIM capacitor above the second insulating layer; forming a third insulating layer above the first plate electrode; Form the second plate electrode of the MIM capacitor above the third insulating layer: 11. The method of claim 10, wherein, The step of planarizing the first insulating layer includes planarizing the first insulating layer using a chemical mechanical polishing process. 12. The method of claim 10, wherein, Also included is forming a second interconnection layer over the third insulating layer. 13. The method of claim 10, wherein, The second plate electrode is electrically coupled to the second interconnection layer. 14. The method of claim 10, wherein, The first insulating layer includes tetraethylorthosilicate (TEOS). 15. The method of claim 10, wherein, The third insulating layer includes a high-K dielectric formed with a thickness of 20 to 1000 angstroms. 16. The method of claim 10, wherein, MIM capacitors are formed directly over the conductors of the interconnection layer. 17. The method of claim 10, wherein, The MIM capacitor covers at least 50% of the surface area of the semiconductor device. 18. The method of claim 10, wherein, The interconnect layer is selected from the group consisting of aluminum and copper. 19. A semiconductor device comprising: semiconductor substrate; an interconnect layer formed over the semiconductor substrate; a first planarization insulating layer formed over the interconnection layer; a second insulating layer formed over the first insulating layer; a first plate electrode formed on the second insulating layer; a third insulating layer formed over the first electrode; and The second plate electrode is formed on the third insulating layer. 20. The semiconductor device as claimed in claim 19, wherein, The first planarizing insulating layer is planarized using a chemical mechanical polishing process.

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