CN101207088A - Method for manufacturing well extension structure of nonvolatile memory - Google Patents

Abstract

The invention relates to a method for manufacturing a well region extension structure of a nonvolatile memory, which comprises the steps of providing a substrate, wherein the substrate comprises a first conductive type well region, an element isolation structure and a virtual memory unit column. The dummy memory cell row includes a second conductive type source region and a second conductive type drain region. A first interlayer insulating layer with an opening is formed on the substrate, and the opening exposes two adjacent second conduction type drain regions and the element isolation structure between the two adjacent second conduction type drain regions. Part of the element isolation structure in the opening is removed, and a first conductive type extension doping region is formed in the substrate in the opening. The opening is filled with a well region extension conductor layer, and then a dummy bit line electrically connected with the well region extension conductor layer is formed on the substrate.

Description

Manufacturing method of well extension structure of non-volatile memory

technical field

The invention relates to a manufacturing method of a semiconductor element, in particular to a manufacturing method of a well area extension structure of a nonvolatile memory.

Background technique

Non-volatile memory components have become widely used in personal computers and electronic devices due to their advantages of multiple data storage, reading, erasing, etc., and the stored data will not disappear after power failure. A memory element used.

Typical non-volatile memory elements are generally designed to have a stacked gate (Stacked-Gate) structure, including a floating gate (Floating Gate) and a control gate (Control Gate) made of doped polysilicon . The floating gate is located between the control gate and the substrate, and is in a floating state, not connected to any circuit, while the control gate is connected to the word line (Word Line), and also includes the tunneling oxide layer (Tunneling Oxide) and the inter-gate dielectric layer (Inter-Gate DielectricLayer) are respectively located between the substrate and the floating gate and between the floating gate and the control gate.

On the other hand, flash memory arrays commonly used in the industry include a NOR array structure and a NAND array structure. Since the non-volatile memory structure of the NAND array is to connect the memory cells in series, its integration and area utilization are better than the non-volatile memory of the NAND array, and it has been widely used in various applications. in electronic products.

In a known NAND nonvolatile memory, a memory cell well (Cellwell) is provided in the substrate. Because the resistance of the well region of the memory cell is extremely high, the conductivity of the channel region of the device is poor, thereby affecting the operating speed and performance of the device. Therefore, in the known NAND nonvolatile memory, a sufficient number of well pick-up structures are usually formed to reduce the resistance of the well. For example, when performing a read operation on a NAND nonvolatile memory, the well extension structure of the memory cell can be used to maintain the well of the memory cell in a good grounding state to avoid the initial voltage distribution of the memory from becoming large. When performing an erasing operation on the NAND nonvolatile memory, the well area of the storage unit can be quickly charged to the erasing voltage (about 20 volts) by using the well extension structure, thereby speeding up the erasing speed.

At present, there are two methods commonly used in the industry to form the well extension structure. One is to pre-reserve a part of the area along the extending direction of the active area in the memory cell array area as the area for forming the extended structure of the well area when defining the active area. Because the well region extension structure is located in the memory cell array, it will occupy part of the area of the word line. Moreover, the width of the region forming the well extension structure is different from that of the word line. When defining the active region, the difference in line width will be caused by the optical proximity effect (proximity effect), and for the subsequent formation of the word line, bit The photomasks of the line plugs and bit lines also need to be finely tuned, which reduces the process window. The other is to pre-reserve a part of the area between the two memory cell arrays along the extending direction of the bit line as the area for forming the extended structure of the well region. Similarly, this well extension structure will also occupy part of the area of the bit line, and cause a difference in line width due to the optical proximity effect (proximity effect), thereby reducing the process margin.

Contents of the invention

In view of this, one of the objectives of the present invention is to provide a method for manufacturing a well extension structure of a nonvolatile memory, which can increase the integration of components without occupying the area of word lines or bit lines.

Another object of the present invention is to provide a method for manufacturing a well area extension structure of a nonvolatile memory, which is simple, can avoid line width differences caused by optical proximity effects, and can reduce the cost of making precision photomasks , and improve the process margin.

The invention proposes a method for manufacturing a well extension structure of a nonvolatile memory, which includes the following steps. Firstly, a substrate is provided, and a well region of the first conductivity type has been formed in the substrate. Then, a plurality of device isolation structures are formed in the substrate, and a plurality of dummy memory cell rows are formed on the substrate. Each dummy memory cell row includes a second conductivity type source region and a second conductivity type drain region. After forming the first interlayer insulating layer on the base, an opening is formed in the first interlayer insulating layer. The opening at least exposes the second conductivity type drain region of the dummy memory cell row and the element isolation structure between the second conductivity type drain region. A part of the device isolation structure exposed by the opening is removed, and a first conductive type extended doping region is formed in the substrate exposed by the opening. A well extension conductor layer is formed in the opening, and the well extension conductor layer is electrically connected to the first conductivity type well region through the first conductivity type extension doping region. After that, a plurality of dummy bit lines are formed on the substrate, wherein the dummy bit lines are electrically connected to the extended conductor layer in the well region.

According to the manufacturing method of the well extension structure of the non-volatile memory according to an embodiment of the present invention, the formation method of the well extension conductor layer is to firstly form a first conductor material layer on the substrate, and the first conductor material layer is filled with The opening is filled, and then the first conductive material layer on the first interlayer insulating layer is removed to form a well extending conductive layer in the opening.

According to the method of manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, the material of the first conductive material layer includes tungsten, copper or aluminum.

According to the method of manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, the method for removing the first conductive material layer on the first interlayer insulating layer includes performing a chemical mechanical polishing process.

According to the method for manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, after forming the opening in the first interlayer insulating layer and before forming the well extension conductor layer in the opening, it further includes forming Adhesion layer/barrier layer.

According to the method for manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, the material of the adhesion layer/barrier layer is selected from the group consisting of tantalum, tantalum nitride, titanium and titanium nitride one of the .

According to an embodiment of the present invention, the method for manufacturing the extended structure of the well region of the non-volatile memory further includes performing a rapid thermal annealing process after forming the extended doped region of the first conductivity type.

The manufacturing method of the well extension structure of the non-volatile memory according to an embodiment of the present invention further includes forming a plurality of plugs electrically connecting the dummy bit line and the well extension conductor layer on the substrate.

According to the method of manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, the plug is formed by first forming the second interlayer insulating layer on the substrate. Then, the second interlayer insulating layer and the first interlayer insulating layer are patterned to form a plurality of plug openings exposing the well region extending conductor layer. Next, a second conductive material layer is formed on the second interlayer insulating layer to fill up the opening of the plug. Afterwards, part of the second conductor material layer on the second interlayer insulating layer is removed.

According to the method of manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, the material of the second conductive material layer includes tungsten, copper, aluminum or doped polysilicon.

According to the method for manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, the method for forming the opening in the first interlayer insulating layer is to firstly form a patterned opening on the first interlayer insulating layer mask layer. Then, using the mask layer as a mask, part of the first interlayer insulating layer is removed to form an opening. Afterwards, the mask layer is removed.

The invention proposes a method for manufacturing a well extension structure of a nonvolatile memory, which includes the following steps. Firstly, a substrate is provided, and a well region of the first conductivity type has been formed in the substrate. Then, a plurality of device isolation structures are formed in the substrate, and the device isolation structures extend toward the first direction. A plurality of memory cell rows are formed on the substrate. Each memory cell row includes a second conductivity type source region and a second conductivity type drain region. Next, a first interlayer insulating layer is formed on the base, and openings and trenches are formed in the first interlayer insulating layer. The opening at least exposes two adjacent drain regions of the second conductivity type in the memory cell row and an element isolation structure between the two drain regions of the second conductivity type. The trench extends in a second direction and exposes the source region of the second conductivity type, and the second direction is intersected with the first direction. Then, part of the device isolation structure exposed by the opening is removed, and a first conductive type extended doping region is formed in the substrate exposed by the opening. A well extending conductor layer is formed in the opening, and a source line is formed in the trench. The well region extension conductor layer is electrically connected to the first conductivity type well region through the first conductivity type extended doped region. Afterwards, a plurality of bit lines and a plurality of dummy bit lines are formed on the substrate, wherein the bit lines are electrically connected to the drain region of the second conductivity type, and the dummy bit lines are respectively electrically connected to the extended conductor layer of the well region and the source line, and the dummy bit lines There is an open circuit between the well extension conductor layer and the source line.

According to the manufacturing method of the well extension structure of the non-volatile memory according to an embodiment of the present invention, the formation method of the well extension conductor layer and the source line is as follows. Firstly, a first conductive material layer is formed on the substrate, and the first conductive material layer fills the opening and the trench. Then, the first conductive material layer on the first interlayer insulating layer is removed to form a well extension conductive layer in the opening and a source line in the trench.

According to the method of manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, the method for removing the first conductive material layer on the first interlayer insulating layer includes performing a chemical mechanical polishing process.

According to the method of manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, the material of the first conductive material layer includes tungsten, copper or aluminum.

The method for manufacturing the well extension structure of the nonvolatile memory according to an embodiment of the present invention further includes forming a mask on the first interlayer insulating layer before the step of removing part of the element isolation structure in the opening layer, the mask layer covers the trench and exposes the opening. Then after the step of forming the extended doped region of the first conductivity type in the substrate, the mask layer is removed.

According to an embodiment of the present invention, the method for manufacturing the extended structure of the well region of the non-volatile memory further includes performing a rapid thermal annealing process after forming the extended doped region of the first conductivity type.

The method for manufacturing the extended well region structure of the nonvolatile memory according to an embodiment of the present invention further includes forming a plurality of first plugs electrically connecting the bit line and the drain region of the second conductivity type on the substrate, A plurality of second plugs are electrically connected to the dummy bit lines and the well extension conductor layer, and a plurality of third plugs are electrically connected to the dummy bit lines and the source lines.

According to the method of manufacturing the well extension structure of the non-volatile memory according to an embodiment of the present invention, the forming methods of the first plug, the second plug and the third plug are as follows. First, a second interlayer insulating layer is formed on a substrate. Then, pattern the second interlayer insulating layer and the first interlayer insulating layer to form a plurality of first plug openings exposing the drain region of the second conductivity type, and a plurality of second plug openings exposing the extended conductor layer of the well region and a plurality of third plug openings exposing the source lines. Next, a second conductive material layer is formed on the second interlayer insulating layer to fill up the first plug opening, the second plug opening and the third plug opening. Afterwards, part of the second conductor material layer on the second interlayer insulating layer is removed.

According to the manufacturing method of the well extension structure of the non-volatile memory according to an embodiment of the present invention, the forming method of the bit line and the dummy bit line is as follows. First, a third conductor material layer is formed on the second interlayer insulating layer. Then, the third conductor material layer is patterned to form a bit line and a dummy bit line, wherein the dummy bit line formed on the second plug and the third plug is an open circuit.

In the manufacturing method of the well extension structure of the non-volatile memory of the present invention, firstly, an extended doping region of the first conductivity type is formed between two adjacent drain regions of the second conductivity type in the memory cell array, so as to As an extension of the first conductivity type well. Then use the well extension conductor layer and the well extension plug to connect the first conductive type extended doped region and the bit line. In this way, the resistance of the well of the first conductivity type can be reduced, and the conductivity of the channel region can be increased. In turn, the operating speed of the device can be accelerated, and the performance of the device can be improved.

Moreover, in the manufacturing method of the well extension structure of the non-volatile memory of the present invention, since the well extension structure and the source line plug are located on the same two memory cell rows, the well extension structure does not The additional area of the memory cell array or the area of the word line and the bit line is occupied, and there is no problem of line width difference. Therefore, the proximity effect can be avoided and the process margin can be improved.

In addition, the well extension structure of the present invention is formed simultaneously with the source line plug, which can simplify the process steps and improve the process margin.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

1A to 1F are top views of the manufacturing process of the well extension structure of the non-volatile memory according to an embodiment of the present invention.

Figures 2A to 2F are cross-sectional views along line A-A' in Figures 1A to 1F respectively.

3A to 3F are cross-sectional views of the manufacturing process along the line B-B' in FIGS. 1A to 1F .

4A to 4F are cross-sectional views of the manufacturing process along the line C-C' in FIGS. 1A to 1F .

[Description of main reference signs]

100: base

102: Well area of the first conductivity type

104: Component isolation structure

106: Active area

108: Memory cell row

108a: Virtual memory cell row

110a, 110b: selection transistors

112: storage unit

114: second conductivity type drain region

116: second conductivity type source region

118: doped area

120a: tunneling dielectric layer

120b: floating gate

120c: inter-gate dielectric layer

120d: Control grid

122: the word lines 122 are connected in series.

124a: Select gate dielectric layer

124b: select gate

126: select gate line

128, 146: interlayer insulating layer

130, 136: mask layer

132, 138: Opening

134: Ditch

140: first conductivity type extended doping region

142a, 144a: Adhesion layer/barrier layer

142b, 144b: conductor material layer

142: Extended conductor layer in the well area

144: Source line

148, 150, 152: plug opening

154: Well extension plug

156: bit line plug

158: Source line plug

160a, 160b: dummy bit lines

162: bit line

Detailed ways

1A to 1F are top views of the manufacturing process of the well extension structure of the non-volatile memory according to an embodiment of the present invention. 2A to 2F are cross-sectional views along the line A-A' in FIGS. 1A to 1F respectively. 3A to 3F are cross-sectional views of the manufacturing process along the line B-B' in FIGS. 1A to 1F . 4A to 4F are cross-sectional views of the manufacturing process along the line C-C' in FIGS. 1A to 1F .

Please refer to FIG. 1A , FIG. 2A , FIG. 3A and FIG. 4A at the same time. Firstly, a substrate 100 is provided. The substrate 100 is, for example, a silicon substrate. A well region 102 of the first conductivity type has been formed in the substrate 100 . Then, a plurality of element isolation structures 104 are formed in the substrate 100 to define active regions 106 between adjacent element isolation structures 104 . The device isolation structure 104 is, for example, a shallow trench isolation structure or a field oxide layer. Any known method can be used to form the shallow trench isolation structure or the field oxide layer. The element isolation structures 104 are arranged in parallel in the X direction (row direction).

Next, a plurality of memory cell rows 108 are formed on the substrate 100 . The memory cell row 108 is composed of, for example, two selection transistors 110 a, 110 b, a plurality of memory cells 112 , a second conductivity type drain region 114 and a second conductivity type source region 116 . A plurality of memory cells 112 are connected in series between the second conductive type source region 116 and the second conductive type drain region 112 . The selection transistor 110 b is formed between the memory unit 112 and the source region 116 of the second conductivity type; the selection transistor 110 a is formed between the memory unit 112 and the drain region 114 of the second conductivity type. Moreover, the memory cells 112 and the memory cells 112 and the selection transistors 110 a and 110 b are connected together by the doped region 118 , for example.

Each memory cell 112 includes at least a tunneling dielectric layer 120a (tunnelingdielectric layer), a floating gate 120b (floating gate), an inter-gate dielectric layer 120c (inter-gatedielectric layer) and a control gate 120d (control gate) from the substrate 100. ). In the Y direction (column direction), the control gates 120d of the memory cells 112 in each column are, for example, connected in series by word lines 122 arranged in parallel in the Y direction (column direction).

The selection transistors 110a, 110b include at least a selection gate dielectric layer 124a and a selection gate 124b starting from the substrate 100 . In the Y direction (column direction), the selection gates 124b of the selection transistors 110a and 110b in each column are connected in series by the selection gate lines 126 arranged in parallel in the Y direction (column direction). The method for forming the memory cell row 108 can adopt any known method, which will not be repeated here. In the present invention, in the memory cell row 108, the source line plug and the well region extension structure of the present invention will be formed on at least two memory cell rows 108. These two memory cell rows 108 are not used to store data, so in the following In the description above, it will be referred to as a virtual memory cell row 108a.

Referring to FIG. 1B , FIG. 2B , FIG. 3B and FIG. 4B simultaneously, an interlayer insulating layer 128 is formed on the substrate 100 . The material of the interlayer insulating layer 128 is, for example, silicon oxide, phosphosilicate glass, borophosphosilicate glass or other suitable dielectric materials, and its formation method is, for example, chemical vapor deposition. Next, a mask layer 130 is formed on the interlayer insulating layer 128 . The material of the mask layer 130 is, for example, silicon nitride or other suitable materials, and its formation method is, for example, chemical vapor deposition.

Afterwards, a patterned photoresist layer (not shown) is formed on the mask layer 130, and the patterned photoresist layer exposes a block of the second conductivity type drain region 114 corresponding to the dummy memory cell row 108a. The strip-shaped region and the strip-shaped region corresponding to the source region 116 of the second conductivity type. The method for forming the patterned photoresist layer is, for example, to form the photoresist layer by spin-on coating first, and then pattern it by photolithography. Next, the exposed mask layer 130 is removed by using the patterned photoresist layer as a mask, such as by etching. Afterwards, the patterned photoresist layer is removed, and the removal method is, for example, removing most of the photoresist layer by an ashing process, and then performing a cleaning process to remove the remaining photoresist layer layer. Then, using the patterned mask layer 130 as a mask, the exposed interlayer insulating layer 120 is removed to form the opening 132 and the trench 134 . A method of removing the exposed interlayer insulating layer 120 is, for example, an etching method. Wherein, the opening 132 exposes two adjacent drain regions 114 of the second conductivity type and the element isolation structure 104 located between the two adjacent drain regions 114 of the second conductivity type. In addition, the trench 134 exposes all the source regions 116 of the second conductivity type in the Y direction. The first conductivity type is, for example, P type, and the second conductivity type is, for example, N type; of course, the first conductivity type may also be N type, and the second conductivity type is P type.

Then, please refer to FIG. 1C, FIG. 2C, FIG. 3C and FIG. 4C at the same time. A mask layer 136 is formed on the mask layer 130 , and the mask layer 136 covers the entire trench 134 and has an opening 138 . The opening 138 together with the opening 132 exposes the second conductive type drain region 114 . The material of the mask layer 136 is, for example, photoresist, and its formation method is, for example, first forming a photoresist layer (not shown) by spin coating, and then patterning by photolithography. Afterwards, part of the device isolation structure 104 exposed by the opening 138 and the opening 132 is removed to form the device isolation structure 104a. The surface of the device isolation structure 104 a is lower than the surface of the substrate 100 . A method for removing part of the device isolation structure 104 in the opening 124 is, for example, using the mask layer 136 and the mask layer 130 as masks to perform an etching process.

Then, in the substrate 100 exposed by the opening 138 and the opening 132 , an extended doped region 140 of the first conductivity type is formed. The method for forming the extended doped region 140 of the first conductivity type is, for example, using the mask layer 136 and the mask layer 130 as a mask to perform an ion implantation process to form the extended doped region of the first conductivity type in the substrate 100 exposed in the opening 124. Miscellaneous area 140. In particular, since part of the element isolation structure 104 is removed, the ion implantation process can be deeper to form the extended doped region 140 of the first conductivity type with a deeper and wider doped area.

Next, referring to FIG. 1D , FIG. 2D , FIG. 3D and FIG. 4D , the mask layer 136 is removed to expose the trench 134 . The method for removing the mask layer 136 is, for example, first removing most of the photoresist layer by an ashing process, and then performing a cleaning process to remove the remaining photoresist layer. In one embodiment, after removing the mask layer 136 , a rapid thermal annealing process may be performed to repair the exposed surface of the substrate 100 damaged by the etching process.

Then, a well extension conductor layer 142 is formed in the opening 132 , and a source line 144 is formed in the trench 134 . The well extension conductor layer 142 is electrically connected to the first conductivity type well region 102 through the first conductivity type extension doped region 140 . The method for forming the well extension conductive layer 142 and the source line 144 is, for example, to firstly form a conductive material layer on the substrate 100 , and the conductive material layer fills the opening 132 and the trench 134 . Next, a chemical mechanical polishing process is performed, using the mask layer 130 as a polishing stop layer to remove part of the conductor material layer. In one embodiment, the well extension conductive layer 142 is composed of an adhesive layer/barrier layer 142a and a conductive layer 142b; the source line 144 is composed of an adhesive layer/barrier layer 144a and a conductive layer 144b. The adhesive layer/barrier layer 142a and the adhesive layer/barrier layer 144a can increase the adhesion of the metal material to different metal materials; or can block the diffusion of the metal material to avoid spiking. Wherein, the material of the adhesive layer/barrier layer 142a and the adhesive layer/barrier layer 144a is, for example, one of the group consisting of tantalum, tantalum nitride, titanium, and titanium nitride, and the formation method thereof is, for example, physical vapor deposition or chemical vapor deposition method. The material of the conductor layer 142b and the conductor layer 144b is, for example, aluminum, tungsten, copper, and the formation method thereof is, for example, physical vapor deposition or chemical vapor deposition.

Afterwards, referring to FIG. 1E , FIG. 2E , FIG. 3E and FIG. 4E , the mask layer 130 is removed. Then, an interlayer insulating layer 146 is formed on the interlayer insulating layer 128 . The interlayer insulating layer 146 and the interlayer insulating layer 138 are patterned to form a plug opening 148 , a plug opening 150 , and a plug opening 152 . The plug opening 148 is located above the well extension conductor layer 142 and exposes the well extension conductor layer 142 ; the plug opening 150 exposes the second conductive type drain region 114 ; the plug opening 152 exposes the source line 144 . The plug opening 148 and the plug opening 152 are located above the same two adjacent dummy memory cell rows 108a. A method of patterning the interlayer insulating layer 146 and the interlayer insulating layer 138 is, for example, a photolithographic etching technique.

Afterwards, please refer to FIG. 1F, FIG. 2F, FIG. 3F and FIG. 4F at the same time, forming a conductive material layer (not shown) on the interlayer insulating layer 146, and filling the plug opening 148, the plug opening 150, and the plug opening 152. The material of the conductive material layer is, for example, tungsten, copper, aluminum or doped polysilicon. In one embodiment, when the material of the conductive material layer is doped polysilicon, its formation method is, for example, first forming polysilicon material by chemical vapor deposition, and then performing ion implantation process; or by in-situ (in-situ) doping complex way of chemical vapor deposition. In another embodiment, when the conductive material layer is tungsten, copper or aluminum, its formation method is, for example, physical vapor deposition or chemical vapor deposition. Of course, an adhesion layer/barrier layer (not shown) can also be optionally formed. Afterwards, a chemical mechanical polishing process is performed to remove the conductive material layer on the interlayer insulating layer 146 . A well extension plug 154 is formed in the plug opening 148 ; a bit line plug 156 is formed in the plug opening 150 ; and a source line plug 158 is formed in the plug opening 152 . Wherein, each bit line plug 156 is electrically connected to a drain region 112 of the second conductivity type; the well extension plug 154 is electrically connected to the well extension conductor layer 142; and the source line plug 158 is electrically connected to the source line 144 electrical connections. Wherein, the source line plug 158 and the well extension plug 154 are located above the same two dummy memory cell rows 108a.

Subsequently, on the interlayer insulating layer 146, a conductor material layer (not shown) is formed. The material of the conductive material layer is, for example, tungsten, copper, aluminum or doped polysilicon. In one embodiment, when the material of the conductive material layer is doped polysilicon, its formation method is, for example, first forming polysilicon material by chemical vapor deposition, and then performing ion implantation process; vapor deposition method. In another embodiment, when the conductive material layer is tungsten, copper or aluminum, its formation method is, for example, physical vapor deposition or chemical vapor deposition. Of course, an adhesion layer/barrier layer (not shown) may also be optionally formed. Then, the layer of conductive material is patterned to form a plurality of bit lines 162 and dummy bit lines 160a, 160b. Wherein, the dummy bit lines 160a, 160b are located on the well extension plug 142 and the source line plug 144, and the dummy bit lines 160a, 160b form an open circuit between the well extension plug 142 and the source line plug 144. .

It is worth mentioning that the first conductive type extended doped region 140 , the well extension conductor layer 142 , the well extension plug 154 and the dummy bit line 160 a are electrically connected to each other to form a well extension structure. Therefore, the well extension structure can be used as an electrical extension path of the first conductivity type well region 102 to reduce the resistance of the first conductivity type region 102 and increase the conductivity of the channel region. In this way, the operation speed of the non-volatile memory can be accelerated, and the device performance can be improved.

Moreover, since in the known process, the space of two memory cell rows (virtual memory cell rows 108a) will be wasted every time a source line plug 158 is formed, the well extension structure and the source line plug of the present invention 158 are located on the same two dummy memory cell rows 108a. Therefore, the well extension structure of the present invention does not need to occupy an additional area of the memory cell array or the area of the word line and the bit line, and there is no problem of line width difference. Therefore, proximity effect can be avoided and process margin can be improved. In addition, the number of well extension structures of the present invention can also be set according to the number of source line plugs 158 .

In addition, the method for forming the well extension structure of the present invention is to add some simple process steps before the step of forming the source line plug, and form the well extension structure at the same time as the source line plug is formed. Therefore, the method for forming the well extension structure of the present invention is simple and has high process margin.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be subject to the scope defined by the appended claims.

Claims (20)

1. the manufacture method of the bore field extension structure of a nonvolatile memory comprises:

Substrate is provided, has been formed with the first conductivity type wellblock in this substrate;

In this substrate, form a plurality of component isolation structures;

It is capable to form a plurality of virtual memory cells in this substrate, capable second conductive type source region and the second conductivity type drain region of comprising of each described virtual memory cell;

In this substrate, form first interlayer insulating film;

Form opening in this first interlayer insulating film, this opening exposes the capable described second conductivity type drain region of described virtual memory cell and this component isolation structure between the described second conductivity type drain region at least;

Remove this opening institute this component isolation structure of exposed portions;

In this substrate that this opening exposed, form first conductivity type and extend doped region;

Form the wellblock and extend conductor layer in this opening, this wellblock is extended conductor layer and is electrically connected this first conductivity type wellblock via this first conductivity type extension doped region; And

Form many dummy bitlines in this substrate, described dummy bitline is electrically connected this wellblock and extends conductor layer.

2. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 1, wherein this wellblock formation method of extending conductor layer comprises:

In this substrate, form first conductor material layer, to fill up this opening; And

Remove this first conductor material layer on this first interlayer insulating film, extend conductor layer in this opening, to form this wellblock.

3. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 2, wherein the material of this first conductor material layer comprises tungsten, copper or aluminium.

4. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 2, the method that wherein removes this first conductor material layer on this first interlayer insulating film comprises carries out chemical mechanical milling tech.

5. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 2, wherein in this first interlayer insulating film, form after this opening, and in this opening, form this wellblock and also comprise formation adhesion coating/barrier layer before extending conductor layer.

6. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 5, wherein the material of this adhesion coating/barrier layer is to be selected from one of them of group that tantalum, tantalum nitride, titanium and titanium nitride form.

7. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 1,, also comprise and carry out rapid thermal anneal process forming after this first conductivity type extends doped region.

8. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 1, also be included in and be electrically connected a plurality of connectors that conductor layer is extended in described dummy bitline and this wellblock in this substrate.

9. the manufacture method of the bore field extension structure of nonvolatile memory according to Claim 8, the formation method of wherein said connector comprises:

In this substrate, form second interlayer insulating film:

This second interlayer insulating film of patterning and this first interlayer insulating film expose a plurality of plug opens that conductor layer is extended in this wellblock to form;

On this second interlayer insulating film, form second conductor material layer, and fill up described plug open; And

Remove this second conductor material layer of part on this second interlayer insulating film.

10. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 9, wherein the material of this second conductor material layer comprises tungsten, copper, aluminium or doped polycrystalline silicon.

11. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 1, the method that forms this opening in this first interlayer insulating film comprises:

On this first interlayer insulating film, form the mask layer of patterning;

With this mask layer is mask, removes this first interlayer insulating film of part to form this opening; And

Remove this mask layer.

12. the manufacture method of the bore field extension structure of a nonvolatile memory comprises:

Substrate is provided, has been formed with the first conductivity type wellblock in this substrate;

Form a plurality of component isolation structures in this substrate, those component isolation structures extend toward first direction;

Form a plurality of memory cell rows in this substrate, each described memory cell rows comprises second conductive type source region and the second conductivity type drain region;

In this substrate, form first interlayer insulating film;

In this first interlayer insulating film, form opening and irrigation canals and ditches, this opening exposes two second adjacent in described memory cell rows conductivity type drain regions and this component isolation structure between this two second conductivity type drain region at least, and these irrigation canals and ditches are toward the second direction extension and expose described second conductive type source region, and this second direction and this first direction are staggered;

Remove this opening institute this component isolation structure of exposed portions;

In this substrate of exposure in this opening, form first conductivity type and extend doped region;

Form the wellblock and extend conductor layer in this opening, this wellblock is extended conductor layer and is electrically connected this first conductivity type wellblock via this first conductivity type extension doped region, and forms source electrode line in these irrigation canals and ditches; And

In this substrate, form multiple bit lines and many dummy bitlines, wherein said bit line is electrically connected the described second conductivity type drain region, described dummy bitline is electrically connected this wellblock respectively and extends conductor layer and this source electrode line, and described dummy bitline extends between conductor layer and this source electrode line to opening circuit in this wellblock.

13. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 12, wherein this wellblock formation method of extending conductor layer and this source electrode line comprises:

In this substrate, form first conductor material layer, and fill up this opening and these irrigation canals and ditches; And

Remove this first conductor material layer on this first interlayer insulating film, extend conductor layer and in these irrigation canals and ditches, form this source electrode line in this opening, to form this wellblock.

14. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 13, the method that wherein removes this first conductor material layer on this first interlayer insulating film comprises carries out chemical mechanical milling tech.

15. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 14, wherein the material of this first conductor material layer comprises tungsten, copper or aluminium.

16. manufacture method according to the bore field extension structure of the nonvolatile memory of claim 12, also be included in before the step of this component isolation structure of part that removes in this opening, form mask layer on this first interlayer insulating film, this mask layer covers this irrigation canals and ditches, and exposes this opening; And

In this substrate, form after the step of this first conductivity type extension doped region, remove this mask layer.

17., wherein, also comprise and carry out rapid thermal anneal process forming after this first conductivity type extends doped region according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 12.

18. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 12, also be included in and form a plurality of first connectors of being electrically connected described bit line and the described second conductivity type drain region respectively in this substrate, be electrically connected described dummy bitline and a plurality of second connectors of conductor layer and a plurality of the 3rd connectors that are electrically connected described dummy bitline and this source electrode line are extended in this wellblock.

19. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 18, wherein the formation method of this first connector, described second connector and the 3rd connector comprises:

In this substrate, form second interlayer insulating film:

This second interlayer insulating film of patterning and this first interlayer insulating film are to form a plurality of first plug opens of exposing the described second conductivity type drain region, to expose a plurality of the 3rd plug opens that this wellblock is extended a plurality of second plug opens of conductor layer and exposed this source electrode line;

On this second interlayer insulating film, form second conductor material layer, and fill up described first plug open, described second plug open and described the 3rd plug open; And

Remove this second conductor material layer of part on this second interlayer insulating film.

20. according to the manufacture method of the bore field extension structure of the nonvolatile memory of claim 19, the formation method of wherein said bit line and described dummy bitline comprises:

On this second interlayer insulating film, form the 3rd conductor material layer;

With the 3rd conductor material layer patterning,, wherein be formed on described dummy bitline on described second connector and described the 3rd connector for opening circuit to form described bit line and described dummy bitline.

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