CN101207044A - Heat dissipation type semiconductor package and manufacturing method thereof - Google Patents
Heat dissipation type semiconductor package and manufacturing method thereof Download PDFInfo
- Publication number
- CN101207044A CN101207044A CNA2006101687435A CN200610168743A CN101207044A CN 101207044 A CN101207044 A CN 101207044A CN A2006101687435 A CNA2006101687435 A CN A2006101687435A CN 200610168743 A CN200610168743 A CN 200610168743A CN 101207044 A CN101207044 A CN 101207044A
- Authority
- CN
- China
- Prior art keywords
- fin
- packing colloid
- substrate
- semiconductor
- packer according
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 169
- 238000004519 manufacturing process Methods 0.000 title claims description 33
- 230000017525 heat dissipation Effects 0.000 title abstract description 121
- 239000000758 substrate Substances 0.000 claims abstract description 71
- 239000000084 colloidal system Substances 0.000 claims abstract description 64
- 229910052751 metal Inorganic materials 0.000 claims abstract description 53
- 239000002184 metal Substances 0.000 claims abstract description 53
- 238000005520 cutting process Methods 0.000 claims abstract description 30
- 238000009713 electroplating Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 8
- 230000002093 peripheral effect Effects 0.000 claims abstract description 6
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 29
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 claims description 23
- 229910052759 nickel Inorganic materials 0.000 claims description 18
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 239000003292 glue Substances 0.000 claims description 13
- 239000010931 gold Substances 0.000 claims description 12
- 239000011135 tin Substances 0.000 claims description 12
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 claims description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 11
- 239000011651 chromium Substances 0.000 claims description 11
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 11
- 229910052737 gold Inorganic materials 0.000 claims description 11
- 229910052763 palladium Inorganic materials 0.000 claims description 11
- 229910052718 tin Inorganic materials 0.000 claims description 11
- 229910052804 chromium Inorganic materials 0.000 claims description 10
- 229910052802 copper Inorganic materials 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 9
- 238000007772 electroless plating Methods 0.000 claims description 6
- 239000011889 copper foil Substances 0.000 claims description 5
- 239000011810 insulating material Substances 0.000 claims description 3
- 238000012856 packing Methods 0.000 claims 34
- 208000003351 Melanosis Diseases 0.000 claims 4
- 230000008021 deposition Effects 0.000 claims 4
- 238000013459 approach Methods 0.000 claims 2
- 238000004806 packaging method and process Methods 0.000 abstract description 14
- 230000005855 radiation Effects 0.000 abstract 9
- 238000002360 preparation method Methods 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 59
- 239000008393 encapsulating agent Substances 0.000 description 45
- 238000005538 encapsulation Methods 0.000 description 38
- 150000001875 compounds Chemical class 0.000 description 15
- 238000007254 oxidation reaction Methods 0.000 description 11
- 239000011241 protective layer Substances 0.000 description 11
- 230000003647 oxidation Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 7
- 239000010408 film Substances 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 229910000679 solder Inorganic materials 0.000 description 5
- 239000000969 carrier Substances 0.000 description 3
- 238000000465 moulding Methods 0.000 description 3
- SZUVGFMDDVSKSI-WIFOCOSTSA-N (1s,2s,3s,5r)-1-(carboxymethyl)-3,5-bis[(4-phenoxyphenyl)methyl-propylcarbamoyl]cyclopentane-1,2-dicarboxylic acid Chemical compound O=C([C@@H]1[C@@H]([C@](CC(O)=O)([C@H](C(=O)N(CCC)CC=2C=CC(OC=3C=CC=CC=3)=CC=2)C1)C(O)=O)C(O)=O)N(CCC)CC(C=C1)=CC=C1OC1=CC=CC=C1 SZUVGFMDDVSKSI-WIFOCOSTSA-N 0.000 description 2
- PYRKKGOKRMZEIT-UHFFFAOYSA-N 2-[6-(2-cyclopropylethoxy)-9-(2-hydroxy-2-methylpropyl)-1h-phenanthro[9,10-d]imidazol-2-yl]-5-fluorobenzene-1,3-dicarbonitrile Chemical compound C1=C2C3=CC(CC(C)(O)C)=CC=C3C=3NC(C=4C(=CC(F)=CC=4C#N)C#N)=NC=3C2=CC=C1OCCC1CC1 PYRKKGOKRMZEIT-UHFFFAOYSA-N 0.000 description 2
- 229940126543 compound 14 Drugs 0.000 description 2
- 238000001816 cooling Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- 238000007789 sealing Methods 0.000 description 2
- JQUCWIWWWKZNCS-LESHARBVSA-N C(C1=CC=CC=C1)(=O)NC=1SC[C@H]2[C@@](N1)(CO[C@H](C2)C)C=2SC=C(N2)NC(=O)C2=NC=C(C=C2)OC(F)F Chemical compound C(C1=CC=CC=C1)(=O)NC=1SC[C@H]2[C@@](N1)(CO[C@H](C2)C)C=2SC=C(N2)NC(=O)C2=NC=C(C=C2)OC(F)F JQUCWIWWWKZNCS-LESHARBVSA-N 0.000 description 1
- 241001311547 Patina Species 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- XRWSZZJLZRKHHD-WVWIJVSJSA-N asunaprevir Chemical compound O=C([C@@H]1C[C@H](CN1C(=O)[C@@H](NC(=O)OC(C)(C)C)C(C)(C)C)OC1=NC=C(C2=CC=C(Cl)C=C21)OC)N[C@]1(C(=O)NS(=O)(=O)C2CC2)C[C@H]1C=C XRWSZZJLZRKHHD-WVWIJVSJSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 229940125961 compound 24 Drugs 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000005871 repellent Substances 0.000 description 1
- 230000002940 repellent Effects 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
技术领域 technical field
本发明涉及一种半导体封装件及其制法,尤其涉及一种整合有散热结构的散热型半导体封装件及其制法。The invention relates to a semiconductor package and its manufacturing method, in particular to a heat dissipation semiconductor package integrated with a heat dissipation structure and its manufacturing method.
背景技术 Background technique
随着对电子产品轻薄短小化的要求,球栅阵列(BGA)半导体封装件(Ball Grid Array Semiconductor Package)因能提供充分数量的输入/输出连结端(I/O Connection)以符合具高密度电子元件(ElectronicComponents)及电子电路(Electronic Circuits)的半导体芯片的需求,现已逐渐成为封装产品的主流。然而,由于该种半导体封装件提供较高密度的电子电路与电子元件,故于运作时所产生的热量亦较高,若不即时将芯片表面的热量快速释除,积存的热量会严重影响半导体芯片的电性功能与产品稳定度。另一方面,为避免封装件内部电路受到外界水尘污染,半导体芯片表面必须外覆一封装胶体予以隔绝,但是构成该封装胶体的封装树脂却是一热传导性甚差的材质,其热导系数仅0.8w/m°K,所以,芯片铺设多个电路的作用表面上产生的热量无法有效藉该封装胶体传递到大气外,而往往导致热积存现象产生,使芯片性能及使用寿命备受考验。With the demand for thinner, lighter and smaller electronic products, the Ball Grid Array (BGA) Semiconductor Package (Ball Grid Array Semiconductor Package) can provide a sufficient number of input/output connections (I/O Connection) to meet the needs of high-density electronics. The demand for semiconductor chips of components (Electronic Components) and electronic circuits (Electronic Circuits) has gradually become the mainstream of packaging products. However, since this kind of semiconductor package provides higher-density electronic circuits and electronic components, it generates high heat during operation. If the heat on the surface of the chip is not released immediately, the accumulated heat will seriously affect the semiconductor. The electrical function and product stability of the chip. On the other hand, in order to prevent the internal circuit of the package from being polluted by external water and dust, the surface of the semiconductor chip must be covered with an encapsulant to insulate it. However, the encapsulation resin constituting the encapsulant is a material with poor thermal conductivity. Only 0.8w/m°K, so the heat generated on the surface of the chip laying multiple circuits cannot be effectively transferred to the outside of the atmosphere through the encapsulation gel, which often leads to heat accumulation, which puts the performance and service life of the chip to the test .
为解决现有球栅阵列半导体封装件在散热性上的不足,遂有于该BGA半导体封装件中装设散热结构的型态应运而生。In order to solve the lack of heat dissipation of the existing ball grid array semiconductor package, a type of heat dissipation structure installed in the BGA semiconductor package emerges as the times require.
参阅图1A至1C,美国专利第6,458,626号及第6,444,498号遂揭示一种直接于半导体芯片上粘置散热件的半导体封装件。Referring to FIGS. 1A to 1C , US Pat. Nos. 6,458,626 and 6,444,498 disclose a semiconductor package in which a heat sink is directly attached to a semiconductor chip.
如图1A所示,该半导体封装件乃在散热件11欲外露于大气中的表面上形成一与封装胶体14间的接合性差的介面层15,再将该散热件11直接粘置于一接置在基板13的半导体芯片10上,继而进行模压制造过程,以使封装胶体14完全包覆该散热件11及半导体芯片10,并使封装胶体14覆盖于散热件11的介面层15上;接着,进行切割作业,并将散热件11上方的封装胶体14去除,其中当形成于散热件11上的介面层15(例如为镀金层)与散热件11间的粘结性大于其与封装胶体14间的粘结性时,将封装胶体14剥除后,该介面层15仍存留于散热件11上,但因介面层15与封装胶体14间的粘结性差,封装胶体14不致残留于介面层15上(如图1B所示)。相对地,当形成于散热件11上的介面层15(例如为聚亚醯胺树脂制成的胶粘片)与散热件11间的粘结性小于其与封装胶体14间的粘结性时,将封装胶体14剥除后,该介面层15会粘附于封装胶体14上而随之去除(如图1C所示)。As shown in FIG. 1A, the semiconductor package forms an
但是于前述的半导体封装件制造过程中,在进行切割步骤时,因切割刀具直接通过该散热件,而由于该散热件一般为如铜、铝的金属材质,因此以切割刀具进行切割时,都将会使得散热件的周缘材料因拉扯产生不平整的锐角边(或称毛边)而影响封装件外观,同时亦导致切割刀具损耗太大,造成成本大幅提高,且生产效率更无法大量提高。However, in the manufacturing process of the aforementioned semiconductor package, when the cutting step is performed, because the cutting tool directly passes through the heat sink, and because the heat sink is generally made of metal materials such as copper and aluminum, when cutting with a cutting tool, it is difficult to The peripheral material of the heat sink will be pulled to produce uneven sharp-edged edges (or burrs), which will affect the appearance of the package, and will also cause too much loss of the cutting tool, resulting in a significant increase in cost, and the production efficiency cannot be greatly improved.
另外,参阅图2A至2C,中国台湾专利I255047号所揭示的散热型半导体封装件是将半导体芯片20接置并电性连接至基板23上,并将该接置有半导体芯片20的基板23定位于一预设有开口220的承载件22中,其中该基板23的平面尺寸接近于该半导体封装件的预定平面尺寸;提供一包含有散热片211及自该散热片211向下延伸支撑部212的散热结构21,并将该散热结构21藉其支撑部212而接置于该承载件22上,以将该半导体芯片20容置于该散热片211下方;进行模压制造过程,以于该基板23及承载件22上形成用以包覆该半导体芯片20及散热结构21的封装胶体24,其中,该封装胶体24所覆盖的平面尺寸大于该散热结构21支撑部所围绕的平面尺寸;以及沿该半导体封装件的预定尺寸位置进行切割作业,藉以移除该封装胶体24及散热结构21的支撑部中超过该封装件预设平面尺寸的部分。In addition, referring to FIGS. 2A to 2C, the heat dissipation semiconductor package disclosed in Taiwan Patent No. I255047 is to connect and electrically connect the
但是在前述的半导体封装件中因其散热结构未直接触碰至半导体芯片,造成热阻过多,芯片逸散的热量实为有限。However, in the aforementioned semiconductor package, because the heat dissipation structure does not directly touch the semiconductor chip, the thermal resistance is too much, and the heat dissipated by the chip is really limited.
另外,如图3A及3B所示,美国专利5,886,408揭示一种散热型半导体封装件,其将散热结构31直接置于半导体芯片30上,再进行封装模压作业,以形成包覆该散热结构31及半导体芯片30的封装胶体34,然后再研磨该封装胶体34部分,以外露出该散热结构31的一表面。In addition, as shown in FIGS. 3A and 3B , US Pat. No. 5,886,408 discloses a heat-dissipating semiconductor package, which places a heat-
然而,于前述的散热型半导体封装件中,由于经研磨后其所外露出封装胶体的散热结构材质主要为铜金属,因此,于长期曝露时易发生氧化反应而产生铜绿,除会影响外观外,更影响其散热品质。However, in the aforementioned heat-dissipating semiconductor package, since the material of the heat-dissipating structure exposed from the encapsulating colloid after grinding is mainly copper metal, it is prone to oxidation reaction to produce patina during long-term exposure, which will not only affect the appearance , but also affect its heat dissipation quality.
因此,如何有效解决半导体封装件的散热问题,同时可降低切割刀具磨损消耗、散热结构上发生溢胶、以及外露散热结构的氧化等问题,乃为业界亟须应对的一大课题。Therefore, how to effectively solve the heat dissipation problem of the semiconductor package, and at the same time reduce the wear consumption of the cutting tool, the glue overflow on the heat dissipation structure, and the oxidation of the exposed heat dissipation structure is a major issue that the industry needs to deal with urgently.
发明内容 Contents of the invention
鉴于以上所述现有技术的问题,本发明的主要目的在于提供一种散热型半导体封装件及其制法,得以避免因散热结构曝露于大气中所导致的氧化情况,甚而所产生的外观不良及散热不佳等问题。In view of the above-mentioned problems in the prior art, the main purpose of the present invention is to provide a heat dissipation semiconductor package and its manufacturing method, which can avoid the oxidation caused by the heat dissipation structure being exposed to the atmosphere, and even the resulting poor appearance and poor heat dissipation.
本发明的另一目的在于提供一种散热型半导体封装件及其制法,从而可减低制造过程中,切割刀具磨损消耗问题。Another object of the present invention is to provide a heat-dissipating semiconductor package and its manufacturing method, so as to reduce the wear and tear of cutting tools during the manufacturing process.
本发明的又一目的在于提供一种散热型半导体封装件及其制法,而得使散热结构与半导体芯片直接接触,以获得高散热性。Another object of the present invention is to provide a heat dissipation semiconductor package and its manufacturing method, so that the heat dissipation structure is in direct contact with the semiconductor chip to obtain high heat dissipation.
为达上述及其它目的,本发明揭示一种散热型半导体封装件的制法,包括:提供接置有半导体芯片的基板及表面设有导电层的承载件,其中该基板的长宽尺寸接近于半导体封装件的预定长宽尺寸,且该承载件具有至少一开口,以将该基板容置于该开口中;提供包含有散热片及自该散热片边缘向下延伸的支撑部的散热结构,以将该散热结构的支撑部接置于该承载件上并电性连接至该导电层,并使半导体芯片接着于该散热片下方;进行封装制造过程,以于该基板及承载件上形成包覆该半导体芯片及散热结构的封装胶体;研磨移除位于该散热结构的散热片上方的封装胶体,以使该散热片外露出该封装胶体;进行电镀制造过程,从而通过该承载件的导电层而于外露出该封装胶体的散热片上沉积一金属保护层;以及依半导体封装件的预定长宽尺寸进行切割作业,以制得半导体封装件。In order to achieve the above and other objects, the present invention discloses a method for manufacturing a heat-dissipating semiconductor package, which includes: providing a substrate on which a semiconductor chip is connected and a carrier with a conductive layer on the surface, wherein the length and width of the substrate are close to Predetermined length and width dimensions of the semiconductor package, and the carrier has at least one opening for accommodating the substrate in the opening; providing a heat dissipation structure comprising a heat sink and a support portion extending downward from the edge of the heat sink, The supporting portion of the heat dissipation structure is placed on the carrier and electrically connected to the conductive layer, and the semiconductor chip is then placed under the heat sink; the package manufacturing process is performed to form a package on the substrate and the carrier. Cover the semiconductor chip and the encapsulation compound of the heat dissipation structure; grind and remove the encapsulation compound located above the heat sink of the heat dissipation structure, so that the heat sink exposes the encapsulation compound; perform an electroplating manufacturing process, thereby passing through the conductive layer of the carrier Depositing a metal protective layer on the heat sink where the encapsulation colloid is exposed; and cutting according to the predetermined length and width of the semiconductor encapsulation to produce the semiconductor encapsulation.
该散热结构的散热片中心具有一凸出部,从而供研磨该封装胶体后该凸出部得外露出封装胶体,且该凸出部上表面电镀沉积有如镍、铬、锡、金或钯等的金属保护层,以防止氧化,而该散热片的其余周围部分仍埋设于封装胶体内,藉以增加该散热结构与封装胶体的附着力;该散热片的四角隅还具有与该支撑部连接的延伸部,以供后续依半导体封装件的预定长宽尺寸进行切割作业时,切割刀具仅切割至该延伸部而非整体散热片,减少刀具的耗损;该散热结构的散热片中相对于外露出封装胶体一侧的另一侧表面可通过一导热胶而直接与半导体芯片接触,从而供该半导体芯片于运作时所产生的热量得以通过该散热结构而向外逸散。The center of the heat sink of the heat dissipation structure has a protruding part, so that the protruding part can expose the encapsulating colloid after grinding the encapsulating colloid, and the upper surface of the protruding part is plated with nickel, chromium, tin, gold or palladium, etc. metal protective layer to prevent oxidation, while the remaining surrounding parts of the heat sink are still embedded in the encapsulant, so as to increase the adhesion between the heat dissipation structure and the encapsulant; the four corners of the heat sink also have a The extension part is used for subsequent cutting operations according to the predetermined length and width of the semiconductor package. The cutting tool only cuts to the extension part instead of the overall heat sink, reducing the loss of the tool; the heat sink of the heat dissipation structure is relatively exposed The other side surface of one side of the encapsulant can be directly contacted with the semiconductor chip through a thermal conductive glue, so that the heat generated by the semiconductor chip during operation can be dissipated outside through the heat dissipation structure.
本发明还揭示一种散热型半导体封装件,包括:基板;半导体芯片,接置并电性连接至该基板;散热片,间隔一导热胶而接置于半导体芯片上;封装胶体,形成于该基板上以包覆该半导体芯片并外露出该散热片的上表面:以及金属保护层,电镀沉积于外露出该封装胶体的散热片外表面上。该散热片中心具有一凸出部,该凸出部的上表面外露出封装胶体且电镀沉积有金属保护层,以防止氧化。另该散热片的四角隅还具有延伸部,该延伸部的侧边与封装胶体的侧边切齐。The present invention also discloses a heat-dissipating semiconductor package, including: a substrate; a semiconductor chip, connected to and electrically connected to the substrate; a heat sink, connected to the semiconductor chip with a gap of thermal conductive glue; and an encapsulation compound formed on the substrate. The substrate covers the semiconductor chip and exposes the upper surface of the heat sink; and the metal protection layer is electroplated and deposited on the outer surface of the heat sink exposed from the encapsulation colloid. The center of the heat sink has a protruding part, the upper surface of the protruding part exposes the encapsulation colloid and is electroplated and deposited with a metal protection layer to prevent oxidation. In addition, the four corners of the heat sink also have extensions, and the sides of the extensions are aligned with the sides of the encapsulant.
另外,于本发明的散热型半导体封装件的制法另一优选实施例,包括:提供接置有半导体芯片的基板及表面设有导电层的承载件,其中该基板的长宽尺寸接近于半导体封装件的预定长宽尺寸,且该承载件具有至少一开口,以将该基板容置于该开口中;提供包含有散热片及自该散热片边缘向下延伸的支撑部的散热结构,以将该散热结构的支撑部接置于该承载件上并电性连接至该导电层,进而使该半导体芯片接着于该散热片下方;进行封装制造过程,以于该基板及承载件上形成包覆该半导体芯片及散热结构的封装胶体;研磨移除位于该散热结构的散热片上方的封装胶体,以使该散热片外露出该封装胶体;于该封装胶体及外露出该封装胶体的散热结构外表面形成一薄金属层;进行电镀制造过程,从而通过该承载件的导电层而于该薄金属层上电镀沉积一金属保护层;以及依半导体封装件的预定长宽尺寸进行切割作业,以制得半导体封装件。In addition, another preferred embodiment of the manufacturing method of the heat-dissipating semiconductor package of the present invention includes: providing a substrate on which a semiconductor chip is connected and a carrier with a conductive layer on the surface, wherein the length and width of the substrate are close to those of the semiconductor chip. The predetermined length and width dimensions of the package, and the carrier has at least one opening, so that the substrate is accommodated in the opening; a heat dissipation structure including a heat sink and a support portion extending downward from the edge of the heat sink is provided, so as to The supporting part of the heat dissipation structure is connected to the carrier and electrically connected to the conductive layer, so that the semiconductor chip is then placed under the heat sink; the package manufacturing process is performed to form a package on the substrate and the carrier. The encapsulation compound covering the semiconductor chip and the heat dissipation structure; grinding and removing the encapsulation compound located above the heat sink of the heat dissipation structure, so that the heat sink exposes the encapsulation compound; Forming a thin metal layer on the outer surface; performing an electroplating manufacturing process, thereby electroplating and depositing a metal protection layer on the thin metal layer through the conductive layer of the carrier; and performing cutting operations according to the predetermined length and width of the semiconductor package to A semiconductor package is produced.
该散热结构的散热片中心具有一凸出部,从而供研磨该封装胶体后该凸出部得外露出封装胶体,同时于该外露凸出部及封装胶体的外表面全面覆盖有如镍、铜的薄金属层,且于该薄金属层上还电镀沉积有如镍、铬、锡、金或钯等的金属保护层,以防止散热结构氧化,而该散热片的其余周围部分仍埋设于封装胶体内,藉以增加该散热结构与封装胶体的附着力;该散热片的四角隅还具有与该支撑部连接的延伸部,以供后续依半导体封装件的预定长宽尺寸进行切割作业时,切割刀具仅切割至该延伸部而非整体散热片,减少刀具的耗损;该散热结构的散热片中相对于外露出封装胶体一侧的另一侧表面可通过一导热胶而直接接置于半导体芯片上,从而供该半导体芯片于运作时所产生的热量得以通过该散热结构而向外逸散。The center of the heat sink of the heat dissipation structure has a protruding part, so that the protruding part can expose the encapsulating colloid after grinding the encapsulating colloid, and at the same time, the exposed protruding part and the outer surface of the encapsulating colloid are fully covered with nickel, copper, etc. A thin metal layer, and a metal protective layer such as nickel, chromium, tin, gold or palladium is electroplated and deposited on the thin metal layer to prevent oxidation of the heat dissipation structure, and the rest of the heat sink is still buried in the encapsulation body , so as to increase the adhesion between the heat dissipation structure and the encapsulant; the four corners of the heat sink also have extensions connected to the support for subsequent cutting operations according to the predetermined length and width of the semiconductor package. Cutting to the extension part instead of the integral heat sink reduces the loss of tools; the surface of the heat sink of the heat dissipation structure opposite to the side exposed to the encapsulation gel can be directly connected to the semiconductor chip through a thermal conductive adhesive, Therefore, the heat generated by the semiconductor chip during operation can be dissipated outside through the heat dissipation structure.
本发明的散热型半导体封装件的另一实施例包括:基板;半导体芯片,接置并电性连接至该基板;散热片,间隔一导热胶而接置于半导体芯片上;封装胶体,形成于该基板上以包覆该半导体芯片并外露出该散热片的上表面;以及薄金属层,全面形成于该封装胶体及外露出该封装胶体的散热片的上表面;以及金属保护层,形成于该薄金属层上。该散热片中心具有一凸出部,该凸出部的上表面外露出封装胶体,另该散热片的四角隅还具有延伸部,该延伸部的侧边与封装胶体的侧边切齐。Another embodiment of the heat-dissipating semiconductor package of the present invention includes: a substrate; a semiconductor chip, connected to and electrically connected to the substrate; a heat sink, connected to the semiconductor chip with a gap between a heat-conducting adhesive; and an encapsulant formed on The substrate covers the semiconductor chip and exposes the upper surface of the heat sink; and a thin metal layer is formed on the packaging colloid and the upper surface of the heat sink exposed from the packaging colloid; and a metal protection layer is formed on the on the thin metal layer. The center of the cooling fin has a protruding part, the upper surface of the protruding part exposes the sealing compound, and the four corners of the cooling fin also have extension parts, and the side of the extending part is aligned with the side of the sealing compound.
因此,本发明的散热型半导体封装件及其制法主要是将完成接置芯片的基板容置于一承载件的开口中,且该承载件上预设有如铜箔的导电层,以将具散热片及支撑部的导电结构藉其支撑部而置于该承载件上并与该承载件的导电层电性连接,以于完成封装制造过程及去除散热片上的封装胶体而外露出散热结构时,得以利用电镀设备通电于承载件的导电层上,以于外露出该封装胶体的散热结构上电镀沉积一如镍、铬、锡、金、钯等金属保护层,以防止裸露外界的散热结构氧化,当然亦可于研磨去除散热片上的封装胶体而外露出散热结构时,先利用无电解电镀(electroless plating)方式全面于该封装胶体及外露出该封装胶体的散热结构外表面形成一如薄铜或薄镍的薄金属层,再于该薄金属层上电镀沉积一如镍、铬、锡、金、钯的金属保护层,避免裸露外界的散热结构氧化,甚而影响外观及散热效能等问题。Therefore, the heat-dissipating semiconductor package of the present invention and its manufacturing method are mainly to accommodate the substrate with the chip mounted in the opening of a carrier, and the carrier is preset with a conductive layer such as copper foil, so as to The conductive structure of the heat sink and the support part is placed on the carrier by its support part and is electrically connected with the conductive layer of the carrier, so that when the package manufacturing process is completed and the encapsulant on the heat sink is removed to expose the heat dissipation structure , so that electroplating equipment can be used to energize the conductive layer of the carrier to electroplate and deposit metal protective layers such as nickel, chromium, tin, gold, palladium, etc. on the heat dissipation structure exposed to the encapsulation colloid, so as to prevent the heat dissipation structure from being exposed to the outside world Oxidation, of course, can also be used when grinding and removing the packaging colloid on the heat sink to expose the heat dissipation structure, first use electroless plating (electroless plating) to form a thin film on the packaging colloid and the outer surface of the heat dissipation structure exposed from the packaging colloid. A thin metal layer of copper or thin nickel, and then electroplating and depositing a metal protective layer such as nickel, chromium, tin, gold, and palladium on the thin metal layer, to avoid the oxidation of the exposed heat dissipation structure, and even affect the appearance and heat dissipation performance. .
另外,本发明的该散热结构的散热片中心具有一凸出部,该凸出部的上表面外露出封装胶体,同时该散热片的其余周围部分仍埋设于封装胶体内,藉以增加该散热结构与封装胶体的附着力;该散热片的四角隅还具有与该支撑部连接的延伸部,以供后续依半导体封装件的预定长宽尺寸进行切割作业时,切割刀具仅切割至该延伸部而非整体散热片,减少刀具的耗损;该散热结构的散热片中相对于外露出封装胶体的另一侧表面可通过一导热胶而直接接置于半导体芯片上,从而供该半导体芯片于运作时所产生的热量得以通过该散热结构而向外逸散。In addition, the center of the heat dissipation fin of the heat dissipation structure of the present invention has a protruding portion, the upper surface of the protrusion exposes the encapsulation compound, while the rest of the heat dissipation fin is still buried in the encapsulation compound, so as to increase the heat dissipation structure. Adhesion to the encapsulant; the four corners of the heat sink also have an extension connected to the support, for subsequent cutting operations according to the predetermined length and width of the semiconductor package, the cutting tool only cuts to the extension and The non-integral heat sink reduces the loss of the cutting tool; the surface of the heat sink of the heat dissipation structure opposite to the exposed encapsulation gel can be directly connected to the semiconductor chip through a thermal conductive glue, so that the semiconductor chip can be used during operation. The generated heat can be dissipated outward through the heat dissipation structure.
附图说明 Description of drawings
图1A至1C为美国专利6,458,626号及第6,444,498所揭示的散热型半导体封装件示意图;1A to 1C are schematic diagrams of heat dissipation semiconductor packages disclosed in US Pat. Nos. 6,458,626 and 6,444,498;
图2A至2C为中国台湾专利I255047所揭示的散热型半导体封装件示意图;2A to 2C are schematic diagrams of heat dissipation semiconductor packages disclosed in Chinese Taiwan patent I255047;
图3A及3B为美国专利5,886,408所揭示的散热型半导体封装件示意图;3A and 3B are schematic diagrams of a heat dissipation semiconductor package disclosed in US Pat. No. 5,886,408;
图4A至4F为本发明的散热型半导体封装件及其制法第一实施例的示意图;4A to 4F are schematic diagrams of the first embodiment of the heat dissipation semiconductor package and its manufacturing method of the present invention;
图5A至5G为本发明的散热型半导体封装件及其制法第二实施例的示意图;以及5A to 5G are schematic diagrams of a second embodiment of the heat dissipation semiconductor package and its manufacturing method of the present invention; and
图6为本发明的散热型半导体封装件第三实施例的示意图。FIG. 6 is a schematic diagram of a third embodiment of a heat dissipation semiconductor package of the present invention.
主要元件符号说明Description of main component symbols
10 半导体芯片10 semiconductor chips
11 散热件11 heat sink
13 基板13 Substrate
14 封装胶体14 Encapsulation colloid
15 介面层15 interface layer
20 半导体芯片20 semiconductor chips
21 散热结构21 Heat dissipation structure
211 散热片211 heat sink
212 支撑部212 support part
22 承载件22 Carriers
220 开口220 opening
23 基板23 Substrate
24 封装胶体24 Encapsulation colloid
30 半导体芯片30 semiconductor chips
31 散热结构31 Heat dissipation structure
34 封装胶体34 Encapsulation colloid
40 半导体芯片40 semiconductor chips
41 散热结构41 Heat dissipation structure
411 散热片411 heat sink
411a 凸出部411a Protrusion
411b 延伸部411b extension
412 支撑部412 support part
42 承载件42 Carriers
420 开口420 opening
421 导电层421 conductive layer
43 基板43 Substrate
44 封装胶体44 Encapsulation colloid
45 金属保护层45 metal protective layer
46 焊球46 solder balls
47 胶片47 film
48 导电胶48 Conductive adhesive
49 导热胶49 thermal adhesive
PE 电镀设备PE electroplating equipment
50 半导体芯片50 semiconductor chips
51 散热结构51 Heat dissipation structure
511 散热片511 heat sink
511a 凸出部511a Protrusion
511b 延伸部511b extension
512 支撑部512 support part
52 承载件52 Carriers
520 开口520 opening
521 导电层521 conductive layer
53 基板53 Substrate
54 封装胶体54 encapsulation colloid
55 金属保护层55 metal protective layer
550 薄金属层550 thin metal layers
56 焊球56 solder balls
57 胶片57 film
59 导热胶59 thermal adhesive
61 散热结构61 heat dissipation structure
610 粗糙表面610 rough surface
64 封装胶体64 Encapsulation colloid
65 金属保护层65 metal protective layer
具体实施方式 Detailed ways
以下通过特定的具体实施例说明本发明的实施方式,本领域技术人员可由本说明书所揭示的内容轻易地了解本发明的其他优点与功效。Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.
第一实施例first embodiment
参阅图4A至4F,为本发明的散热型半导体封装件及其制法第一实施例的示意图。Referring to FIGS. 4A to 4F , they are schematic diagrams of a first embodiment of the heat dissipation semiconductor package and its manufacturing method of the present invention.
如图4A所示,提供基板43及承载件42,该基板43的平面尺寸接近于所欲形成的半导体封装件的预定平面尺寸,并将至少一半导体芯片40接置且电性连接至基板43上。该半导体芯片40除可以图示的覆晶方式外,亦可通过打线方式而电性连接至该基板43。As shown in FIG. 4A , a
该承载件42具有开口420且设有导电层421,该承载件开口420的平面尺寸大于该基板43的平面尺寸,以供该承载有半导体芯片40的基板43嵌合定位于该对应开口420中,同时可于该基板43与该承载件42的下表面上贴置一可封盖该承载件开口420与该基板43间的间隙的胶片(Tape)47,以同时定位该基板43并封盖该间隙。The
该胶片47可为一耐高温的高分子材料,该承载件42可为一表面或二表面附有导电层421(如铜箔)的FR4、FR5、BT等有机绝缘材料,另该承载件42的开口420可为一个或多个,以供容置一或多个承载有芯片的基板。另外,还可以多个小尺寸的胶片封盖于该基板43与该承载件42的间隙,以减省胶片材料的使用量,此外,亦可以点胶方式而于该基板43与该承载件42间的间隙中填充满一例如拒焊剂或环氧树脂等高分子材料的胶料(未图示),以同时定位该基板43并封盖该间隙。The film 47 can be a high temperature resistant polymer material, and the
如图4B及4C所示,其中该图4C为对应图4B的上视图,提供散热结构41,该散热结构41的材质如为铜金属,且其包含有散热片411及自该散热片411边缘向下延伸的支撑部412,以将该散热结构41的支撑部412接置并电性连接至该承载件42的导电层421上,并通过一导热胶49以将该散热片411接着于该半导体芯片40上,从而供该半导体芯片40于运作时所产生的热量得以直接通过该散热结构41而向外逸散,同时该散热结构41亦可通过一导电胶48以供其支撑部412接置并电性连接至该承载件42的导电层421。As shown in Figures 4B and 4C, wherein this Figure 4C is a top view corresponding to Figure 4B, a
该散热结构41的散热片411中心具有一凸出部411a,该散热片411的四角隅还具有延伸部411b,以与该支撑部412连接,且由图4C可知,该散热结构41仅是延伸部411b通过半导体封装件预定切割路径(如虚线所示),以供后续依半导体封装件的预定长宽尺寸进行切割作业时,切割刀具仅切割至该延伸部411b而非整体散热片,减少刀具的耗损。The center of the
接着,进行封装制造过程,以于该承载件42及基板43上形成包覆该半导体芯片40及散热结构41的封装胶体44。该封装胶体44所覆盖的平面尺寸大于该散热结构支撑部412所围绕的平面尺寸,且该封装胶体44的厚度大于该散热结构41的高度,以使该封装胶体44全面包覆该散热结构41,同时该封装胶体44亦可填充至该基板43与承载件开口420间的间隙中。Next, a package manufacturing process is performed to form an
如图4D所示,利用如研磨等方式移除位于该散热结构41的散热片411上方的封装胶体44,以使该散热片411外露出该封装胶体44,亦即使该散热片411中心的凸出部411a外露出封装胶体44,而该散热片411的其余周围部分仍埋设于封装胶体44内,藉以增加该散热结构41与封装胶体44的附着力。As shown in FIG. 4D , the
如图4E所示,将该完成封装作业且外露出部分散热结构的承载件42置入一电镀设备(PE,plating equipment)中进行电镀制造过程,从而通过该承载件42的导电层421及电性连接至该导电层421的散热结构41,而于外露出该封装胶体44的散热结构41外表面上电镀沉积有如镍(Ni)、铬(Cr)、锡(Sn)、金(Au)、钯(Pd)等的金属保护层45,其厚度约1至3μm,以保护外露出该封装胶体44的散热结构41部分。As shown in FIG. 4E , the
如图4F所示,移除该胶片47,并于该基板43上未设置半导体芯片40的表面上植接多个焊球46,以及沿该半导体封装件的预定尺寸(即约基板43的平面尺寸)位置进行切割作业,以制得本发明的散热型半导体封装件。As shown in FIG. 4F, the film 47 is removed, and a plurality of
通过前述的制法,本发明的散热型半导体封装件,包括:基板43;半导体芯片40,接置并电性连接至该基板43;散热片411,间隔一导热胶49而接置于半导体芯片40上;封装胶体44,形成于该基板43上以包覆该半导体芯片40并外露出该散热片411的上表面;以及金属保护层45,电镀沉积于外露出该封装胶体44的散热片411外表面上。Through the aforementioned manufacturing method, the heat dissipation semiconductor package of the present invention includes: a
该散热片411中心具有一凸出部411a,从而供研磨该封装胶体44后,该凸出部得外露出封装胶体44,以将金属保护层45电镀沉积于该外露凸出部411a的上表面以防止氧化发生,另该散热片411的四角隅还具有延伸部411b,由于该延伸部411b通过形成该半导体封装件的切割路径上,因此,该延伸部411b的侧边与封装胶体44的侧边切齐。The center of the
第二实施例second embodiment
参阅图5A至5G,为本发明的散热型半导体封装件及其制法第二实施例的剖面示意图。Referring to FIGS. 5A to 5G , they are schematic cross-sectional views of a second embodiment of the heat dissipation semiconductor package and its manufacturing method of the present invention.
如图5A所示,提供基板53及承载件52,该基板53的长宽尺寸接近于半导体封装件的预定长宽尺寸,且基板53上设置有至少一半导体芯片50,该承载件52具有开口520且设有导电层521,该开口520的长宽尺寸大于该基板53的长宽尺寸,以将该基板53容置于该开口520。As shown in Figure 5A, a
如图5B及5C所示,其中该图5C为对应图5B的上视图,提供散热结构51,该散热结构51包含有散热片511及自该散热片511向下延伸的支撑部512,以将该散热结构51的支撑部512接置并电性连接至该承载件52的导电层521上,且使该半导体芯片50通过一导热胶59而与该散热片511接着。As shown in Figures 5B and 5C, wherein Figure 5C is a top view corresponding to Figure 5B, a
该散热结构51的散热片511中心具有一凸出部511a,该散热片511的四角隅还具有延伸部511b,以与该支撑部512连接,且由图5C可知,该散热结构51仅是延伸部511b通过半导体封装件预定切割路径(如虚线所示),以供后续依半导体封装件的预定长宽尺寸进行切割作业时,切割刀具仅切割至该延伸部511b而非整体散热片,减少刀具的耗损。The center of the
接着,进行封装制造过程,以于该承载件52及基板53上形成包覆该半导体芯片50及散热结构51的封装胶体54。Next, a package manufacturing process is performed to form an
如图5D所示,利用如研磨等方式移除位于该散热结构51的散热片511上方的封装胶体54,以使该散热片511外露出该封装胶体54。亦即使该散热片511中心的凸出部511a外露出封装胶体54。As shown in FIG. 5D , the
如图5E所示,全面于该封装胶体54及外露出该封装胶体54的散热片511外表面形成一薄金属层550。该薄金属层550可以无电解电镀方式形成一厚约0.1至0.5μm的薄铜或薄镍层。As shown in FIG. 5E , a
如图5F所示,利用如前述的电镀设备及制造过程,从而通过该承载件52的导电层521及散热结构51而于该薄金属层550上电镀沉积一厚约1至3μm的如镍、铬、锡、金、钯等的金属保护层55。As shown in FIG. 5F , using the aforementioned electroplating equipment and manufacturing process, a metal layer such as nickel, nickel, etc. with a thickness of about 1 to 3 μm is electroplated and deposited on the
如图5G所示,沿半导体封装件的预定长宽尺寸进行切割作业,且植设多个焊球56,以制得散热型半导体封装件。As shown in FIG. 5G , cutting is performed along the predetermined length and width of the semiconductor package, and a plurality of
通过前述的制法,本发明的散热型半导体封装件,包括:基板53;半导体芯片50,接置并电性连接至该基板53;散热片511,间隔一导热胶59而接置于半导体芯片50上;封装胶体54,形成于该基板53上以包覆该半导体芯片50并外露出该散热片511上表面;薄金属层550,全面形成于该封装胶体54及外露出该封装胶体54的散热片511的上表面;以及金属保护层55,电镀沉积于该薄金属层550上。Through the aforementioned manufacturing method, the heat-dissipating semiconductor package of the present invention includes: a
第三实施例third embodiment
参阅图6,为本发明的散热型半导体封装件第三实施例的剖面示意图。Referring to FIG. 6 , it is a schematic cross-sectional view of a third embodiment of the heat dissipation semiconductor package of the present invention.
如图所示,本实施例的散热型半导体封装件与前述实施例大致相同,主要差异在于散热结构61的表面经黑化处理,以形成有粗糙表面610,藉以供该散热结构61与封装胶体64有良好的接着力。研磨移除该散热结构61上的封装胶体,从而供后续于外露出该封装胶体64的散热结构61部分表面电镀沉积一金属保护层65。As shown in the figure, the heat dissipation semiconductor package of this embodiment is substantially the same as the previous embodiment, the main difference is that the surface of the
因此,本发明的散热型半导体封装件及其制法主要是将完成接置芯片的基板容置于一承载件的开口中,且该承载件上预设有如铜箔的导电层,以将具支撑部的散热片藉其支撑部而置于该承载件上并与该承载件的导电层电性连接,以于完成封装制造过程及研磨去除散热片上的封装胶体而外露出散热结构时,得以利用电镀设备通电于承载件的导电层上,以于外露出该封装胶体的散热结构上电镀沉积一如镍、铬、锡、金、钯等金属保护层,以防止裸露外界的散热结构氧化,当然亦可于研磨去除散热片上的封装胶体而外露出散热结构时,先利用无电解电镀方式全面于该封装胶体及外露出该封装胶体的散热结构外表面形成一如薄铜或薄镍的薄金属层,再于该薄金属层上电镀沉积一金属保护层,避免裸露外界的散热结构氧化,甚而影响外观及散热效能等问题。Therefore, the heat-dissipating semiconductor package of the present invention and its manufacturing method are mainly to accommodate the substrate with the chip mounted in the opening of a carrier, and the carrier is preset with a conductive layer such as copper foil, so as to The heat sink of the support part is placed on the carrier by its support part and is electrically connected with the conductive layer of the carrier, so that when the package manufacturing process is completed and the packaging gel on the heat sink is removed by grinding to expose the heat dissipation structure, Electroplating equipment is used to energize the conductive layer of the carrier to electroplate and deposit metal protective layers such as nickel, chromium, tin, gold, palladium, etc. on the heat dissipation structure exposed to the encapsulation colloid to prevent oxidation of the heat dissipation structure exposed to the outside world. Of course, when the encapsulation colloid on the heat sink is removed by grinding to expose the heat dissipation structure, an electroless plating method is used to form a thin copper or thin nickel coating on the encapsulation colloid and the outer surface of the heat dissipation structure where the encapsulation colloid is exposed. A metal layer, and then a metal protection layer is electroplated and deposited on the thin metal layer to avoid the oxidation of the heat dissipation structure exposed to the outside, and even affect the appearance and heat dissipation performance.
另外,本发明的该散热结构的散热片中心具有一凸出部,从而供研磨该封装胶体后,该凸出部得外露出封装胶体,同时该散热片的其余周围部分仍埋设于封装胶体内,藉以增加该散热结构与封装胶体的附着力;该散热片的四角隅还具有与该支撑部连接的延伸部,以供后续依半导体封装件的预定长宽尺寸进行切割作业时,切割刀具仅切割至该延伸部而非整体散热片,减少刀具的耗损;该散热结构的散热片中相对于外露出封装胶体的另一侧表面可通过一导热胶而直接接置于半导体芯片上,从而供该半导体芯片于运作时所产生的热量得以通过该散热结构而向外逸散。In addition, the center of the heat sink of the heat dissipation structure of the present invention has a protruding part, so that after grinding the encapsulating compound, the protruding part can expose the encapsulating compound, while the rest of the heat sink is still embedded in the encapsulating compound. , so as to increase the adhesion between the heat dissipation structure and the encapsulant; the four corners of the heat sink also have extensions connected to the support for subsequent cutting operations according to the predetermined length and width of the semiconductor package. Cutting to the extension part instead of the integral heat sink reduces the loss of the tool; the other side surface of the heat sink of the heat dissipation structure relative to the exposed encapsulant can be directly connected to the semiconductor chip through a thermal conductive glue, so as to provide The heat generated by the semiconductor chip during operation can dissipate outside through the heat dissipation structure.
上述的实施例仅为例示性说明本发明的原理及其功效,而非用于限制本发明。任何本领域技术人员均可在不违背本发明的精神及范围下,对上述实施例进行修饰与变化。因此,本发明的权利保护范围应如随附的权利要求所列。The above-mentioned embodiments are only for illustrating the principles and effects of the present invention, but not for limiting the present invention. Any person skilled in the art can modify and change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be as listed in the appended claims.
Claims (30)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2006101687435A CN101207044A (en) | 2006-12-18 | 2006-12-18 | Heat dissipation type semiconductor package and manufacturing method thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNA2006101687435A CN101207044A (en) | 2006-12-18 | 2006-12-18 | Heat dissipation type semiconductor package and manufacturing method thereof |
Publications (1)
Publication Number | Publication Date |
---|---|
CN101207044A true CN101207044A (en) | 2008-06-25 |
Family
ID=39567115
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNA2006101687435A Pending CN101207044A (en) | 2006-12-18 | 2006-12-18 | Heat dissipation type semiconductor package and manufacturing method thereof |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN101207044A (en) |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102130571A (en) * | 2011-03-21 | 2011-07-20 | 华为技术有限公司 | A kind of power package and its device |
CN102254880A (en) * | 2010-05-21 | 2011-11-23 | 南茂科技股份有限公司 | Chip packaging device and manufacturing method thereof |
CN102368481A (en) * | 2011-10-11 | 2012-03-07 | 常熟市广大电器有限公司 | High-strength chip packaging structure |
CN105470199A (en) * | 2015-12-09 | 2016-04-06 | 华天科技(西安)有限公司 | Separation method for package part with cooling fins |
CN108133915A (en) * | 2017-12-21 | 2018-06-08 | 乐健科技(珠海)有限公司 | Power device is built-in and power modules of two-side radiation and preparation method thereof |
CN110957286A (en) * | 2019-12-04 | 2020-04-03 | 矽品科技(苏州)有限公司 | Slice disconnect-type fin subassembly |
CN114664759A (en) * | 2020-12-22 | 2022-06-24 | 华泰电子股份有限公司 | Semiconductor package and fabrication method thereof |
-
2006
- 2006-12-18 CN CNA2006101687435A patent/CN101207044A/en active Pending
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN102254880A (en) * | 2010-05-21 | 2011-11-23 | 南茂科技股份有限公司 | Chip packaging device and manufacturing method thereof |
CN102130571A (en) * | 2011-03-21 | 2011-07-20 | 华为技术有限公司 | A kind of power package and its device |
CN102368481A (en) * | 2011-10-11 | 2012-03-07 | 常熟市广大电器有限公司 | High-strength chip packaging structure |
CN105470199A (en) * | 2015-12-09 | 2016-04-06 | 华天科技(西安)有限公司 | Separation method for package part with cooling fins |
CN108133915A (en) * | 2017-12-21 | 2018-06-08 | 乐健科技(珠海)有限公司 | Power device is built-in and power modules of two-side radiation and preparation method thereof |
CN108133915B (en) * | 2017-12-21 | 2020-04-03 | 乐健科技(珠海)有限公司 | Power module with built-in power device and double-sided heat dissipation function and manufacturing method thereof |
CN110957286A (en) * | 2019-12-04 | 2020-04-03 | 矽品科技(苏州)有限公司 | Slice disconnect-type fin subassembly |
CN114664759A (en) * | 2020-12-22 | 2022-06-24 | 华泰电子股份有限公司 | Semiconductor package and fabrication method thereof |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20080122071A1 (en) | Heat dissipating semiconductor package and fabrication method therefor | |
US6534849B1 (en) | Tape having implantable conductive lands for semiconductor packaging process and method for manufacturing the same | |
CN102074516B (en) | Semiconductor element packaging and manufacturing method thereof | |
US7759170B2 (en) | Fabrication method of semiconductor package having heat dissipation device | |
CN105206592B (en) | The structure and production method of fan-out package | |
TWI249232B (en) | Heat dissipating package structure and method for fabricating the same | |
CN101101880A (en) | Heat dissipation type package structure and manufacturing method thereof | |
US10600743B2 (en) | Ultra-thin thermally enhanced electro-magnetic interference shield package | |
CN101207044A (en) | Heat dissipation type semiconductor package and manufacturing method thereof | |
WO2008059301A1 (en) | An electronic component and method for its production | |
US11488883B1 (en) | Semiconductor device package having thermally conductive layers for heat dissipation | |
TWM506373U (en) | Die packaging with fully or partially fused dielectric leads | |
US8669142B2 (en) | Method of manufacturing package structure | |
CN101877334B (en) | Semiconductor device with thermal gain | |
CN101562138B (en) | Semiconductor Package Manufacturing Method | |
US20080122070A1 (en) | Heat dissipating semiconductor package and fabrication method therefor | |
CN111180426B (en) | Packaging structure with graphene layer for heat dissipation and manufacturing method thereof | |
CN100411121C (en) | Heat dissipation type package structure and manufacturing method thereof | |
CN111180403B (en) | Packaging structure with graphene layer for heat dissipation and manufacturing method thereof | |
CN101207045A (en) | Heat dissipation type semiconductor package and manufacturing method thereof | |
CN107369663A (en) | A kind of chip of fan-out package structure for possessing front salient point and preparation method thereof | |
JP2011155120A (en) | Method for manufacturing lead frame substrate for led light-emitting device | |
CN112435969A (en) | Packaging method and packaging structure | |
CN112185908A (en) | Semiconductor packaging structure and preparation method thereof | |
KR100388287B1 (en) | back grinding method of wafer and semiconductor package thereof and its manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
WD01 | Invention patent application deemed withdrawn after publication |