CN101202690B - System structure of multi-IP modules and method for reading data of multi-IP modules - Google Patents
System structure of multi-IP modules and method for reading data of multi-IP modules Download PDFInfo
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The invention discloses a system structure with a plurality of IP modules, including a plurality of IP modules, an address bus, a data reading bus and a data writing bus. The data writing bus is accessed into a data writing port of each IP module in parallel. The IP modules are arranged in sequence. The data reading bus is connected with a data reading output port of the last IP module. A data reading input port that is neighboring to the behind IP module is connected with the data reading output port is neighboring to the front IP module. The invention also discloses a method for reading dataof a plurality of IP modules, which selects to output the data of the IP module or the data input by the front IP module according to whether the addresses of the IP modules are selected The invention avoids using a three-state data bus and realizes the operation of reading data of the IP modules; by adopting the system structure with a plurality of IP modules of the invention, the data bus doesnot adopt the three-state data bus, thus greatly reducing the technical difficulty, simplifying the system structure and reducing the power consumption of the system.
Description
Technical field
The present invention relates to a kind of system configuration of many intelligence core module, the invention still further relates to the method that a kind of many intelligence core module carries out read data.
Background technology
The designing technique of bus architecture has determined the scheme that can adopt when chip system is integrated in the microcontroller chip design, also can cause direct influence for the performance of system, it also defines the method for designing of the bus portion of corresponding peripheral IP (intelligence nuclear) module simultaneously.
At present common microcontroller nuclear all provides read-write data/address bus scheme separately, and as shown in Figure 1, wherein read data bus and write data bus all are to be connected in parallel to each intelligence core module.Owing to circuit such as declare based on all having comprised the address for writing of register in each intelligence core module of this design, so it is all comparatively unified that the partial circuit that data are write is realized, but read function realize in owing to there are a plurality of IP can supply with the processor core data, the selection problem of the method that a bus articulates is just arranged this moment.Common way is to adopt inner tristate bus line to realize the read operation of data, the read port that does not carry out the intelligence core module of data read is set to high-impedance state, prevent from the intelligence core module of other work is exerted an influence, each intelligence core module just can directly be articulated on the read bus of same processor like this.As shown in Figure 1, in order to realize the operation of tristate bus line read data, also need adjunct circuits such as total wire maintainer in the system state of tristate bus line is controlled.
Although this method can effectively solve the bus collision problem when articulating a plurality of IP, owing to used tristate bus line can bring following shortcoming: one, the essential bus of using keeps technology; Its two, use tristate bus line can cause the whole system power consumption to increase.
Summary of the invention
Technical problem to be solved by this invention is, a kind of system configuration of many intelligence core module is provided, can avoid using ternary data/address bus, and the structure of simplified system, reduce system power dissipation.
For solving the problems of the technologies described above, the technical scheme of the system configuration of many intelligence of the present invention core module is, comprise a plurality of intelligence core modules, address bus, read data bus and write data bus, described each intelligence core module respectively includes the data write port, data read input port and data are read output port, the write data bus parallel connection inserts the data write port of each intelligence core module, described each intelligence core module is arranged in order in order and is IP1, IP2 is up to IPn, described read data bus is connected to the data of last intelligence core module IPn and reads output port, in all intelligence core modules after the ordering, the data of an adjacent back intelligence core module are read input port and are read output port with the data of previous intelligence core module and be connected, include selector in the described intelligence core module, data of selecting input to connect this intelligence core module of described selector are read input port, another of described selector selects input to connect the data output end of this intelligence core module, the output of described selector connects the data of this intelligence core module and reads output port, and the control end of described selector connects the address decoding circuitry of this intelligence core module.
Another technical problem to be solved by this invention is, the method for the read data that a kind of system configuration of utilizing above-mentioned many intelligence core module realizes is provided, and can not use ternary data/address bus that data are read, and reduces system power dissipation.
For solving the problems of the technologies described above, the technical scheme of the method for many intelligence of the present invention core module read data is to comprise the steps:
(1) by address bus will reading of data the address send to each intelligence core module;
(2) each intelligence core module carries out address decoding, and the address decoding circuitry of the intelligence core module corresponding with this address is according to this address, and the selector of controlling this corresponding intelligence core module is selected the data of intelligence core module that should correspondence to export to data and read output port; With the address decoding circuitry of the not corresponding intelligence core module in this address according to this address, the data that the selector of controlling this not corresponding intelligence core module selects the intelligence core module that this is not corresponding to read the input port input from data are exported to data and are read output port.
The present invention avoids using tristate bus line by the method for above-mentioned many intelligence core module read data, has realized the operation of intelligence core module read data; And the system configuration of many intelligence of the present invention core module, its data/address bus does not adopt ternary data/address bus yet, greatly reduces technical difficulty, has simplified system configuration, has reduced system power dissipation.
Description of drawings
The present invention is further detailed explanation below in conjunction with drawings and Examples:
Fig. 1 is the schematic diagram of the system configuration of existing many intelligence core module;
Fig. 2 is the schematic diagram of the system configuration of many intelligence of the present invention core module;
Fig. 3 is the structural representation that each intelligence core module inner port connects.
Embodiment
The system configuration of many intelligence of the present invention core module can be referring to Fig. 2 and shown in Figure 3, comprise a plurality of intelligence core modules, address bus, read data bus and write data bus, described each intelligence core module respectively includes the data write port, data read input port and data are read output port, the write data bus parallel connection inserts the data write port of each intelligence core module, described each intelligence core module is arranged in order in order and is IP1, IP2 is up to IPn, described read data bus is connected to the data of last intelligence core module IPn and reads output port, in all intelligence core modules after the ordering, the data of an adjacent back intelligence core module are read input port and are read output port with the data of previous intelligence core module and be connected.For example, the data of IP1 are read the data that output port is connected to IP2 and are read input port, and the data of IP2 are read the data that output port is connected to IP3 and read input port.
Include selector in the described intelligence core module, data of selecting input to connect this intelligence core module of described selector are read input port, another of described selector selects input to connect the data output end of this intelligence core module, the output of described selector connects the data of this intelligence core module and reads output port, and the control end of described selector connects the address decoding circuitry of this intelligence core module.After the address of this intelligence core module was selected, address decoding circuitry can be controlled selector input is switched to the data output end of this intelligence core module, with the output output from selector of the data of this intelligence core module; When the address of this intelligence core module does not have when selected, address decoding circuitry can be controlled selector the data that input switches to this intelligence core module are read input port, data is read the data output of input port.
In the described intelligence core module that respectively is arranged in order, the higher intelligence core module of reading of data frequency is arranged in the position than the back, and the intelligence core module that the reading of data frequency is lower is arranged in the position than the front.
The present invention also provides a kind of system configuration of utilizing above-mentioned many intelligence core module to carry out the method for read data, comprises the steps: at first to send to each intelligence core module by the address that address bus will reading of data; Each intelligence core module carries out address decoding then, and the address decoding circuitry of the intelligence core module corresponding with this address is according to this address, and the selector of controlling this corresponding intelligence core module is selected the data of intelligence core module that should correspondence to export to data and read output port; With the address decoding circuitry of the not corresponding intelligence core module in this address according to this address, the data that the selector of controlling this not corresponding intelligence core module selects the intelligence core module that this is not corresponding to read the input port input from data are exported to data and are read output port.
Before the data address that described address bus transmission is read, also comprise the step that each intelligence core module is sorted.
When each intelligence core module was sorted, the higher intelligence core module of reading of data frequency was arranged in the position than the back, and the intelligence core module that the reading of data frequency is lower is arranged in the position than the front.
This ordering can be dynamic.When system carries out different work, the frequency of the intelligence core module that calls also may be different, therefore in the time of can carrying out different work according to system, putting in order of intelligence core module changed, make the high intelligence core module of frequency of utilization come position than the back, the intelligence core module that frequency of utilization is few comes the position than the front.
The present invention is by the system configuration of above-mentioned many intelligence core module and the method for many intelligence core module read data, a plurality of intelligence core modules in the system are connected in series, after the address of some intelligence core modules is selected, each intelligence core module of this intelligence core module back be connected to form a path, the data output of the intelligence core module that this is selected, avoided the use of tristate bus line like this, realized the operation of many intelligence core module read data, the adjunct circuits such as total wire maintainer that are used for controlling tristate bus line have also been omitted, greatly reduce technical difficulty, simplify system configuration, reduced system power dissipation.
Claims (6)
1. the system configuration of intelligence core module more than a kind, it is characterized in that, comprise a plurality of intelligence core modules, address bus, read data bus and write data bus, described each intelligence core module respectively includes the data write port, data read input port and data are read output port, the write data bus parallel connection inserts the data write port of each intelligence core module, described each intelligence core module is arranged in order in order and is IP1, IP2 is up to IPn, described read data bus is connected to the data of last intelligence core module IPn and reads output port, in all intelligence core modules after the ordering, the data of an adjacent back intelligence core module are read input port and are read output port with the data of previous intelligence core module and be connected, include selector in the described intelligence core module, data of selecting input to connect this intelligence core module of described selector are read input port, another of described selector selects input to connect the data output end of this intelligence core module, the output of described selector connects the data of this intelligence core module and reads output port, and the control end of described selector connects the address decoding circuitry of this intelligence core module.
2. the system configuration of many intelligence core module according to claim 1, it is characterized in that, in the described intelligence core module that respectively is arranged in order, the higher intelligence core module of reading of data frequency is arranged in the position than the back, and the intelligence core module that the reading of data frequency is lower is arranged in the position than the front.
3. the system configuration of any described many intelligence core module is carried out the method for read data in a utilization such as claim 1 or 2, it is characterized in that, comprises the steps:
(1) by address bus will reading of data the address send to each intelligence core module;
(2) each intelligence core module carries out address decoding, and the address decoding circuitry of the intelligence core module corresponding with this address is according to this address, and the selector of controlling this corresponding intelligence core module is selected the data of intelligence core module that should correspondence to export to data and read output port; With the address decoding circuitry of the not corresponding intelligence core module in this address according to this address, the data that the selector of controlling this not corresponding intelligence core module selects the intelligence core module that this is not corresponding to read the input port input from data are exported to data and are read output port.
4. the method for many intelligence core module read data according to claim 3 is characterized in that, also comprises the step that each intelligence core module is sorted before described (1) step.
5. the method for many intelligence core module read data according to claim 4, it is characterized in that, when each intelligence core module was sorted, the higher intelligence core module of reading of data frequency was arranged in the position than the back, and the intelligence core module that the reading of data frequency is lower is arranged in the position than the front.
6. the method for many intelligence core module read data according to claim 4 is characterized in that, each intelligence core module is carried out dynamic order.
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| CN101639692B (en) * | 2009-08-31 | 2011-11-16 | 杭州华三通信技术有限公司 | Method, equipment and system for controlling a plurality of programmable logical components |
| CN110493038B (en) * | 2019-08-01 | 2021-10-01 | 苏州浪潮智能科技有限公司 | A communication model optimization method and device |
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| CN1614580A (en) * | 2004-11-26 | 2005-05-11 | 上海广电（集团）有限公司中央研究院 | Low-speed bus structure and its data transmission |
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| CN1556476A (en) * | 2003-12-30 | 2004-12-22 | 中兴通讯股份有限公司 | Method of realizing conversion between PCI bus and CPU bus |
| CN1614580A (en) * | 2004-11-26 | 2005-05-11 | 上海广电（集团）有限公司中央研究院 | Low-speed bus structure and its data transmission |
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| 郭腊梅，胡越黎.一种微控制器总线结构的设计.计算机测量与控制 2005年第7期.2005,(2005年第7期),715-717. |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Patentee after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Patentee before: Shanghai Huahong NEC Electronics Co., Ltd. |