CN101202259B - Chip stack packaging structure, embedded chip packaging structure and manufacturing method thereof - Google Patents

Abstract

An embedded chip package structure includes a substrate, a semiconductor structure, a sealing material layer, and a plurality of via holes. The substrate comprises at least one dielectric layer and at least one patterned circuit layer arranged on the dielectric layer. The semiconductor structure is arranged on the substrate, and the semiconductor structure is provided with a plurality of electric connecting pads which are in contact with the dielectric layer. The sealing material layer is disposed on the substrate around the semiconductor structure. In addition, a plurality of via holes are arranged in the substrate, so that the patterned circuit layer is electrically connected with the electric connecting pads.

Description

Chip stack package structure, embedded chip package structure and manufacturing method thereof

technical field

The invention relates to a chip packaging structure and a manufacturing method thereof, and in particular to a chip stack packaging structure, an embedded chip packaging structure and a manufacturing method thereof.

Background technique

In the semiconductor industry, the purpose of chip packaging is to prevent the bare chip from being affected by moisture, heat and noise, and to provide a medium for electrical connection between the bare chip and external circuits. In recent years, with the rapid development of electronic technology and the continuous integration and innovation of high-tech electronic products, traditional semiconductor packaging technology has been unable to meet product function and cost requirements. At present, semiconductor packaging technology has moved towards the trend of integrating chips into circuit substrates, so that the entire packaging area/volume can be greatly reduced to meet the needs of light, thin, short, high-function, high-speed and high-density electronic products.

The main manufacturing process of the existing chip-embedded packaging technology is that the chip is first loaded on the substrate, and then the chip is buried therein by using a dielectric material. Generally speaking, the dielectric material can be formed on the chip by spin coating, printing or pressing, but this method may easily cause the surface of the dielectric material to be uneven, which will affect the subsequent process. In particular, for a thicker chip, the thickness difference between the chip and the substrate often results in poor uniformity of the surface of the dielectric material, which affects the yield of the process. Therefore, it is usually necessary to use a grinding method to thin the chip before performing the chip embedded packaging process, or to use more dielectric materials to improve the uniformity. However, the grinding step will increase the manufacturing cost and easily cause chip damage, and the method of coating more dielectric materials will also increase the manufacturing cost.

With regard to chip embedded packaging technology, the industry also proposes various methods. For example, Freescale Semiconductor, Inc. has proposed a related semiconductor packaging technology about chip embedded packaging. In addition, U.S. Patent Application Publication No. 6759270 (US6759270) is titled "Semiconductor chip module and method of manufacture of same", which discloses that first a cavity is made in the substrate as a chip embedding area, and then the chip is Place it in the groove, and then carry out processes such as dielectric material coating, metal circuit forming and pad production in order to complete the chip embedded package. However, the method of this patent requires additional filling materials to fill the gap between the chip and the substrate, and there are problems that the substrate still occupies the main package thickness and the depth of the groove is not easy to control.

In addition, U.S. Patent Application Publication No. 6469374 (US 6469374) is titled "Superposed printed substrates and insulating substrates having semiconductor elements inside", which uses the method of stacking multiple hollow substrates to form grooves for embedding chips, so as to Carry out chip embedded packaging process. The method of this patent still has the problems that the substrate occupies the main package thickness, additional filling material is required to fill the gap between the chip and the substrate, and the alignment between the substrates.

Therefore, how to embed the chip in the circuit substrate and avoid various problems caused by the existing chip packaging technology has become a key technology at present.

Contents of the invention

The invention provides a chip stack packaging structure, an embedded chip packaging structure and a manufacturing method thereof, which can avoid various problems of the existing packaging, and can be compatible with the existing technology, simplify the technology and save the technology cost.

The invention proposes an embedded chip packaging structure, which includes a substrate, a semiconductor chip, a sealing material layer and a plurality of via holes. Wherein, the substrate includes at least one dielectric layer and at least one patterned circuit layer disposed on the dielectric layer. The semiconductor chip is disposed on the substrate, the semiconductor chip has a plurality of first electrical pads, and the first electrical pads are in contact with the dielectric layer. The sealing material layer is arranged on the substrate around the semiconductor chip. In addition, the aforementioned plurality of via holes are disposed in the substrate, so that the patterned circuit layer is electrically connected to the first electrical pads.

Based on the above, the material of the sealing material layer is, for example, molding compound or potting compound. The semiconductor chip is a semiconductor chip with first electrical pads. In addition, a metal layer may also be disposed on the semiconductor chip, and the first electrical pad is located on the semiconductor chip. In addition, the semiconductor chip may also be composed of a first semiconductor chip and a second semiconductor chip, and a connection layer is further provided between the first semiconductor chip and the second semiconductor chip. Wherein, the first semiconductor chip has a first electrical pad. The connection layer is disposed on the first semiconductor chip, and it can be an adhesive layer or a metal layer. The second semiconductor chip is disposed on the connection layer, the upper surface of the second semiconductor chip has a plurality of second electrical pads, and the lower surface of the second semiconductor chip is in contact with the connection layer.

The present invention further provides an embedded chip packaging structure, which includes a first substrate, a semiconductor chip, a sealing material layer, a plurality of first via holes, a second substrate, and a plurality of second via holes. Wherein, the first substrate includes at least one first dielectric layer and at least one first patterned circuit layer disposed on the first dielectric layer. The semiconductor chip is disposed on the first substrate, and the semiconductor chip has a plurality of first electrical pads, and the first electrical pads are in contact with the first dielectric layer. The sealing material layer is disposed on the first substrate around the semiconductor chip. A plurality of first via holes are disposed in the first substrate to electrically connect the first patterned circuit layer to the first electrical pad. The second substrate includes at least one second dielectric layer and at least one second patterned circuit pattern disposed on the second dielectric layer, the second substrate is disposed on the semiconductor chip and the sealing material layer, and the second dielectric layer contact with the semiconductor chip. A plurality of second via holes are disposed in the first substrate, the sealing material layer and the second substrate, so that the first patterned circuit layer is electrically connected to the second patterned circuit layer.

Based on the above, the material of the sealing material layer is, for example, molding compound or potting compound. Moreover, the sealing material layer further includes being disposed on the semiconductor chip. The aforementioned semiconductor chip is a semiconductor chip with a first electrical pad. In addition, a metal layer may also be provided on the semiconductor chip, and the first electrical pad is located on the semiconductor chip. In addition, the semiconductor chip may also be composed of a first semiconductor chip and a second semiconductor chip, and a connection layer is further provided between the first semiconductor chip and the second semiconductor chip. Wherein, the first semiconductor chip has these first electrical pads. The connection layer is disposed on the first semiconductor chip, and it can be an adhesive layer or a metal layer. The second semiconductor chip is disposed on the connection layer, and the upper surface of the second semiconductor chip has a plurality of second electrical pads, and the lower surface of the second semiconductor chip is in contact with the connection layer.

The embedded chip packaging structure according to an embodiment of the present invention further includes a plurality of third via holes for electrically connecting the second patterned circuit layer to the second electrical pad.

The present invention further proposes a chip stack packaging structure. The chip stack package structure includes a carrier component and at least one chip package structure. Wherein, the carrying component is one of the above-mentioned embedded chip packaging structures of the double-sided substrate. The above-mentioned chip package structure is arranged on the carrier component and is electrically connected with the carrier component. The chip package structure is an embedded chip package structure selected from the above-mentioned single-sided substrate. Moreover, the carrying component and the chip packaging structure can be electrically connected by means of bonding wires or metal bumps.

The invention further proposes a method for manufacturing an embedded chip packaging structure. The method is to form a semiconductor chip on a carrier board, wherein a plurality of first electrical pads have been formed on the semiconductor chip, and the first electrical pads are in contact with the carrier board. Then, a sealing material layer is formed on the carrier around the semiconductor chip. Afterwards, the carrier board is removed, and then a first substrate is formed on the sealing material layer and the semiconductor chip. Wherein, the first substrate includes at least one first dielectric layer and at least one first patterned circuit layer formed on the first dielectric layer, and the first dielectric layer is in contact with the semiconductor chip. Subsequently, a plurality of first via holes are formed in the first substrate, so that the first patterned circuit layer is electrically connected to the first electrical pad.

The method for forming the sealing material layer on the carrier around the semiconductor chip is, for example, performing a compression molding step or a potting filling step. Based on the above, the material of the sealing material layer is, for example, molding compound or potting compound. The semiconductor chip is a semiconductor chip with first electrical pads. In addition, a metal layer may also be provided on the semiconductor chip, and the first electrical pad is located on the semiconductor chip. In addition, the semiconductor chip may also be composed of a first semiconductor chip and a second semiconductor chip, and a connection layer is further provided between the first semiconductor chip and the second semiconductor chip. Wherein, the first semiconductor chip has these first electrical pads. The connection layer is formed on the first semiconductor chip, which can be an adhesive layer or a metal layer. The second semiconductor chip is formed on the connection layer, and the upper surface of the second semiconductor chip has a plurality of second electrical pads, and the lower surface of the second semiconductor chip is in contact with the connection layer.

In addition, before forming the first via hole in the first substrate, it further includes forming a second substrate on the sealing material layer and the semiconductor chip. Wherein, the second substrate includes at least one second dielectric layer and at least one second patterned circuit layer formed on the second dielectric layer, and the second dielectric layer is in contact with the semiconductor chip. In addition, it further includes forming a plurality of second via holes in the first substrate, the second substrate and the sealing material layer, so that the first patterned circuit layer is electrically connected to the second patterned circuit layer. Also, the sealing material layer is further formed between the semiconductor chip and the second substrate. According to the above, the semiconductor chip is a semiconductor chip with the first electrical pads. A metal layer may also be provided on the semiconductor chip, and the first electrical pad is located on the semiconductor chip. In addition, the semiconductor chip may also include a first semiconductor chip and a second semiconductor chip, and a connection layer is further provided between the first semiconductor chip and the second semiconductor chip. Wherein, the first semiconductor chip has a first electrical pad, and the connection layer is formed on the first semiconductor chip, which can be an adhesive layer or a metal layer. The second semiconductor chip is formed on the connection layer, the upper surface of the second semiconductor chip has a plurality of second electrical pads, and the lower surface of the second semiconductor chip is in contact with the connection layer. In the above embodiment, it further includes forming a plurality of third via holes in the second substrate, so that the second patterned circuit layer is electrically connected to the second electrical pad.

The invention further proposes a method for manufacturing an embedded chip packaging structure. The method is to form a first substrate on a carrier, wherein the first substrate includes at least one first dielectric layer and at least one first patterned circuit layer formed on the first dielectric layer, and the first patterned circuit layer layer is in contact with the carrier. Then, a semiconductor chip is formed on the first substrate, wherein a plurality of first electrical pads have been formed on the semiconductor chip, and these first electrical pads are in contact with the first substrate. Next, a sealing material layer is formed on the first substrate around the semiconductor chip. Subsequently, the carrier board is removed, and then a plurality of first via holes are formed in the first substrate, so that the first patterned circuit layer is electrically connected to the first electrical pads.

The above-mentioned method of forming a sealing material layer on the first substrate around the semiconductor chip is, for example, performing a compression molding step or a potting filling step. The material of the sealing material layer is, for example, molding compound or potting compound. The semiconductor chip is a semiconductor chip with first electrical pads. A metal layer may also be provided on the semiconductor chip, and the first electrical pad is located on the semiconductor chip. In addition, the semiconductor chip includes a first semiconductor chip and a second semiconductor chip, and a connection layer is further provided between the first semiconductor chip and the second semiconductor chip. Wherein, the first semiconductor chip has these first electrical pads. The connection layer is formed on the first semiconductor chip, which can be an adhesive layer or a metal layer. The second semiconductor chip is formed on the connection layer, and the upper surface of the second semiconductor chip has a plurality of second electrical pads, and the lower surface of the second semiconductor chip is in contact with the connection layer.

In addition, before forming the first via hole in the first substrate, it further includes forming a second substrate on the sealing material layer and the semiconductor chip. Wherein, the second substrate includes at least one second dielectric layer and at least one second patterned circuit layer formed on the second dielectric layer, and the second dielectric layer is in contact with the semiconductor chip. In addition, it further includes forming a plurality of second via holes in the first substrate, the second substrate and the sealing material layer, so that the first patterned circuit layer is electrically connected to the second patterned circuit layer. Also, the sealing material layer is further formed between the semiconductor chip and the second substrate. According to the above, the semiconductor chip is a semiconductor chip with the first electrical pads. A metal layer may also be provided on the semiconductor chip, and the first electrical pad is located on the semiconductor chip. In addition, the semiconductor chip may also include a first semiconductor chip and a second semiconductor chip, and a connection layer is further provided between the first semiconductor chip and the second semiconductor chip. Wherein, the first semiconductor chip has a first electrical pad, and the connection layer is formed on the first semiconductor chip, which can be an adhesive layer or a metal layer. The second semiconductor chip is formed on the connection layer, the upper surface of the second semiconductor chip has a plurality of second electrical pads, and the lower surface of the second semiconductor chip is in contact with the connection layer. In the above embodiment, it further includes forming a plurality of third via holes in the second substrate, so that the second patterned circuit layer is electrically connected to the second electrical pad.

The structure of the present invention replaces the core layer (core layer) of the substrate in the existing packaging structure with the sealing material layer, so various existing problems can be avoided. The sealing material layer can be used to support the wiring layer of the semiconductor chip and the package body, and can achieve the purpose of protecting the semiconductor chip and the package body. Moreover, the sealing material layer of the present invention can be selected to have a thermal expansion coefficient similar to that of the semiconductor chip, or a material with stress buffering, so as to reduce the stress caused by the difference in thermal expansion between the two. In addition, the structure of the present invention also includes a metal layer, so it can help the entire packaging structure to dissipate heat, and can reduce the electromagnetic interference between the outside world or the embedded stacked chips. Moreover, compared with the prior art, the structure of the present invention can increase the number of chips in the embedded chip packaging structure, and can improve the efficiency of the components. On the other hand, the structure of the present invention enables the embedded chip packaging structure to have double-sided contacts, and this structure can be used as a carrier required for stack packaging. The method of the present invention can replace the existing groove process, and the method of the present invention is compatible with the existing process, and can simplify the process, thus saving process cost.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with accompanying drawings.

Description of drawings

Figure 1, Figure 2(a)-2(c), Figure 3(a)-3(b), Figure 4, Figure 5(a)-5(b), Figure 6(a)-6(b), 7 , FIGS. 8( a ) to 8 ( b ) and FIGS. 9 ( a ) to 9 ( b ) are schematic cross-sectional views of embedded chip packaging structures according to Embodiments 1 to 9 of the present invention.

10A to 10D are schematic cross-sectional views of a chip stack package structure according to an embodiment of the present invention.

11A to 11D are cross-sectional views of a manufacturing method of the embedded chip packaging structure according to Embodiments 1-3 of the present invention.

12A to 12D are cross-sectional views of a manufacturing method of an embedded chip package structure according to Embodiments 4-6 of the present invention.

13A to 13D are cross-sectional views of a manufacturing method of an embedded chip package structure according to Embodiments 7-9 of the present invention.

14A to 14D are cross-sectional views of another manufacturing method of the embedded chip packaging structure shown in Embodiments 1-3 of the present invention.

15A to 15D are cross-sectional views of another manufacturing method of the embedded chip packaging structure shown in Embodiments 4-6 of the present invention.

16A to 16D are cross-sectional views of another manufacturing method of the embedded chip packaging structure shown in Embodiments 7-9 of the present invention.

Explanation of reference signs

102, 202, 302, 412, 422: dielectric layer

103, 203, 303, 414, 424: patterned circuit layer

104, 204, 304, 410, 420: substrate

106, 106a, 408, 408a: sealing material layer

108, 107, 109, 416, 426: via holes

110, 120, 130, 140, 150, 160, 170, 180, 190: Embedded chip package structure

200, 402: Semiconductor Structure

202, 210, 406: electrical pads

204, 208, 404: semiconductor chips

206a, 206b, 206c: metal layer

207: Connection layer

400: carrier board

Detailed ways

Hereinafter, the embodiment 1 to the embodiment 9 are specifically cited to describe the embedded chip packaging structure of the present invention in detail. The same components in Embodiment 1 to Embodiment 9 are given the same reference numerals, and possible overlapping descriptions are omitted.

Fig. 1, Fig. 2(a) ~ 2(c) and Fig. 3(a) ~ 3(b) are schematic diagrams showing the structures of Embodiments 1 ~ 3 respectively, all of which show the embedded type with a single-sided substrate. Chip package structure.

Please refer to FIG. 1 , which is a schematic cross-sectional view of an embedded chip packaging structure according to Embodiment 1 of the present invention. The embedded chip packaging structure 110 of this embodiment is mainly composed of a substrate 104 , a semiconductor structure 200 , a sealing material layer 106 and a plurality of via holes 108 .

Wherein, the substrate 104 is mainly composed of a dielectric layer 102 and a patterned circuit layer 103 disposed on the dielectric layer 102 . The material of the dielectric layer 102 is, for example, polyimide (polyimide, PI), glass epoxy resin (FR-4, FR-5), bismaleimide-triazine (BT), Epoxy resin or other suitable dielectric material. The material of the patterned circuit layer 103 is, for example, a conductive material, which can be, for example, copper foil. The semiconductor structure 200 is disposed on the substrate 104 . There are a plurality of electrical pads 202 on the semiconductor structure 200 , and the electrical pads 202 are in contact with the dielectric layer 102 . The material of the electrical pad 202 can be, for example, aluminum, copper, nickel/gold or other conductive materials. In this embodiment, the semiconductor structure 200 is formed by disposing electrical pads 202 on a semiconductor chip 204 , such as a silicon chip. In addition, a plurality of via holes 108 are disposed in the substrate 104 to electrically connect the patterned circuit layer 103 to the electrical pad 202 . The material of the via hole 108 is, for example, a conductive material such as copper, silver, tin-lead alloy or other suitable materials.

In addition, the embedded chip packaging structure 110 further includes a sealing material layer 106 disposed on the substrate 104 around the semiconductor structure 200 . The material of the sealing material layer 106 is, for example, a molding compound or a potting compound, such as epoxy resin, a polymer material containing silica, or other suitable molding compound. In particular, the sealing material layer 106 is used to support and protect the semiconductor chip. On the other hand, since the materials of the sealing material layer 106 and the semiconductor chip 204 have similar coefficients of thermal expansion (CTE), the stress caused by the difference in thermal expansion between the sealing material layer 106 and the semiconductor chip 204 can be reduced. Based on the above, the encapsulation material layer 106 can only be disposed around the semiconductor structure 200 , instead of covering the entire assembly like conventional encapsulation materials. Especially, for semiconductor chips that are not ground to make the thickness thinner or higher, the structure of the present invention does not need to use the existing groove process when performing the packaging step, so the process cost can be saved, and the process can be simplified. craft.

Please refer to FIGS. 2( a ) to 2 ( c ), which are schematic cross-sectional views of an embedded chip packaging structure according to Embodiment 2 of the present invention. The embedded chip packaging structure 120 of this embodiment is similar to the embedded chip packaging structure 110 of the above embodiment, but the main difference between the two is that the semiconductor structure 200 of the embedded chip packaging structure 120 may further include a metal layer 206a , 206b, 206c, which are disposed on the semiconductor chip 204. As shown in the sub-figure (a) of Figure 2, the metal layer 206a is only located on the semiconductor chip 204; On the layer 106; as shown in sub-figure (c) of FIG. The material of the metal layers 206a, 206b, 206c is, for example, copper, aluminum or other suitable metal materials. The metal layers 206a, 206b, 206c can be used to help the heat dissipation of the entire package structure, and can reduce the electromagnetic interference (EMI) between the outside world or between embedded stacked chips.

Please refer to FIGS. 3( a ) to 3 ( b ), which are schematic cross-sectional views of an embedded chip packaging structure according to Embodiment 3 of the present invention. The embedded chip packaging structure 130 of this embodiment is similar to the embedded chip packaging structure 110 , but the main difference is that the semiconductor structure 200 of the embedded chip packaging structure 130 can further include a semiconductor chip 208 and a connection layer 207 . Wherein, the semiconductor chip 208 is disposed above the semiconductor chip 204 , and the upper surface of the semiconductor chip 208 has a plurality of electrical pads 210 , and the lower surface of the semiconductor chip 208 is in contact with the connection layer 207 . The material of the electrical contact pad 210 can be, for example, aluminum, copper, nickel/gold or other conductive materials. In addition, the connection layer 207 is disposed between the semiconductor chip 204 and the semiconductor chip 208 , which is an adhesive layer or a metal layer. If the connecting layer 207 is an adhesive layer connecting the semiconductor chips 204 and 208 , its structure can be as shown in sub-figure (a) of FIG. 3 . If the connection layer 207 is a metal layer that helps the entire package structure to dissipate heat, its structure can be as shown in sub-figure (a) and sub-figure (b) of FIG. 3 . In this embodiment, the semiconductor structure 200 includes a semiconductor chip 204 and a semiconductor chip 208, that is, two chips are embedded in the embedded chip packaging structure 130, so the number of chips in the embedded chip packaging structure can be increased. , and can improve component performance.

In addition to the above-mentioned embodiments, the present invention also has other implementation forms. Figure 4, Figure 5(a)-5(b), Figure 6(a)-6(b), Figure 7, Figure 8(a)-8(b) and Figure 9(a)-9(b) respectively It is a schematic diagram illustrating the structures of embodiments 4-9, all of which illustrate the embedded chip packaging structure with double-sided substrates.

Please refer to Figure 4, Figures 5(a)-5(b) and Figures 6(a)-6(b), the embedded chip packaging structures 140, 150, 160 of this embodiment are respectively connected 110 , 120 , 130 are similar, but the main difference is: the embedded chip packaging structures 140 , 150 , 160 may further include a substrate 304 . Wherein, the substrate 304 is mainly composed of a dielectric layer 302 and a patterned circuit layer 303 disposed on the dielectric layer 302 . The substrate 304 is disposed on the semiconductor structure 200 and the sealing material layer 106 , and the dielectric layer 302 is in contact with the semiconductor structure 200 . As mentioned above, the material of the dielectric layer 302 is, for example, polyimide, glass epoxy resin, bismaleimide, epoxy resin or other suitable dielectric materials. The material of the patterned circuit layer 303 is, for example, a conductive material, which may be, for example, copper foil. In addition, the embedded chip packaging structure 140, 150, 160 may include a via hole 109, which is disposed in the substrate 304, the sealing material layer 106 and the substrate 104, so that the patterned circuit layer 303 is electrically connected to the patterned circuit layer. Line layer 103. As mentioned above, the material of the via hole 109 is, for example, a conductive material, such as copper, silver, tin-lead alloy or other suitable materials. In addition, please refer to FIGS. 6(a) to 6(b) again, the embedded chip package structure 160 may further include a via hole 107, which is disposed in the substrate 204, so that the patterned circuit layer 303 is electrically connected. Electrical pads 210 . The material of the via hole 107 is, for example, a conductive material such as copper, silver, tin-lead alloy or other suitable materials.

In addition, please refer to Figures 7, 8(a)-8(b) and Figures 9(a)-9(b), the embedded chip packaging structures 170, 180, 190 of this embodiment are respectively connected to the embedded chip package The structures 140 , 150 , and 160 are similar, but the main difference is that: the sealing material layer 106 a of the embedded chip packaging structures 170 , 180 , 190 can be disposed around the semiconductor structure 200 and cover the semiconductor structure 200 .

The structure of the present invention is to use the sealing material layer to replace the existing groove process to manufacture the embedded chip packaging structure, so the manufacturing cost can be saved. Moreover, the present invention includes bonding two chips back-to-back and embedding them in the packaging structure, so the number of chips in the embedded chip packaging structure can be increased to improve component performance. In addition, the structure of the present invention can also be provided with a metal layer to help the package structure dissipate heat and reduce the electromagnetic interference between the outside world or the embedded stacked chips. In addition, the structure of the present invention includes a double-sided substrate, so that the embedded chip packaging structure can have double-sided contacts, and this structure can be used as a carrier required for stack packaging.

Next, the chip stack package structure of the present invention will be described. The chip stack package structure includes a carrier component and at least one chip package structure. Wherein, the chip packaging structure is arranged on the carrying component and is electrically connected with the carrying component. The number of chip packaging structures can be single or multiple, and the present invention does not specifically limit the number. In the following embodiments, a single chip packaging structure is used as an example for illustration.

Please refer to FIG. 10A , which is a schematic cross-sectional view of a chip stack package structure according to an embodiment of the present invention. In this embodiment, the carrier component can be the embedded chip packaging structure 140 , and the chip packaging structure can be the embedded chip packaging structure 110 . In particular, the arrangement relationship between the embedded chip packaging structure 110 and the embedded chip packaging structure 140 is not limited to the manner shown in FIG. 10A . The arrangement relationship of the embedded chip packaging structures 110 and 140 may be, for example, that the substrate 104 of the embedded chip packaging structure 110 is disposed on the embedded chip packaging structure 140 (as shown in FIG. 10B ). In addition, the arrangement relationship of the embedded chip packaging structures 110 and 140 can also be, for example, as shown in FIG. 10C and FIG. 10D . Based on the above, in FIG. 10A and FIG. 10C , the embedded chip packaging structures 110 and 140 are electrically connected, for example, by wire bonding. In FIG. 10B and FIG. 10D , the embedded chip packaging structures 110 , 140 are electrically connected, for example, by metal bumps, that is, for example, by forming solder balls.

In other embodiments, the carrier component of the chip stack package structure of the present invention can also be one of the embedded chip package structures 140, 150, 160, 170, 180, 190, and the chip package structure can also be embedded One of the type chip packaging structures 110 , 120 , 130 . Based on the above, other embodiments of chip stack packaging structures of the present invention can be easily completed by those skilled in the art according to the embodiments, so they are not shown here and will not be repeated here.

In addition, it should be noted that the structures shown in FIG. 10A to FIG. 10D are only schematic diagrams, and the present invention does not specifically limit the size of the carrier component and the chip package structure of the chip stack package structure.

Next, several manufacturing methods are given to describe in detail the manufacturing method of the embedded chip packaging structure of the present invention. In the following drawings, the same components are given the same reference numerals, and possible overlapping explanations are omitted.

11A to 11D are cross-sectional views of a manufacturing method of the embedded chip packaging structure according to Embodiments 1-3 of the present invention.

Referring to FIG. 11A , a carrier board 400 is provided, and the carrier board 400 may be, for example, a supporting metal plate, an insulating board or other suitable carrier boards. Then, the semiconductor structure 402 is placed on the carrier 400 . As mentioned above, the method of forming the semiconductor structure 402 on the carrier 400 may be, for example, bonding the semiconductor structure 402 and the carrier 400 with an adhesive. Taking the structure of Embodiment 1 as an example, the semiconductor structure 402 is formed by disposing electrical pads 406 on the semiconductor chip 404 . Furthermore, electrical pads 406 on the semiconductor structure 402 are in contact with the carrier 400 . The material of the electrical pad 406 can be, for example, aluminum, copper, nickel/gold or other conductive materials.

In addition, taking the structure of Embodiment 2 as an example, the semiconductor structure 402 may further include a metal layer (not shown), which may be formed on the semiconductor chip 404 . The material of the metal layer is, for example, copper, aluminum or other suitable metal materials. The metal layer can be used to help the heat dissipation of the packaging structure, and can reduce the interference of electromagnetic waves, so that the chip can operate normally. Based on the above, taking the structure of Embodiment 3 as an example, the semiconductor structure 402 may further include another semiconductor chip (not shown) formed on the semiconductor chip 404 and a connection layer, wherein the connection layer is formed between the two semiconductor chips , and electrical pads (not shown) are also formed on the semiconductor chip.

Then, referring to FIG. 11B , a molding or potting step is performed to form a sealing material layer 408 on the carrier 400 around the semiconductor structure 402 . The material of the sealing material layer 408 is, for example, a molding compound or a potting compound, such as epoxy resin, a polymer material containing silica, or other suitable molding compound. More specifically, the method of forming the sealing material layer 408 is, for example, by covering the semiconductor structure with a mold and injecting a molding compound material layer therein, so as to directly form the sealing material on the carrier 400 around the semiconductor structure 402 Layer 408. In addition, the method for forming the sealing material layer 408 may also be, for example, performing a molding step to form a molding compound material layer on the carrier 400 to cover the semiconductor structure 402, and then remove part of the molding compound material layer, until the semiconductor structure 402 is exposed to form a sealing material layer 408 . In addition, in the above method, part of the molding compound material layer and part of the semiconductor structure 402 can be removed to a required chip thickness according to different process requirements.

Subsequently, referring to FIG. 11C , after the sealing material layer 408 is formed, the carrier 400 is then removed. Next, a substrate 410 is formed on the sealing material layer 408 and the semiconductor structure 402 . The substrate 410 is mainly composed of a dielectric layer 412 and a patterned circuit layer 414 formed on the dielectric layer 412 . Wherein, the material of the dielectric layer 412 is, for example, polyimide, glass epoxy resin, bismaleimide, epoxy resin or other suitable dielectric materials. The material of the patterned circuit layer 414 is, for example, a conductive material, which may be, for example, copper foil. As mentioned above, the method of forming the sealing material layer 408 and the semiconductor structure 402 on the substrate 410 is, for example, first forming the dielectric layer 412 and the patterned circuit layer 414 to form the substrate 410, and then using an adhesive to make the sealing material layer 408 The semiconductor structure 402 is adhered to the substrate 410 . In addition, the forming method of forming the substrate 410 on the sealing material layer 408 and the semiconductor structure 402 can also be, for example, forming a dielectric layer 412 on the sealing material layer 408 and the semiconductor structure 402, and then forming a dielectric layer 412 on the dielectric layer 412 A patterned wiring layer 414 is formed thereon.

Then, referring to FIG. 11D , a plurality of via holes 416 are formed in the substrate 410 so that the patterned circuit layer 414 is electrically connected to the electrical pad 406 . The material of the via hole 416 is, for example, a conductive material, such as copper, silver, tin-lead alloy or other suitable materials. The via hole 416 is formed by, for example, using laser drilling technology to form a plurality of via holes (not shown) in the substrate 410 , and then filling the via holes with conductive material. Next, after the via hole 416 is formed, part of the substrate 410 can be further removed and cut according to the required size of different components.

12A to 12D are cross-sectional views of a manufacturing method of an embedded chip package structure according to Embodiments 4-6 of the present invention.

Please refer to FIGS. 12A-12B , the steps are the same as those in FIGS. 11A-11B , so the components that are the same as those in FIGS. 11A-11B and their relative relationships will not be repeated here. Similarly, taking the structure of Embodiment 4 as an example, the semiconductor structure 402 is formed by disposing electrical pads 406 on the semiconductor chip 404 . Taking the structure of Embodiment 5 as an example, the semiconductor structure 402 may further include a metal layer (not shown), which is formed on the semiconductor chip 404 . Taking the structure of Embodiment 6 as an example, the semiconductor structure 402 may further include another semiconductor chip (not shown) formed on the semiconductor chip 404 and a connection layer, wherein the connection layer is formed between the two semiconductor chips, and this Electrical pads (not shown) are formed on the semiconductor chip.

Then, referring to FIG. 12C , remove the carrier board 400 . Next, a substrate 410 and a substrate 420 are formed on the sealing material layer 408 and the semiconductor structure 402 . Wherein, the substrate 410 is mainly composed of a dielectric layer 412 and a patterned circuit layer 414 . The substrate 420 is mainly composed of a dielectric layer 422 and a patterned circuit layer 424 .

Next, referring to FIG. 12D , via holes 416 and 426 are formed to electrically connect the patterned circuit layer 414 to the electrical pad 406 , and to electrically connect the patterned circuit layer 414 to the patterned circuit layer 424 . In addition, taking the structure of Embodiment 6 as an example, the step in FIG. 12D also includes forming a via hole (not shown) to electrically connect the patterned circuit layer 424 and the semiconductor structure 402 . Next, after the via holes 416 and 426 are formed, part of the substrates 410 and 420 can be further removed and cut according to the required dimensions of different components.

13A to 13D are cross-sectional views of a manufacturing method of an embedded chip package structure according to Embodiments 7-9 of the present invention. The steps in FIG. 13A to FIG. 13D are similar to the steps in FIG. 12A to FIG. 12D , but the main difference is that: the sealing material layer 408 a is formed around the semiconductor structure 402 and covers the semiconductor structure 402 . The method of forming the sealing material layer 408a is, for example, performing a compression molding step to form a molding compound material layer on the carrier 400 to cover the semiconductor structure 402, and then remove part of the molding compound material according to different process requirements. layer to form. Similarly, taking the structure of Embodiment 7 as an example, the semiconductor structure 402 is formed by disposing electrical pads 406 on the semiconductor chip 404 . Taking the structure of Embodiment 8 as an example, the semiconductor structure 402 may further include a metal layer (not shown), which is formed on the semiconductor chip 404 . Taking the structure of Embodiment 9 as an example, the semiconductor structure 402 may further include another semiconductor chip (not shown) formed on the semiconductor chip 404 and a connection layer (not shown), wherein the connection layer is formed on the two semiconductor chips between, and electrical pads (not shown) are formed on the semiconductor chip.

14A to 14D are cross-sectional views of another manufacturing method of the embedded chip packaging structure shown in Embodiments 1-3 of the present invention.

Referring to FIG. 14A , a carrier board 400 is provided. Then, a substrate 410 is formed on the carrier 400 , the substrate 410 is mainly composed of a dielectric layer 412 and a patterned circuit layer 414 formed on the dielectric layer 412 , and the patterned circuit layer 414 is in contact with the carrier 400 .

Then, referring to FIG. 14B , a semiconductor structure 402 is formed on the substrate 410 . Taking the structure of Embodiment 1 as an example, the semiconductor structure 402 is formed by disposing electrical pads 406 on the semiconductor chip 404 . Taking the structure of Embodiment 2 as an example, the semiconductor structure 402 may further include a metal layer (not shown), which is formed on the semiconductor chip 404 . Taking the structure of Embodiment 3 as an example, the semiconductor structure 402 may further include another semiconductor chip (not shown) formed on the semiconductor chip 404 and a connection layer, wherein the connection layer is formed between the two semiconductor chips, and this Electrical pads (not shown) are formed on the semiconductor chip.

After that, referring to FIG. 14C , a sealing material layer 408 is formed on the carrier 400 around the semiconductor structure 402 .

Subsequently, referring to FIG. 14D , after the sealing material layer 408 is formed, the carrier 400 is then removed. Then, a plurality of via holes 416 are formed in the substrate 410 to electrically connect the patterned circuit layer 414 to the electrical pad 406 . Next, after the via hole 416 is formed, part of the substrate 410 can be further removed and cut according to the required size of different components.

15A to 15D are cross-sectional views of another manufacturing method of the embedded chip packaging structure shown in Embodiments 4-6 of the present invention.

Please refer to FIGS. 15A-15C , the steps are the same as those in FIGS. 14A-14C , so the components that are the same as those in FIGS. 14A-14C and their relative relationships will not be repeated here. Taking the structure of Embodiment 4 as an example, the semiconductor structure 402 is formed by disposing electrical pads 406 on the semiconductor chip 404 . Taking the structure of Embodiment 5 as an example, the semiconductor structure 402 may further include a metal layer (not shown), which is formed on the semiconductor chip 404 . Taking the structure of Embodiment 6 as an example, the semiconductor structure 402 may further include another semiconductor chip (not shown) formed on the semiconductor chip 404 and a connection layer, wherein the connection layer is formed between the two semiconductor chips, and this Electrical pads (not shown) are formed on the semiconductor chip.

Then, please refer to Figure 15D. A substrate 420 is formed on the sealing material layer 408 and the semiconductor structure 402 , wherein the substrate 420 is mainly composed of a dielectric layer 422 and a patterned circuit layer 424 . Afterwards, the carrier 400 is removed, and then via holes 416 and 426 are formed to electrically connect the patterned circuit layer 414 to the electrical contact pad 406 and to electrically connect the patterned circuit layer 414 to the patterned circuit layer 424, respectively. . In addition, taking the structure of Embodiment 6 as an example, the step of FIG. 15D also includes forming a via hole (not shown) to electrically connect the patterned circuit layer 424 and the semiconductor structure 402 . Next, after the via holes 416 and 426 are formed, part of the substrates 410 and 420 can be further removed and cut according to the required dimensions of different components.

16A to 16D are cross-sectional views of another manufacturing method of the embedded chip packaging structure shown in Embodiments 7-9 of the present invention.

The steps in FIG. 16A to FIG. 16D are similar to the steps in FIG. 15A to FIG. 15D , but the main difference is that: the sealing material layer 408 a is formed around the semiconductor structure 402 and covers the semiconductor structure 402 . Similarly, taking the structure of Embodiment 7 as an example, the semiconductor structure 402 is formed by disposing electrical pads 406 on the semiconductor chip 404 . Taking the structure of Embodiment 8 as an example, the semiconductor structure 402 may further include a metal layer (not shown), which is formed on the semiconductor chip 404 . Taking the structure of Embodiment 9 as an example, the semiconductor structure 402 may further include another semiconductor chip (not shown) formed on the semiconductor chip 404 and a connection layer, wherein the connection layer is formed between the two semiconductor chips, and this Electrical pads (not shown) are formed on the semiconductor chip. In addition, taking the structure of Embodiment 6 as an example, the step of FIG. 16D also includes forming a via hole (not shown) to electrically connect the patterned circuit layer 424 and the semiconductor structure 402 .

From the above, it can be known that the method of the present invention forms the encapsulation material layer by means of molding or potting to replace the existing groove process for encapsulation of embedded chips. Compared with the prior art, the method of the present invention is compatible with the existing process and can simplify the process, thus saving process cost.

In summary, the present invention may have the following advantages:

1. The structure of the present invention replaces the core layer (core layer) of the substrate in the existing packaging structure with a sealing material layer, so various existing problems can be avoided. The sealing material layer can be used to support the wiring layer of the semiconductor chip and the package body, and can achieve the purpose of protecting the semiconductor chip and the package body. Moreover, the sealing material of the present invention can be selected to have a thermal expansion coefficient similar to that of the semiconductor chip, or a material with stress buffering, so as to reduce the stress caused by the difference in thermal expansion between the two.

2. The structure of the present invention can help the entire packaging structure to dissipate heat, and can reduce the electromagnetic interference between the outside world or embedded stacked chips. In addition, compared with the prior art, the structure of the present invention can increase the number of chips in the embedded chip packaging structure, and can improve the performance of the components.

3. The structure of the present invention can make the embedded chip packaging structure have double-sided contacts, and this structure can be used as a carrier required for stack packaging.

4. The method of the present invention can replace the existing groove process, and the method of the present invention is compatible with the existing process, and can simplify the process, thus saving process cost.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Those skilled in the art may make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is defined by the claims.

Claims (40)

1. buried chip encapsulation structure comprises:

Substrate, this substrate comprise at least one dielectric layer and at least one patterned line layer that is arranged on this dielectric layer;

Semiconductor chip is arranged on this substrate, has a plurality of first electric connection pad on this semiconductor chip, and this first electric connection pad contacts with this dielectric layer;

The involution material layer is arranged on this semiconductor chip this substrate on every side, and this semiconductor chip is also supported in this involution material layer protection; And

A plurality of vias are arranged in this substrate, make this patterned line layer electrically connect this first electric connection pad.

2. buried chip encapsulation structure as claimed in claim 1, wherein the material of this involution material layer comprises mould envelope compound or perfusion compound.

3. buried chip encapsulation structure as claimed in claim 1 wherein also is provided with metal level on this semiconductor chip, and this first electric connection pad is positioned on this semiconductor chip.

4. buried chip encapsulation structure as claimed in claim 1, wherein this semiconductor chip comprises:

First semiconductor chip has this first electric connection pad on this first semiconductor chip;

Second semiconductor chip, this second semiconductor chip upper surface has a plurality of second electric connection pad, and

Also be provided with articulamentum between this first semiconductor chip and this second semiconductor chip, this second semiconductor chip is arranged on this articulamentum, and the lower surface of this second semiconductor chip contacts with this articulamentum.

5. buried chip encapsulation structure as claimed in claim 4, wherein this articulamentum is adhesion layer or metal level.

6. buried chip encapsulation structure comprises:

First substrate, this first substrate comprise at least one first dielectric layer and at least one first patterned line layer that is arranged on this first dielectric layer;

Semiconductor chip is arranged on this first substrate, has a plurality of first electric connection pad on this semiconductor chip, and this first electric connection pad contacts with this first dielectric layer;

The involution material layer is arranged on this semiconductor chip this first substrate on every side, and this semiconductor chip is also supported in this involution material layer protection;

A plurality of first vias are arranged in this first substrate, make this first patterned line layer electrically connect this first electric connection pad;

Second substrate comprises at least one second dielectric layer and at least one the second patterned circuit figure that is arranged on this second dielectric layer, and this second substrate is arranged on this semiconductor chip and this involution material layer, and this second dielectric layer contacts with this semiconductor chip; And

A plurality of second vias are arranged in this first substrate, this involution material layer and this second substrate, make this first patterned line layer electrically connect this second patterned line layer.

7. buried chip encapsulation structure as claimed in claim 6, wherein the material of this involution material layer comprises mould envelope compound or perfusion compound.

8. buried chip encapsulation structure as claimed in claim 6, wherein this involution material layer further comprises and being arranged on this semiconductor chip.

9. buried chip encapsulation structure as claimed in claim 6 wherein also is provided with metal level on this semiconductor chip, and this first electric connection pad is positioned on this semiconductor chip.

10. buried chip encapsulation structure as claimed in claim 6, wherein this semiconductor chip comprises:

First semiconductor chip has this first electric connection pad on this first semiconductor chip;

Second semiconductor chip, the upper surface of this second semiconductor chip have a plurality of second electric connection pad, and

Also be provided with articulamentum between this first semiconductor chip and this second semiconductor chip, this second semiconductor chip is arranged on this articulamentum, and the lower surface of this second semiconductor chip contacts with this articulamentum.

11. buried chip encapsulation structure as claimed in claim 10, wherein this articulamentum is adhesion layer or metal level.

12. buried chip encapsulation structure as claimed in claim 10 further comprises a plurality of the 3rd vias, so that this second patterned line layer electrically connects this second electric connection pad.

13. a chip stack package structure comprises:

Bearing assembly, this bearing assembly be as claim 7 to the 14th described buried chip encapsulation structure one of them; And

At least one chip-packaging structure is arranged on this bearing assembly, and electrically connects with this bearing assembly, and wherein this chip-packaging structure is for being selected from as claim 1 to the 6th described buried chip encapsulation structure.

14. chip stack package structure as claimed in claim 13, wherein this bearing assembly and this chip-packaging structure can utilize solder taul or the metal coupling mode electrically connects.

15. the manufacture method of a buried chip encapsulation structure comprises:

On support plate, form semiconductor chip, wherein be formed with a plurality of first electric connection pad on this semiconductor chip, and this first electric connection pad contacts with this support plate;

Form the involution material layer on this support plate around this semiconductor chip, this involution material layer protection is also supported this semiconductor chip;

Remove this support plate;

On this involution material layer and this semiconductor chip, form first substrate, wherein this first substrate comprises at least one first dielectric layer and at least one first patterned line layer that is formed on this first dielectric layer, and this first dielectric layer contacts with this semiconductor chip; And

In this first substrate, form a plurality of first vias, so that this first patterned line layer electrically connects this first electric connection pad.

16. the manufacture method of buried chip encapsulation structure as claimed in claim 15, the method that wherein forms this involution material layer on this support plate around this semiconductor chip comprise, carry out pressing mold step or perfusion filling step.

17. the manufacture method of buried chip encapsulation structure as claimed in claim 15, wherein the material of this involution material layer comprises mould envelope compound or perfusion compound.

18. the manufacture method of buried chip encapsulation structure as claimed in claim 15 wherein also is provided with metal level on this semiconductor chip, and this first electric connection pad is positioned on this semiconductor chip.

19. the manufacture method of buried chip encapsulation structure as claimed in claim 15, wherein this semiconductor chip comprises:

First semiconductor chip has this first electric connection pad on this first semiconductor chip;

Second semiconductor chip, this second semiconductor chip upper surface has a plurality of second electric connection pad, and

Also be provided with articulamentum between this first semiconductor chip and this second semiconductor chip, this second semiconductor chip is arranged on this articulamentum, and the lower surface of this second semiconductor chip contacts with this articulamentum.

20. the manufacture method of buried chip encapsulation structure as claimed in claim 19, wherein this articulamentum is adhesion layer or metal level.

21. the manufacture method of buried chip encapsulation structure as claimed in claim 15, wherein in this first substrate, form before those first vias, further comprise: on this involution material layer and this semiconductor chip, form second substrate, wherein this second substrate comprises at least one second dielectric layer and at least one second patterned line layer that is formed on this second dielectric layer, and this second dielectric layer contacts with this semiconductor chip.

22. the manufacture method of buried chip encapsulation structure as claimed in claim 21, further be included in and form a plurality of second vias in this first substrate, this second substrate and this involution material layer, so that this first patterned line layer electrically connects this second patterned line layer.

23. the manufacture method of buried chip encapsulation structure as claimed in claim 21, wherein this involution material layer further comprises and being formed between this semiconductor chip and this second substrate.

24. the manufacture method of buried chip encapsulation structure as claimed in claim 21 wherein also is provided with metal level on this semiconductor chip, and this first electric connection pad is positioned on this semiconductor chip.

25. the manufacture method of buried chip encapsulation structure as claimed in claim 21, wherein this semiconductor chip comprises:

First semiconductor chip has this first electric connection pad on this first semiconductor chip;

Second semiconductor chip, this second semiconductor chip upper surface has a plurality of second electric connection pad, and

Also be provided with articulamentum between this first semiconductor chip and this second semiconductor chip, this second semiconductor chip is arranged on this articulamentum, and the lower surface of this second semiconductor chip contacts with this articulamentum.

26. the manufacture method of buried chip encapsulation structure as claimed in claim 25, wherein this articulamentum is adhesion layer or metal level.

27. the manufacture method of buried chip encapsulation structure as claimed in claim 25 further is included in and forms a plurality of the 3rd vias in this second substrate, so that this second patterned line layer electrically connects this second electric connection pad.

28. the manufacture method of a buried chip encapsulation structure comprises:

Form first substrate on support plate, wherein this first substrate comprises at least one first dielectric layer and at least one first patterned line layer that is formed on this first dielectric layer, and this first patterned line layer contacts with this support plate;

On this first substrate, form semiconductor chip, wherein be formed with a plurality of first electric connection pad on this semiconductor chip, and this first electric connection pad and this first substrate contacts;

Form the involution material layer on this first substrate around this semiconductor chip, this involution material layer protection is also supported this semiconductor chip;

Remove this support plate; And

In this first substrate, form a plurality of first vias, so that this first patterned line layer electrically connects this first electric connection pad.

29. the manufacture method of buried chip encapsulation structure as claimed in claim 28, the method that wherein forms this involution material layer on this first substrate around this semiconductor chip comprise, carry out pressing mold step or perfusion filling step.

30. the manufacture method of buried chip encapsulation structure as claimed in claim 28, wherein the material of this involution material layer comprises mould envelope compound or perfusion compound.

31. the manufacture method of buried chip encapsulation structure as claimed in claim 28 wherein also is provided with metal level on this semiconductor chip, and this first electric connection pad is positioned on this semiconductor chip.

32. the manufacture method of buried chip encapsulation structure as claimed in claim 28, wherein this semiconductor chip comprises:

First semiconductor chip has this first electric connection pad on this first semiconductor chip;

Second semiconductor chip, this second semiconductor chip upper surface has a plurality of second electric connection pad, and

Also be provided with articulamentum between this first semiconductor chip and this second semiconductor chip, this second semiconductor chip is arranged on this articulamentum, and the lower surface of this second semiconductor chip contacts with this articulamentum.

33. the manufacture method of buried chip encapsulation structure as claimed in claim 32, wherein this articulamentum is adhesion layer or metal level.

34. the manufacture method of buried chip encapsulation structure as claimed in claim 28, wherein in this first substrate, form before this first via, further comprise: on this involution material layer and this semiconductor chip, form second substrate, wherein this second substrate comprises at least one second dielectric layer and at least one second patterned line layer that is formed on this second dielectric layer, and this second dielectric layer contacts with this semiconductor chip.

35. the manufacture method of buried chip encapsulation structure as claimed in claim 34, further be included in and form a plurality of second vias in this first substrate, this second substrate and this involution material layer, so that this first patterned line layer electrically connects this second patterned line layer.

36. the manufacture method of buried chip encapsulation structure as claimed in claim 34, wherein this involution material layer further comprises and being formed between this first semiconductor chip and this second substrate.

37. the manufacture method of buried chip encapsulation structure as claimed in claim 34 wherein also is provided with metal level on this semiconductor chip, and this first electric connection pad is positioned on this semiconductor chip.

38. the manufacture method of buried chip encapsulation structure as claimed in claim 34, wherein this semiconductor chip comprises:

First semiconductor chip has this first electric connection pad on this first semiconductor chip;

Second semiconductor chip, this second semiconductor chip upper surface has a plurality of second electric connection pad, and

Also be provided with articulamentum between this first semiconductor chip and this second semiconductor chip, this second semiconductor chip is arranged on this articulamentum, and the lower surface of this second semiconductor chip contacts with this articulamentum.

39. the manufacture method of buried chip encapsulation structure as claimed in claim 38, wherein this articulamentum is adhesion layer or metal level.

40. the manufacture method of buried chip encapsulation structure as claimed in claim 38 further is included in and forms a plurality of the 3rd vias in this second substrate, so that this second patterned line layer electrically connects this second electric connection pad.

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