CN101196806B - 用于可编程逻辑器件的大型乘法器及其方法 - Google Patents
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Abstract
可编程逻辑器件中的多个专用处理模块，其包括乘法器和用于对这些乘法器的结果求和的电路，通过添加用于在求和前对乘法器结果进行移位的专用处理模块可选择电路，所述专用处理模块可被配置为较大的乘法器。在一个实施例中，这允许除最终求和之外的所有运算发生于专用处理模块中，而最终求和在可编程逻辑电路中进行。在另一个实施例中，额外的压缩和加法电路使得甚至最终求和也可在专用处理模块中进行。
Description
背景技术
本发明涉及可编程逻辑器件(PLD)，而更具体地说，涉及可以包含于这些器件中来执行大型乘法运算的专用处理模块的使用。
随着使用PLD的应用的复杂度增加，设计包含除通用可编程逻辑设备的模块之外的专用处理模块的PLD变得更加普通。这种专用处理模块可以包括PLD上的电路集合，该PLD已部分或完全被硬连线来执行一个或多个专门的任务，如逻辑或数学运算。专用处理模块也可以包含一个或多个专用结构，如可配置存储元件阵列。通常被用于这些专用处理模块中的结构示例包括：乘法器、算术逻辑单元(ALU)、桶型移位器、各种存储元件(如先进先出(FIFO)/后进先出(LIFO)/系统安装辅助软件任选(SIPO)/随机存取存储器(RAM)/只读存储器(ROM)/中央地址存储器(CAM)模块和寄存器文件)、与门(AND)/与非门(NAND)/或门(OR)/或非门(NOR)阵列等，或这些结构的组合。
已被用于PLD的一种特别有用的专用处理模块是数字信号处理(DSP)模块，该模块可以被用于处理，例如，音频信号。这种模块也往往被称为乘法-累加(“MAC”)模块，因为它们包含用于执行乘法运算，以及求和和/或乘法运算的累加的结构。
例如，加利福尼亚州圣何塞的Altera公司所出售的名为STRATIX
II的PLD包括DSP模块，每个DSP模块包括四个18×18乘法器。这些DSP模块中的每一个还包括加法器和寄存器，以及允许各种部件以不同方式进行配置的可编程连接器(如多路转换器)。在每一个这种模块中，乘法器不仅可以配置为四个独立的18×18乘法器，还可以配置为四个更小的乘法器，或者一个更大的(36×36)乘法器。此外，可以执行一个18×18的复数乘法(针对每个实部和虚部其分解为两个18×18的乘法运算)。
尽管这一DSP模块可以被配置为高达36×36的乘法器，但用
户可能想要生成更大的乘法器。例如，尽管在IEEE 754-1985标准下36×36乘法器可以支持25×25的单精度乘法运算，但对于双精度乘法运算它就太小了。尽管来自多个DSP模块的乘法器可以被共同用来实现双精度乘法运算，但将乘法器相互联接所需要的逻辑要提前由用户在DSP模块之外的通用可编程逻辑电路中进行编程，这就使得它运行缓慢而缺乏效率，同时占用可能用作其它用途的通用设备。
发明内容
本发明涉及用于PLD的专用处理模块，所述PLD在所述模块中配备有逻辑电路以便于实现比在任何单一专用处理模块内所能执行的更大的乘法运算性能，以此降低或消除对PLD中的通用可编程设备的依赖。
在一个实施例中，专用处理模块中提供了额外的移位设备，这样所有的部分积都可以在专用处理模块中进行计算，尽管这些乘积的最终求和在专用处理模块之外的通用可编程逻辑电路中进行。在另一个实施例中，额外的移位和加法设备被添加到专用处理模块中，这样基本上可以实现整个乘法运算而不需要借助于PLD中的通用可编程设备。
依照本发明，提供了实现3n×3n乘法运算的方法，该运算适用于具有多个专用处理模块的可编程逻辑器件，每个专用处理模块具有排列于四-乘法器单元中的至少四个n×n乘法器。该方法包括在四-乘法器单元中的第一个中利用四个n×n乘法器实现2n×2n乘法运算，在四-乘法器单元中的第二个中利用一个n×n乘法器实现n×n乘法运算，在四-乘法器单元中的第三个中实现第一和第二2n×n乘法运算，这些2n×n乘法运算中的每一个都使用两个n×n乘法器，对每个2n×n乘法运算的第二部分积进行移位以使它与每个2n×n乘法运算的第一部分积对齐，以便在所述第三四-乘法器单元中进行求和，以及对来自第一、第二和第三四-乘法器单元的乘法结果求和。
同样提供了被配置为执行该方法的可编程逻辑器件，以及配置该可编程逻辑器件的软件。
附图说明
通过对下面详细描述的理解并结合附图，本发明的上述及其他目的和优点将会变得清楚，在附图中相同的参考符号始终对应于相同的部件，并且其中：
图1是将54位×54位乘法运算分解为部分积之和的一种表示；
图2是对图1中用于求和的部分积进行对齐的一种表示；
图3是用于本发明第一优选实施例的专用处理模块的一部分的示意图；
图4是在本发明第一优选实施例中实现54位×54位乘法运算的示意图；
图5是用于本发明第二优选实施例的一组专用处理模块的示意图；
图6是用于图5中实施例的4:2压缩器的示意图；
图7是使用并入本发明的可编程逻辑器件的示例性系统的简化框图；
图8是磁性数据存储介质的截面视图，该磁性数据存储介质通过机器可执行指令集进行编码以实现依据本发明的方法；以及
图9是光可读数据存储介质的截面视图，该光可读数据存储介质通过机器可执行指令集进行编码以实现依据本发明的方法。
具体实施方式
现在参考图1-6通过54位×54位乘法运算对本发明进行描述，其很好地映射到前面提到的STRATIXIIPLD中DSP模块的18位乘法器，并且可以用于在IEEE 754-1985标准下执行双精度乘法运算。但是，本发明可被用于不同尺寸的专用处理模块。
图1示出了将54位×54位乘法运算10分解为对部分积12求和11的过程，该过程可以利用18位×18位乘法器来执行以得到乘积13。在第一被乘数101中，A包含18个最高有效位，而B包含36个最低有效位。在第二被乘数102中，C包含18个最高有效位，而D包含36个最低有效位。结果(A，B)×(C，D)可以计算为B×D+((A×D+C×B)＜＜36)+((A×C)＜＜72)，其中“＜＜n”指的是与其相关的
表达式的结果向左移动n位。
在实现54位乘法运算时浮点尾数乘法运算所需的中间值优选地不标示出来——也就是说，它们包括接在“01.”之后的52位尾数。该中间值可以如图2所示进行对齐，由此输出36位的输出20和3级72位的相加21。
在前面提到的STRATIX
II PLD的DSP模块以及改进的DSP模块中，四个乘法器设置在一个单元中，其可以称为模块或半模块，再连同压缩器、加法器、移位器和多路转换器来共同形成和相加各种部分积；上述改进的DSP模块描述在同时待审且共同转让的美国专利申请号11/447,329、11/447,370、11/447,472、11/447,474(这几个申请提交于2006年6月5日)、11/426,403(提交于2006年6月26日)、11/458,361(提交于2006年7月18日)中，其中每个申请的全部内容均被并入本文。
当被应用于图1和图2所示的当前问题时，那种DSP模块体系结构可以支持36位×36位乘法运算(B×D)和18位×18位乘法运算(A×C)，但是那种体系结构中多路转换器的模式不能支持将两个18位×36位的乘法运算(A×D和C×B)相加在一起所必需的连接。对于每个18位×36位的乘法运算都是单独支持的，但结果必须被发送到DSP模块之外，在PLD的通用可编程逻辑电路中进行相加。这会占用大量的通用可编程逻辑电路以及发送和互联设备。
依照本发明，与前面提到的DSP模块相比，DSP模块的中间多路转换器的排列依照这样的方式被改变：允许两个18位×36位乘法运算之和在一个四-乘法器模块/半模块中产生。结果，在单个四-乘法器模块/半模块中，54位×54位乘法运算所必需的所有部分积都可实现并至少部分求和。
在图3和图4所示的第一优选实施例中，对于一对被乘数A和D，D可以被拆分为最高有效部分和最低有效部分，或DH和DL。然后可以将乘积A×D表示为(A×DH)＜＜18+A×DL。(A×DH)优选地由乘法器31在310处提供，然后由移位器311左移18位，在信号313的控制下由多路转换器312进行选择。A×DL优选地由乘法器32在320处提供。然后乘积A×D优选地通过在加法器33处对部分积310和320
求和而得到，加法器33可以包括连接在一起的4:2压缩器、30位加法器和24位加法器(未示出)。
第二对被乘数C和B可以做类似处理以提供(C×BH)＜＜18+C×BL。(C×BH)优选地由乘法器33在330处提供，然后被移位器331左移18位，在信号333的控制下由多路转换器332进行选择。C×BL优选地由乘法器34在340处提供。然后乘积C×B优选地通过在加法器35处对部分积330和340求和而得到，加法器35可以包括连接在一起的4:2压缩器、30位加法器和24位加法器(未示出)。
然后18位×36位乘法运算A×D和C×B的两个54位和数优选地在加法器36处相加起来，加法器36可以包括连接在一起的4:2压缩器和两个44位加法器(未示出)。尽管18位移位器37被提供用于选择性地左移加法器33的输出，这由多路转换器370在信号371的控制下进行选择，但为了这一54位的加法，和数33(A×D)未被移位。
特别地，在信号312、332、371的控制下，三个移位器311、331、37允许专用处理模块30用于多种功能。例如，对于四个18位×18位乘法运算的总和，每个信号312、332、371都优选地设定为选择其相应的未移位结果。对于一个36位×36位乘法运算，每个信号312、332、371都优选地设定为选择其相应的移位结果。如前面所述，为实现54位×54位乘法运算的两个18位×36位部分积，每个信号312、332都优选地设定为选择其相应的移位结果，而信号371优选地设定为选择其未移位结果。
如图4中所见，54位×54位乘法运算通过以下过程来实现：利用专用处理模块/半模块40来实现36位×36位部分积B×D，利用专用处理模块/半模块30来实现并将两个18位×36位部分积A×D和C×B相加，以及利用专用处理模块/半模块41来实现一个18位×18位乘法运算A×C。注意到模块/半模块41中的四个乘法器410-413仅有一个被使用，尽管如上面合并的申请11/447,472所解释，如果模块/半模块41是那一申请中所述的模块/半模块，使用仅一个乘法器410需要牺牲第二乘法器411。但是，在那一实施例中至少乘法器412、413仍可用于其他用途，而且在其他实施例中甚至乘法器411也是可用的。
依照图3和图4所示的本发明实施例，三个部分积或部分积之
和405、305和415通过加法器42相加，其结果优选地生成在PLD的可编程逻辑电路中的专用处理模块40、30、41之外，其中专用处理模块40、30、41是PLD的一部分。
在图3和图4的实施例中，对最终的求和42仍然必需使用通用可编程逻辑电路、发送和互联设备。在图5所示的第二优选实施例50中，54位×54位乘法运算可以基本上完整地在PLD上的专用处理模块中实现，基本不需要借助于该PLD中的通用可编程逻辑电路。在实施例50中，优选地使用两个四-乘法器单元51、52和第三四-乘法器单元53的一部分。优选地，每个这些四-乘法器单元51-53都是基于上面合并的申请11/447,472中所述的专用处理模块的半模块，并依照本说明书所述进行修改。因此，优选地使用一个这种模块的完整体和第二这种模块的一部分。
在实施例50中，每个半模块51、52(和半模块53，但未示出所有部件，因为仅一个乘法器530由那个半模块52使用)优选地具有四个18位×18位乘法器510-513、520-523，优选地排列成对510-511、512-513、520-521和522-523，且在每一对中某个部件的输出被相应的移位器55左移18位后，每对部件的输出优选地通过相应的54位加法器541-544进行求和。在上面图3和图4的实施例中，一个或更多移位器55可以是可编程地被旁路(未示出)，但是在这一实施例中，为了实现54位×54位乘法运算，移位器55优选地不被旁路(即使它们是可旁路的)。
在上面合并的申请11/447,472中所描述的专用处理模块中，加法器541的输出，以及加法器542的输出在被移位器545左移18位后，可以通过3:2压缩器560和链式进位/传递加法器570、571进行求和。类似地，加法器543和544的输出可以通过3:2压缩器561和链式进位/传递加法器572、573进行求和。依照本发明，添加了4:2压缩器562和两个36位右移移位器546、547。如下所述添加了很多AND门580-583作为选择器，尽管多路转换器也可以用于实现这一功能，同时添加AND门584以将加法器570、571和加法器572、573链接起来。此外，添加18位右移移位器548和AND门585，桥接不同的专用处理模块中的半模块52、53。注意到另一个类似于移位器548的
18位右移移位器(未示出)和另一个类似于AND门585的AND门(未示出)可以以相似的方式将半模块51连接到它右边的另一个半模块。
当不用于54位×54位乘法运算模式时，每个专用处理模块以上面合并的申请11/447,472所示的方式进行操作。同样地，每个AND门580、582、584和585的第二输入(未示出)均为“0”以便于移位器546-548不被使用而两个半模块的进位/传递加法器链仍然分离或独立。类似地，每个AND门581、583的第二输入(未示出)均为“1”以便于每个部分积直接送入其相应的3:2或4:2压缩器。注意到在这种情况下，由于AND门580的第二输入为“0”，4:2压缩器562的作用就像3:2压缩器560、561。
当专用处理模块被用于54位×54位乘法运算模式时，每个AND门580、582、584和585的第二输入(未显示)均为“1”以便于移位器546-548被使用而两个半模块的进位/传递加法器链被连接起来。由于这是72位加法，自44位加法器571传给44位加法器572的进位输出(通过AND门584)优选地不从加法器571的末端取出，而优选地取自加法器571的第29位，包括加法器570在内这是第73个比特位，代表来自72位加法的进位输出。尽管它依赖于多于一个的专用处理模块，但这种排列可以基本对所有的部分积求和而不需借助于PLD的通用可编程逻辑电路。
图6示意性地示出了4:2压缩器562可以如何由两个3:2压缩器560(或561)配置而成。
因此可以看出需要多于一个PLD专用处理模块的大型乘法运算可以通过使用更少的或不使用PLD通用可编程设备来实现。
依据本发明合并这些电路的PLD 280可以被用于很多种电子器件中。一种可能的应用是应用于图7所示的数据处理系统900。数据处理系统900可以包括一个或更多以下部件：处理器281；存储器282；I/O电路283；以及外围设备284。这些部件通过系统总线285耦合在一起并组装在电路板286上，该电路板包含于终端用户系统287中。
系统900可以用于很多不同的应用，如计算机网络、数据网络、仪表设备、视频处理、数字信号处理，或其他任何希望利用可编程或可重复编程逻辑器件优点的应用。PLD 280可以用于实现各种不同的逻
辑功能。例如，PLD 280可以被配置为与处理器281协同工作的处理器或控制器。PLD 280也可以被用作仲裁器来仲裁对系统900中的共享资源的存取。在另一个示例中，PLD 280可以被配置为处理器281与系统900中的其他部件中的一个之间的接口。需要注意的是系统900只是示例性的，而本发明的真实范围和精神应由下面的权利要求进行说明。
各种不同的技术都可以用来执行如上所述的PLD 280并且合并到本发明中。
用于实现依据本发明的方法的指令可以在机器可读的介质上进行编码，以便由合适的计算机或类似设备来执行以实现对PLD编程的本发明的方法。例如，个人计算机可以配备有可连接PLD的接口，而该个人计算机可以由用户使用以借用合适的软件工具，如加利福尼亚州圣何塞的Altera公司所提供的QUARTUS
II软件对该PLD进行编程。
图8展现了磁性数据存储介质600的截面图，该磁性数据存储介质可以通过机器可执行程序进行编码，该机器可执行程序可以由前面提到的个人计算机，或其他计算机或类似设备之类的系统来执行。介质600可以是软盘或硬盘，或磁带，该介质按照惯例含有合适的衬底601，同时按照惯例在一面或两面覆盖有合适的涂层602，该介质包含极性或取向可以在磁性上改变的磁畴(不可见)。除了是磁带的情况外，介质600也可以具有接纳磁盘驱动器或其他数据存储器件的中心轴的开孔(未示出)。
介质600上涂层602的磁畴被极化或定向以便以传统的方式对机器可执行程序进行编码，以此通过个人计算机或其他计算机或类似系统之类的程序设计系统的执行来依照本发明对PLD适当的部分进行设定，如果该PLD有专用处理模块的话，包括其专用处理模块，该程序设计系统具有要被编程的PLD可以插入的插槽或外围附件。
图9示出了光可读数据存储介质700的截面图，该光可读数据存储介质也可以通过这一机器可执行程序进行编码，该机器可执行程序可以由前面提到的个人计算机，或其他计算机或类似设备之类的系统来执行。介质700可以是传统的光盘只读存储器(CD-ROM)或数字视频光盘只读存储器(DVD-ROM)或可重写介质，如CD-R、CD-RW、DVD-R、DVD-RW、DVD+R、DVD+RW、或DVD-RAM或光可读且磁光可重写的磁光盘。
介质700优选地按照惯例含有合适的衬底701，同时按照惯例一般在衬底701的一面或两面覆盖有合适的涂层702。
如果是基于CD或基于DVD的介质，众所周知的是，涂层702是可反射的且被施加多个凹陷点703，这些凹陷点排列在一层或更多层上，以对机器可执行程序进行编码。凹陷点的排列通过从涂层702的表面反射激光进行读取。在涂层702的上面为其提供保护性涂层704，保护性涂层优选地是基本透明的。
如果是磁光盘，众所周知的是，涂层702上没有凹陷点703，但是有多个磁畴，当例如被激光(未示出)加热到一定温度之上后，这些磁畴的极性或取向可以在磁性上改变。这些磁畴的取向可以通过测量从涂层702反射的激光的偏振性来进行读取。这些磁畴的排列对上述的程序进行编码。
应理解以上只是本发明原理的示意性说明，本领域的技术人员可以做出各种修改而不偏离本发明的范围和精神。例如，本发明中的各种元件可以以任何所需的数量和/或排列提供给PLD。本领域的技术人员应理解本发明可以由除所述实施例之外的其他实施例来实现，所述实施例仅被用于示例性说明而不是限制，本发明仅由所附的权利要求进行限制。
Claims (16)
1.为了用于含有多个专用处理模块的可编程逻辑器件中，每个所述专用处理模块含有排列于四-乘法器单元中的至少四个n×n乘法器，执行3n×3n乘法运算的方法，所述方法包括：
在所述四-乘法器单元中的第一个中利用四个所述n×n乘法器执行2n×2n乘法运算；
在所述四-乘法器单元中的第二个中利用一个所述n×n乘法器执行n×n乘法运算；
在所述四-乘法器单元中的第三个中执行第一和第二2n×n乘法运算，对每个所述2n×n乘法运算使用两个所述n×n乘法器；
对每个所述2n×n乘法运算的第二部分积进行移位以使它与每个所述2n×n乘法运算的第一部分积对齐，以便在所述第三四-乘法器单元中进行求和；以及
对来自所述第一、第二和第三四-乘法器单元的所述乘法运算的结果求和。
2.根据权利要求1所述的方法，其中所述对来自所述第一、第二和第三四-乘法器单元的所述乘法运算的结果求和包含在所述可编程逻辑器件的通用可编程逻辑电路中对所述结果进行求和。
3.根据权利要求2所述的方法，其中：
所述执行第一和第二2n×n乘法运算包括，对于每个相应的所述第一和第二2n×n乘法运算之一：
利用所述第三四-乘法器单元中的一个所述乘法器执行相应最高有效位的乘法运算来形成相应的最高有效位部分积，以及
利用所述第三四-乘法器单元中的另一个所述乘法器执行相应最低有效位的乘法运算来形成相应的最低有效位部分积；
所述移位包含将每个相应的最高有效位部分积左移而不对任何相应的最低有效位部分积进行移位；以及
所述第三四-乘法器单元中的所述求和不包括进一步对部分积进行移位。
4.根据权利要求3所述的方法，进一步包含选择控制信号来执行所述移位和未进一步移位情况下的所述在所述第三四-乘法器单元中进行求和。
5.根据权利要求1所述的方法，其中每个所述专用处理模块包含两个所述四-乘法器单元。
6.根据权利要求5所述的方法，其中所述对来自所述第一、第二和第三四-乘法器单元的所述乘法运算的结果求和包含在一个所述专用处理模块中执行所述对来自所述第一、第二和第三四-乘法器单元的所述乘法运算的结果求和。
7.根据权利要求6所述的方法，其中：
所述2n×2n乘法运算以及所述第一和第二2n×n乘法运算在包含所述第一和第三四-乘法器单元的所述的一个专用处理模块中执行；
所述执行所述2n×2n乘法运算以及第一和第二2n×n乘法运算包括，对于每个相应的所述2n×2n乘法运算以及第一和第二2n×n乘法运算之一：
利用所述第一四-乘法器单元中的一个所述乘法器为所述2n×2n乘法运算执行最高有效位的乘法运算来为所述2n×2n乘法运算形成最高有效位部分积，并利用所述第三四-乘法器单元中相应的一个所述乘法器为所述2n×n乘法运算中每个相应的乘法运算执行相应的最高有效位的乘法运算来为所述2n×n乘法运算中每个相应的乘法运算形成相应的最高有效位部分积；以及
利用所述第一四-乘法器单元中的另一个所述乘法器为所述2n×2n乘法运算执行最低有效位的乘法运算来为所述2n×2n乘法运算形成最低有效位部分积，并利用所述第三四-乘法器单元中相应的其他所述乘法器为所述2n×n乘法运算中每个相应的乘法运算执行相应的最低有效位的乘法运算来为所述2n×n乘法运算中每个相应的乘法运算形成相应的最低有效位部分积；以及
所述移位包含对所述2n×n乘法运算的每一个相应的所述最高有效位部分积左移而不对所述2n×n乘法运算的任何一个相应的所述最低有效位部分积进行移位；所述方法进一步包括：
对所述2n×2n乘法运算的所述最高有效位部分积左移而不对所述2n×2n乘法运算的所述最低有效位部分积进行移位；
对所述2n×2n乘法运算的所述最高有效部分积和最低有效位部分积求和以生成所述2n×2n乘法运算的2n×2n部分积的最高有效位和数和最低有效位和数；
对所述2n×n乘法运算的每对相应的最高有效部分积和最低有效位部分积求和以为每个所述2n×n乘法运算生成相应的最高有效位和数和最低有效位和数；
左移所述2n×2n乘法运算的所述2n×2n部分积的最高有效位和数；
右移2n×n部分积的所述最高有效位和数以及所述2n×n部分积的所述最低有效位和数；
右移所述n×n乘法运算的输出并且将所述经右移的所述n×n乘法运算的输出输入到包含所述第一和第三四-乘法器单元的所述专用处理模块中的所述一个中；以及
对所述2n×2n部分积的所述经左移的最高有效位和数、所述2n×n部分积的所述经右移的最高有效位和数和最低有效位和数、所述n×n乘法运算的所述经右移的输出，以及所述2n×2n部分积的所述最低有效位和数求和。
8.根据权利要求7所述的方法，其中对所述2n×2n部分积的所述经左移的最高有效位和数、所述2n×n部分积的所述经右移的最高有效位和数和最低有效位和数、所述n×n乘法运算的所述经右移的输出，以及所述2n×2n部分积的所述最低有效位和数求和包括：
压缩所述2n×2n部分积的所述最低有效位和数；
压缩所述2n×2n部分积的所述经左移的最高有效位和数连同所述2n×n部分积的第一个所述经右移的最高有效位和数和最低有效位和数；
压缩所述n×n乘法运算的所述经右移的输出连同所述2n×n部分积的第二个所述经右移的最高有效位和数和最低有效位和数；以及
对所述压缩的结果求和。
9.一个可编程逻辑器件含有多个专用处理模块，每个所述专用处理模块含有排列于四-乘法器单元中的至少四个n×n乘法器，所述可编程逻辑器件被配置用来执行3n×3n乘法运算并且其包含：
四个所述n×n乘法器，其位于被配置用来执行2n×2n乘法运算的所述四-乘法器单元中的第一个中；
一个所述n×n乘法器，其位于被配置用来执行n×n乘法运算的所述四-乘法器单元中的第二个中；
所述四-乘法器单元中的第三个，其被配置用来执行第一和第二2n×n乘法运算，对每个所述2n×n乘法运算使用两个所述n×n乘法器；
移位器，其被配置用来对每个所述2n×n乘法运算的第二部分积进行移位以使它与每个所述2n×n乘法运算的第一部分积对齐，以便在所述第三四-乘法器单元中进行求和；以及
电路，其被配置用来对来自所述第一、第二和第三四-乘法器单元的所述乘法运算的结果求和。
10.根据权利要求9所述的可编程逻辑器件，其中所述对来自所述第一、第二和第三四-乘法器单元的所述乘法运算的结果求和包含在所述可编程逻辑器件的通用可编程逻辑电路中对所述结果进行求和。
11.根据权利要求10所述的可编程逻辑器件，其中：
所述可编程逻辑器件被配置用来执行所述第一和第二2n×n乘法运算，经由对于每个相应的所述第一和第二2n×n乘法运算之一：
利用所述第三四-乘法器单元中的一个所述乘法器执行相应最高有效位的乘法运算来形成相应的最高有效位部分积，以及
利用所述第三四-乘法器单元中的另一个所述乘法器执行相应最低有效位的乘法运算来形成相应的最低有效位部分积；
所述可编程逻辑器件被配置用来对每个相应的最高有效位部分积左移而不对任何相应的最低有效位部分积进行移位；以及
所述电路被配置用来求和而不对部分积进行进一步的移位。
12.根据权利要求11所述的可编程逻辑器件，进一步包括选择器，它可响应选择控制信号来执行所述移位和未进一步移位情况下的所述在所述第三四-乘法器单元中进行求和。
13.根据权利要求9所述的可编程逻辑器件，其中每个所述专用处理模块包含两个所述四-乘法器单元。
14.根据权利要求13所述的可编程逻辑器件，其中被配置用来求和的所述电路位于一个所述专用处理模块中。
15.根据权利要求14所述的可编程逻辑器件，其中：
所述一个专用处理模块包含所述第一和第三四-乘法器单元，所述第一四-乘法器单元被配置用来执行所述2n×2n乘法运算以及所述第三四-乘法器单元被配置用来执行所述第一和第二2n×n乘法运算；
在每个所述第一和第三四-乘法器单元中，所述执行所述2n×2n乘法运算以及第一和第二2n×n乘法运算包括：对于每个相应的所述2n×2n乘法运算以及第一和第二2n×n乘法运算之一：
利用第一所述四-乘法器单元中的一个所述乘法器为所述2n×2n乘法运算执行最高有效位的乘法运算来为所述2n×2n乘法运算形成最高有效位部分积，并利用所述第三四-乘法器单元中相应的一个所述乘法器为所述2n×n乘法运算中每个相应的乘法运算执行相应的最高有效位的乘法运算来为所述2n×n乘法运算中每个相应的乘法运算形成相应的最高有效位部分积；以及
利用所述第一四-乘法器单元中的另一个所述乘法器为所述2n×2n乘法运算执行最低有效位的乘法运算来为所述2n×2n乘法运算形成最低有效位部分积，并利用所述第三四-乘法器单元中相应的其他所述乘法器为所述2n×n乘法运算中每个相应的乘法运算执行相应的最低有效位的乘法运算来为所述2n×n乘法运算中每个相应的乘法运算形成相应的最低有效位部分积；以及
所述移位器被配置用来对所述2n×n乘法运算的每一个相应所述最高有效位部分积左移而不对所述2n×n乘法运算的任何一个相应的所述最低有效位部分积进行移位；所述经配置的可编程逻辑器件进一步包含：
移位器，其用来对所述2n×2n乘法运算的所述最高有效位部分积左移而不对所述2n×2n乘法运算的所述最低有效位部分积进行移位；
电路，其被配置用来对所述2n×2n乘法运算的所述最高有效位部分积和最低有效位部分积求和，以生成所述2n×2n乘法运算的2n×2n部分积的最高有效位和数和最低有效位和数；
电路，其被配置用来对所述2n×n乘法运算每对相应的最高有效位部分积和最低有效位部分积求和，以生成每个所述2n×n乘法运算的相应的最高有效位和数和最低有效位和数；
第一左移电路，其用来左移所述2n×2n乘法运算的所述2n×2n部分积的所述最高有效位和数；
右移电路，其用来右移2n×n部分积的所述最高有效位和数以及所述2n×n部分积的所述最低有效位和数；
第二右移电路，其用来右移所述n×n乘法运算的输出并且将所述经右移的所述n×n乘法运算的输出输入到包含所述第一和第三四-乘法器单元的所述一个所述专用处理模块中；以及
电路，其被配置用来对所述2n×2n部分积的所述经左移的最高有效位和数、所述2n×n部分积的所述经右移的最高有效位和数和最低有效位和数、所述n×n乘法运算的所述经右移的输出以及所述2n×2n部分积的所述最低有效位和数求和。
16.根据权利要求15所述的可编程逻辑器件，其中被配置用来对所述2n×2n部分积的所述经左移的最高有效位和数、所述2n×n部分积的所述经右移的最高有效位和数和最低有效位和数、所述n×n乘法运算的所述经右移的输出以及所述2n×2n部分积的所述最低有效位和数求和的电路包含：
第一3:2压缩电路，其用来压缩所述2n×2n部分积的所述最低有效位和数；
4:2压缩电路，其用来压缩所述2n×2n部分积的所述经左移的最高有效位和数连同所述2n×n部分积的第一个所述经右移的最高有效位和数和最低有效位和数；
第二3:2压缩电路，其用来压缩所述n×n乘法运算的所述经左移的输出连同所述2n×n部分积的第二个所述经右移的最高有效位和数和最低有效位和数；以及
加法电路，其用来对所述第一和第二3:2压缩电路以及所述4:2压缩电路的输出求和。
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| CN (1) | CN101196806B (zh) |
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| US20140289293A1 (en) | 2014-09-25 |
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| EP1936809A2 (en) | 2008-06-25 |
| EP2464010A2 (en) | 2012-06-13 |
| JP2012248208A (ja) | 2012-12-13 |
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