CN101183315A - A Parallel Multiprocessor Virtual Machine System - Google Patents

Abstract

The invention discloses a parallel multi-processor virtual machine system supporting simultaneous CPU execution, which includes a virtual machine and an operating system running on the virtual machine. The virtual machine system can simulate at least one virtual processor, which includes a processor parallel simulation module, a memory management module, an interrupt control simulation module and a peripheral simulation module; the machine instructions of the operating system are transmitted through the memory management module of the virtual machine For the processor simulation module, the processor simulation module can simulate multiple virtual processors to execute the operating system instructions translated by the instruction translation module, and make them execute in parallel. At the same time, the present invention proposes synchronization and access control in the process of parallel execution Algorithm; the interrupt control analog module is responsible for coordinating the peripheral analog module and the processor analog module. The invention is particularly suitable for virtualizing a parallel execution environment of a complete simulated hardware on an SMP server or a multi-core server.

Description

A Parallel Multiprocessor Virtual Machine System

technical field

The invention relates to a computer system structure, in particular to a parallel multi-processor virtual machine system, which enables multiple virtual processors to run in parallel on a modern multi-processor server platform.

Background technique

The operating system plays a very special role in today's personal computers and servers. It is like a bridge that bridges the gap between user applications and hardware platforms. For a long time in the past, only one operating system could run on a computer at any given time. Therefore, in order to enable multiple operating systems, or application programs of different operating systems to run simultaneously on the same computer, scientists have invented many methods and technologies.

Virtual machines are widely used as a powerful and convenient technology.

System-level virtual machines simulate all components of a computer system with high precision. In this way, the operating system and its applications can run correctly on this virtual machine. A system-level virtual machine runs on an operating system as an application. The system-level virtual machine can use the services provided by the operating system, but is also limited by the operating system. For example, if the operating system provides protection for memory access and does not allow applications to directly access the physical address of the memory, then when the virtual machine is running, the There will be a huge overhead in memory management. Representatives of this type of virtual machine are: Bochs, QEMU, etc. System-level virtual machines are generally used in the scientific research field of system structure to help researchers measure the performance of multi-processor or storage systems, or in the field of operating system development.

With the rapid development of hardware, especially the wide application of SMP (symmetrical multiprocessor) servers and the advancement of multi-core technology, some current virtual machine technologies either cannot make full use of multi-processor resources, or the number of virtual CPUs is limited. The actual number of physical processors is limited. The various virtual machines mentioned above also have one or another deficiency. When a traditional virtual machine (such as: Bochs IA-32 Emulator: http://bochs.sourceforge.net/ ) constructs a user execution environment with multi-processing resources, in order to realize the synchronization of execution units, multiple processing units are actually The execution content is placed in a loop for serial execution, and its efficiency is very low. In order to construct a general-purpose and virtual execution environment in a multi-processor environment, it is necessary to realize the parallelization of the execution environment itself. At the same time, due to the continuous increase in the number of cores owned by multi-core hardware, the execution environment itself must be scalable. Reliability, that is, the system can run without modification on a processor machine with any number of cores, and can fully utilize the processing performance of the underlying host. And the parallel multiprocessor virtual machine system of the present invention has just solved this problem effectively.

Contents of the invention

The purpose of the present invention is to provide a parallel multi-processor virtual machine system, which can simulate a complete computer system, can simulate multiple CPUs, and make the virtual CPUs execute in parallel at the same time.

The parallel multiprocessor virtual machine system provided by the present invention is characterized in that: the system includes a virtual machine and an operating system in the virtual machine;

The operating system in the virtual machine uses an operating system that supports symmetric multiprocessors and runs on the virtual machine;

The virtual machine provides users with a virtual platform, which includes a processor parallel simulation module, a memory management module, an interrupt control simulation module and a peripheral simulation module;

The processor parallel simulation module is used to receive the instructions submitted by the operating system in the virtual machine, and execute them after translation; if the instructions involve memory reading and writing, the read and write operation signals will be passed to the memory management module; if the processor parallel simulation module needs to handle interrupts, then send the interrupt signal to the interrupt control module;

The memory management module is responsible for the management of all memory read and write operations. The memory management module transmits the received peripheral port address to the peripheral simulation module, and feeds back the results of memory read and write operations to the processor parallel simulation module;

The peripheral analog module is responsible for simulating all peripheral actions and responding to port access messages. If an interrupt is to be triggered, the interrupt signal is sent to the interrupt control analog module for processing;

The interrupt control module is responsible for the control and management of the interrupt signal in the virtual machine; on the one hand, it receives the external interrupt signal from the peripheral simulation module, and on the other hand, it cooperates with the processor parallel simulation module to execute the interrupt operation.

The present invention can not only completely provide a computer system view, but also make full use of various processing resources of actual hardware. Compared with existing technology, the present invention has following characteristics:

a. Be able to simulate a complete computer system. Many traditional virtual machines cannot provide a complete view of the computer system due to performance considerations or limitations of implementation methods. They often just provide a software execution environment. Because of this, only some software written specifically for these traditional virtual machines can run on these virtual machines. Such restrictions make many other widely used software must be rewritten before they can be applied to virtual machines, which will inevitably increase a lot of workload virtually. Since the present invention provides a simulation of a complete computer system, various mainstream operating systems can be directly run without any modification. In this way, all application software can be directly used without any modification depending on the operating system.

b. You can adjust the number of virtual CPUs and configure various hardware parameters at any time. Because the present invention implements each virtual CPU with thread encapsulation, the number of virtual CPUs is completely not limited by the number of actual physical CPUs. In addition, since all the peripherals of the present invention are simulated and managed by the peripheral simulation module, the peripherals will not be limited by actual real devices. Users can simulate various types of peripherals at will, and they can be easily added to the virtual machine system only by providing a unified read and write interface.

c. The multi-processor computing resource of the actual server can be efficiently utilized by means of parallel execution. The present invention simulates a computer system in a completely parallel manner. If the virtual machine of the present invention runs in a multi-processor hardware environment, it will make full use of actual computing resources. Even if the underlying physical computing environment changes, it is transparent to the operating system and its application software running inside the virtual machine of the present invention.

d. When parallelizing and simulating multi-processors, the present invention utilizes a synchronization method of virtual CPU threads and access control to critical resources to ensure the logical correctness of virtual machines during execution.

Description of drawings

Fig. 1 is a schematic diagram of the hierarchical structure of the parallel multiprocessor virtual machine system provided by the present invention;

Fig. 2 is the structural representation of the processor parallel simulation module in Fig. 1;

Fig. 3 is a schematic structural diagram of the memory management module in Fig. 1;

Fig. 4 is a schematic diagram of thread allocation when the number of virtual CPUs is less than the number of actual processors in the parallel multiprocessor virtual machine system provided by the present invention;

Fig. 5 is a schematic diagram of thread allocation when the number of virtual CPUs is greater than the number of actual processors in the parallel multiprocessor virtual machine system provided by the present invention;

6 is a schematic diagram of a method for synchronizing parallel virtual CPU threads in a parallel multiprocessor virtual machine system provided by the present invention;

FIG. 7 is a service flowchart of the parallel multiprocessor virtual machine system provided by the present invention.

Detailed ways

Below in conjunction with accompanying drawing and example the present invention is described in further detail.

As shown in FIG. 1 , from the perspective of the architecture level, the computer system applied by the present invention includes a parallel multiprocessor virtual machine system 3 , a local operating system layer 4 and a local server 5 from top to bottom.

The local operating system 4 can use any current mainstream operating system supporting SMP (such as Windows, Linux). The local server 5 is the physical basis of the present invention, and it includes p processors 51, 52, . . . , 5p, where 2≤p≤16.

The parallel multiprocessor virtual machine system 3 includes a virtual machine 1 and an operating system 2 in the virtual machine, and the operating system 2 in the virtual machine runs on the virtual machine 1 . The operating system 2 in the virtual machine is an operating system supporting SMP (symmetrical multiprocessor), and it has the capability of supporting parallel processing. If you use Windows, Windows can directly support SMP. If you use Linux, you need to recompile the Linux kernel to add its support option for SMP.

The virtual machine 1 provides a virtual platform for users, and it includes a processor parallel simulation module 11 , a memory management module 12 , an interrupt control simulation module 13 and a peripheral hardware simulation module 14 .

The processor parallel simulation module 11 is used for receiving instructions submitted by the operating system 2 in the virtual machine, and executing them after translation. If the instruction involves memory reading and writing, the reading and writing operation signal will be transmitted to the memory management module 12 . If the processor parallel simulation module 11 is to process an interrupt, it sends the interrupt signal to the interrupt control module 13 .

The memory management module 12 is responsible for the management of all memory read and write operations. The memory management module mainly transmits the received peripheral port address to the peripheral simulation module 14 , and feeds back the result of the memory read and write operation to the processor parallel simulation module 11 .

The interrupt control module 13 is responsible for the control and management of the interrupt signal in the virtual machine 1; on the one hand, it receives the external interrupt signal from the peripheral simulation module 14, and on the other hand, it cooperates with the processor parallel simulation module 11 to execute the interrupt operation.

The peripheral hardware simulation module 14 is responsible for simulating all peripheral hardware actions and responding to port access messages. If an interrupt is to be triggered, the interrupt signal is sent to the interrupt control simulation module 13 for processing.

The specific structures of the processor parallel simulation module 11 and the memory management module 12 are illustrated below with examples. Those skilled in the art can implement the technical solutions of the present invention with other various specific implementation methods according to the content disclosed by the present invention, and the protection scope of the present invention It is not limited to the contents of the following examples.

As shown in FIG. 2 , the processor parallel simulation module 11 includes an instruction function function table 111 , a synchronization control module 112 and a virtual CPU thread module 113 .

The virtual CPU thread module 113 dynamically constructs n virtual CPU threads T ₁ , T ₂ , . . . , T _n (3≤n≤17), and each virtual CPU thread corresponds to a physical CPU. The virtual CPU threads T ₁ , T ₂ , . . . , T _n (hereinafter referred to as virtual CPU threads) are all responsible for simulating the behavior of a virtual CPU, and their main functions are instruction translation and instruction function execution.

All virtual CPU threads in the virtual CPU thread module 113 can obtain the binary code of the instruction to be executed by the current virtual CPU through the memory management module 12, and the binary code is translated into a corresponding instruction number via the virtual CPU thread. After the virtual CPU thread obtains the translated instruction number, it queries the instruction function function table 111 to obtain the entry of the function function corresponding to the current instruction. Then, the virtual CPU thread executes the function corresponding to the instruction to complete the action specified by the current instruction.

If the current instruction involves a soft interrupt or an exception, the virtual CPU thread will send the interrupt number to the interrupt control simulation module 13 . After the interrupt control simulation module 13 receives the interrupt number, it realizes the corresponding interrupt function according to the interrupt number, and simultaneously switches the context of the virtual CPU thread corresponding to this instruction, so that it can transfer to the interrupt or exception processing.

If the function of the current instruction is only to change the state of the virtual CPU itself, then after the corresponding action is executed, the execution process of the next instruction will be entered by the same method mentioned above. If the function of the current instruction involves reading and writing of the physical address of the memory, the reading and writing operation will be passed to the memory management module 12 .

The synchronization control module 112 cooperates with the virtual CPU thread module 113 to coordinate the synchronous execution of all virtual CPU threads.

As shown in FIG. 3 , the memory management module 12 includes an address judgment module 121 and a memory access operation module 122 . After receiving the read and write operations sent by the virtual CPU thread 1 , the address judging module 121 judges the physical addresses involved in the read and write operations. If it is an ordinary memory address, then it is directly handed over to the memory access operation module 122 to perform the memory access action; After receiving the port number, the peripheral device that retrieves the port response performs read and write operations.

If the peripheral simulated by the peripheral simulation module 14 has an interrupt request, the peripheral simulation module 14 will send the interrupt request to the interrupt control simulation module 13 . After the interrupt control simulation module 13 executes the corresponding processing, the interrupt number is put into the interrupt request queue of the interrupt simulation module 13. Meanwhile, the interrupt control simulation module 13 will set the context of the virtual CPU thread 1 and hand it over to the virtual CPU thread 1 for processing.

The principle of _parallel execution of virtual CPU threads T ₁ , T ₂ , . . .

The parallel execution of virtual CPU threads T ₁ , T ₂ , . . . , T _n is the core component of the present invention. Existing traditional system-level virtual machine systems generally mark each CPU with an array, and then use a loop to allocate each virtual CPU to run on a single physical CPU time-sharing. However, in the present invention, each virtual CPU is implemented with a thread, so that it can run on a multi-processor server in parallel at the same time.

The virtual CPU threads T ₁ , T ₂ , . . . , T _n are threaded CPU simulations. Furthermore, each virtual CPU is encapsulated with a thread, and each thread can access the common memory management module 12, thereby realizing a virtual SMP architecture. Further, as shown in Figure 4, assuming that the number of real physical CPUs is p, and the number of virtual CPU threads T ₁ , T ₂ , ..., T _n is less than or equal to the actual number of physical CPUs, the virtual CPU process will be connected with Physical CPUs are mapped one-to-one. In this way, the disadvantage of low cache hit rate caused by switching threads between different CPUs can be reduced. If the number of virtual CPUs is greater than the number of actual physical CPUs, the local operating system 4 will try to ensure that each virtual CPU thread T ₁ , T ₂ , ..., T _n can be scheduled to run on the physical CPU that has been running before .

As shown in FIG. 5 , assume that the number of real physical CPUs is p, and the number of virtual CPUs of the user is a*p+b (where a, b, and p are all positive integers, b<p). The local operating system 4 will assign the 1st, p+1, 2p+1, ..., a*p+1 created virtual CPU threads to run on the 1st physical CPU. In the same way: the 2nd, p+2, 2p+2, ..., a*p+2 virtual CPU threads are assigned to run on the 2nd physical CPU. In this way, the virtual CPU threads will be divided into p groups, and each group has a or a+1 virtual CPU threads running on a physical CPU. However, it is worth noting that if the following conditions occur, the sum of the number of user program processes or threads is less than the number of virtual CPUs. For example, there are currently 4 real physical CPUs, and the user creates 8 virtual CPU threads, so that each real There are 2 virtual CPU threads running on the CPU. At this time, if there are only 2 user threads running on the virtual machine, and they all run on the same virtual CPU thread. Native OS 4 also does not reschedule virtual CPU threads. This is because, if there is no task running on the virtual CPU thread, there will be an idle process running on it. It is simply impossible for the native operating system 4 to know whether a virtual CPU thread is idle or not. Therefore, the operating system does not schedule virtual CPU threads according to the load of the virtual machine. That is to say, once a virtual CPU thread is created, it is basically determined to run on the same CPU, which can improve the cache hit rate, reduce the cache synchronization overhead between the local server CPUs, and the memory synchronization overhead, and improve the system performance. Operate with speed and efficiency.

In order to ensure that the virtual machine of the present invention can run correctly under the condition of parallel execution, the present invention proposes a method for controlling its parallel execution. Including: a method for synchronizing parallel virtual CPUs and an access control method for critical resources.

Further for the synchronous method (as Fig. 6) of parallel virtual CPU, the present invention is each virtual CPU thread T ₁ , T ₂ , ..., T _n all is provided with a pair of sending and waiting operation of message communication; Simultaneously in all A synchronization control module 112 is set outside the virtual CPU thread. After each virtual CPU thread executes a specified number of instructions, it sends a notification message to the synchronization control module. Then enter the message and wait for the operation. After the notification messages of all the CPU threads are sent to the synchronization control module 112, the synchronization control module 112 sends the continuation messages to all the virtual CPU threads T ₁ , T ₂ , . . . , T _n respectively. The virtual CPU threads T ₁ , T _{2 ,} . The synchronization method of the present invention enables all virtual CPU threads to keep the error of the number of relative executed instructions within a certain controllable range. This ensures the logical correctness of the entire virtual machine.

In the access control method for critical resources, the critical resources to be managed in the present invention include: atomic operations of reading and writing peripheral ports and two memory access instructions.

Furthermore, regarding the reading and writing of peripheral ports, when a certain virtual CPU thread 1 in the virtual machine of the present invention is performing read and write operations on a memory address mapped by a certain peripheral port, if there is another virtual CPU thread ( If virtual CPU thread 2) also sends read and write operations to the same port at this time, the conflict between these two operations will cause the wrong setting of data, so that the operation signal of virtual CPU thread 1 to the peripheral is disturbed, and read Or write out illegal data, or even not read the desired data at all. Therefore, when this virtual machine is executing in parallel and simulating a plurality of virtual CPU threads T ₁ , T ₂ , ..., T _n running simultaneously, if a virtual CPU thread is about to send an instruction to operate an I/O port, it first It must be detected whether other virtual CPU threads are performing I/O read and write operations. Further speaking, it is to detect whether the function of reading and writing operations on the virtual I/O bus is locked by other virtual CPU threads. If so, wait for it to release the ownership of the lock. If not or other virtual CPU threads have released the lock, then this The virtual CPU thread performs a locking operation on the lock. Then perform read and write operations. Release the lock after the operation is complete. This not only ensures that each I/O read and write operation can become an atomic operation without being interrupted by other operations, but also enables each virtual CPU thread to obtain I/O read and write rights through competition. A certain degree of fairness is guaranteed.

With regard to the atomic operation of the two memory access instructions, the present invention realizes by locking the memory for reading and writing after judgment. More specifically, an instruction with two memory accesses means that the operation of some instructions involves two reads and writes to the memory. Such as the INC instruction, if you want to perform an INC operation on the data of a certain memory address, the operation will first read the contents of the memory into the register of the CPU, then add one to the value in the register, and finally rewrite the new data Write to the original memory address. When this type of instruction involving two memory accesses is executed, if other instructions running on the virtual CPU thread also read and write the memory address, then either dirty data is read or the write is lost.

In order to prevent the occurrence of dirty data reading and write loss, the specific method adopted by the present invention is: at first judge whether the next instruction to be executed on the virtual CPU thread is an instruction of this type of two memory accesses, and if so, add memory read and write Lock, unlock the lock after the operation is completed. For other instructions that do not involve two accesses to memory, if they need to read and write memory, first check whether the memory read and write has been locked. If not, it means that no instruction involving two memory accesses is executed at this time, and it can be executed. If it is found that the memory read and write has been locked, it means that there is exactly one instruction designed to access memory twice at this time, so it will check and wait in place until the read and write lock of the memory is released, which involves two memory accesses. Until the instruction is executed, then continue normal execution. The present invention adopts the above method to prevent the atomic execution of instructions involving two memory accesses from being interrupted, and ensures that the operations of such instructions can be implemented correctly.

The present invention utilizes the method mentioned above to effectively control possible conflicts in accessing critical resources when virtual CPU threads are executed in parallel. Combined with the synchronization method of parallel virtual CPUs mentioned above, the present invention ensures logically correct execution of virtual machines after parallelization.

The entire system service process of the present invention is shown in FIG. 7 . If the user needs to use the parallel multi-processor virtual machine provided by the present invention. If you are using it for the first time, you should first edit the configuration script provided by the system to specify the model, number, memory size, disk size and specifications, virtual network address and other information of the processors to be simulated. Then install an operating system that supports SMP that meets user requirements for the virtual machine. Then the user directly starts the virtual machine of the present invention, and after the operating system in the virtual machine is started, the parallel virtual machine system can be used like any real computer.

If it is not used for the first time, the user can directly start the virtual machine of the present invention, and after the operating system in the virtual machine is started, the parallel virtual machine system can be tried out like any real computer.

If the user is dissatisfied with the virtual hardware configuration when using for the first time, the user can at first stop the execution of the virtual machine of the present invention, modify the configuration script provided by the system until each configuration meets the needs of the user, and restart the virtual machine. Can continue to use.

The virtual machine in the present invention will automatically execute the tasks assigned by the user to the virtual CPU in parallel on the real hardware server in units of virtual CPUs, thereby efficiently utilizing the computing resources of multiprocessors on the existing hardware to provide users with High performance service.

Claims (3)

1. A parallel multiprocessor virtual machine system, characterized by: the system comprises a virtual machine (1) and an operating system (2) in the virtual machine;

the operating system (2) in the virtual machine adopts an operating system supporting a symmetric multiprocessor and runs on the virtual machine (1);

the virtual machine (1) provides a virtual platform for a user, and comprises a processor parallel simulation module (11), a memory management module (12), an interrupt control simulation module (13) and a peripheral simulation module (14);

the processor parallel simulation module (11) is used for receiving an instruction submitted by the operating system (2) in the virtual machine, and executing the instruction after translation; if the instruction relates to memory reading and writing, the reading and writing operation signal is transmitted to a memory management module (12); sending an interrupt signal to an interrupt control module (13) if the processor parallel simulation module (11) is to process an interrupt;

the memory management module (12) is responsible for the read-write operation management of all memories, transmits the received peripheral port address to the peripheral simulation module (14) and feeds back the result of the read-write operation of the memories to the processor parallel simulation module (11);

the peripheral simulation module (14) is responsible for simulating all peripheral actions and responding to port access messages, and if an interrupt is to be triggered, an interrupt signal is sent to the interrupt control simulation module (13) for processing;

the interrupt control module (13) is responsible for controlling and managing interrupt signals in the virtual machine (1); it receives external interrupt signal from peripheral analog module (14) and executes interrupt operation with processor parallel analog module (11).

2. The system of claim 1, wherein: the processor parallel simulation module (11) comprises an instruction function table (111), a synchronous control module (112) and a virtual CPU thread module (113).

The virtual CPU thread module (113) is used for simulating the behavior of the CPU and constructing n virtual CPU threads T₁、T₂、……、T_nN is more than or equal to 1 and less than or equal to 17, and each virtual CPU thread corresponds to one physical CPU;

the query instruction function table (111) is used for storing a corresponding table of instructions and function functions;

the synchronization control module (112) coordinates the synchronous execution of all virtual CPU threads in cooperation with the virtual CPU thread module (113).

3. The system according to claim 1 or 2, characterized in that: the memory management module (12) comprises an address judgment module (121) and a memory access operation module (122); wherein,

the address judgment module (121) judges a physical address related to the read-write operation after receiving the read-write operation sent by the virtual CPU thread (1); if the address is a common memory address, the address is directly handed to the memory access operation module (122) to execute the memory access action; if the port address is the port address mapped by the peripheral equipment, the mapped port address is transmitted to the peripheral equipment simulation module (14), and after the peripheral equipment simulation module (14) acquires the corresponding port number, the peripheral equipment responding to the port is retrieved to execute read-write operation;

the memory access operation module (122) processes the read-write request of the virtual CPU thread and ensures the atomicity of two memory access instructions.

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