CN101174043B - Liquid crystal display device - Google Patents

Abstract

A multi-viewing zone liquid crystal panel includes a data line, a scan line and a pixel. Each pixel includes a first sub-pixel and a second sub-pixel, each having a first storage capacitor and a second storage capacitor. A first data switch selectively connects the first storage capacitor and the data line. A second data switch selectively connects the second storage capacitor and the data line. A first bias line is connected to the other end of the first storage capacitor; and a second bias line is connected to the other end of the second storage capacitor. When the scan line is enabled, the first data switch and the second data switch are turned on so that the signal of the data line is transmitted to the first sub-pixel and the second sub-pixel. Then, when the scan line is de-enabled, the potentials of the first bias line and the second bias line are changed respectively so that the pixel voltage of the first sub-pixel is slightly different from the pixel voltage of the second sub-pixel.

Description

Liquid crystal display device

technical field

The invention relates to a liquid crystal panel, in particular to a liquid crystal panel with low color difference and multiple viewing areas. the

Background technique

Generally, the viewing angle of an LCD screen is not large. When viewed at an oblique angle, the color of the screen will become incorrect. For large-screen LCD screens, there will be the disadvantage of different brightness between the center of the screen and the surrounding areas. Therefore, various manufacturers are committed to developing various wide-angle LCD screens, such as in-plane switching (In-Plane Switching, IPS) LCD screens, multi-view Vertical alignment (Multi-domain Vertical Alignment, MVA) LCD screen and so on. the

In a multi-view vertically aligned liquid crystal screen (MVA LCD), a pixel is divided into multiple viewing areas, and the alignment direction of the liquid crystal molecules in each viewing area is slightly different, so that there will not be too much difference when viewed from different angles. question. the

However, the displayed colors of the images of the multi-view LCD screen viewed from different angles still have slight differences, so there is still room for improvement in the image quality. the

In an existing driving method for solving chromatic aberration, a pixel in a liquid crystal panel is divided into two sub-pixels, and each sub-pixel is controlled by a thin film transistor, so slightly different driving voltages can be respectively input to the two sub-pixels of a pixel. pixels to improve the phenomenon of chromatic aberration. the

Contents of the invention

In view of this, the object of the present invention is to provide a low color difference multi-view LCD screen with improved picture quality. the

According to an object of the present invention, a liquid crystal panel is provided, including data lines, scan lines and pixels. Each pixel includes a first sub-pixel and a second sub-pixel, respectively having a first storage capacitor and a second storage capacitor. The first data switch selectively connects the first storage capacitor and the data line. The second data switch selectively connects the second storage capacitor and the data line. The first bias line is connected to the other end of the first storage capacitor; the second bias line is connected to the other end of the second storage capacitor. When the scan line is enabled, the first data switch and the second data switch are turned on, so that the signal of the data line is transmitted to the first sub-pixel and the second sub-pixel. Next, when the scan line is de-energized and before the scan line is enabled again, the potentials of the first bias line and the second bias line are changed once respectively, so that the pixel voltage of the first sub-pixel is the same as that of the second sub-pixel Pixel voltage is slightly different. the

In order to make the above-mentioned purpose, features, and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below, and is described in detail with reference to the accompanying drawings. the

Description of drawings

FIG. 1A shows a multi-view liquid crystal display module according to the first embodiment of the present invention. the

FIG. 1B shows an equivalent circuit diagram of a part of the liquid crystal panel. the

2A and 2B show signal waveform diagrams of the first sub-pixel and the second sub-pixel on the liquid crystal panel according to a first driving method, respectively. the

FIGS. 3A and 3B show signal waveform diagrams of the first sub-pixel and the second sub-pixel on the liquid crystal panel according to the second driving method, respectively. the

FIG. 4 shows an equivalent circuit diagram of a multi-view liquid crystal panel according to a second embodiment of the present invention. the

5A and 5B are diagrams showing signal waveforms for driving the first sub-pixel and the second sub-pixel on the liquid crystal panel according to a third driving method, respectively. the

6A and 6B show signal waveform diagrams of the first sub-pixel and the second sub-pixel on the liquid crystal panel 400 according to a fourth driving method, respectively. the

7A-7D show schematic diagrams of a liquid crystal screen with gate drivers driving bias lines. the

FIG. 8 is a schematic diagram of the first liquid crystal screen using logic circuits to drive bias lines. the

9A, 10A, 11A, and 12A show circuit diagrams of bias units, respectively. the

9B, 10B, 11B and 12B show various bias voltage units and corresponding signal waveform diagrams of the first sub-pixel and the second sub-pixel. the

13A-13C show layout diagrams of three types of pixels. the

FIG. 14A is a schematic diagram of the liquid crystal panel 100 of the first embodiment. the

Fig. 14B is a cross-sectional view along line AA' of the first liquid crystal panel structure. the

Fig. 14C is a cross-sectional view along line AA' of the second liquid crystal panel structure. the

Fig. 14D is a cross-sectional view along line AA' of the third liquid crystal panel structure. the

Fig. 14E is a cross-sectional view along line AA' of the fourth liquid crystal panel structure. the

FIG. 15A is a schematic diagram of a liquid crystal panel 400 of the second embodiment. the

15B-15E are cross-sectional views of various structures of the liquid crystal panel 400 . the

Description of reference symbols

100, 400: LCD panel

101: Pixels

700, 720, 740, 760, 800: LCD screen

710, 721, 722, 741, 742, 761, 762, 763, 764, 810: gate driver

820: Bias voltage generating circuit

822, 832, 842, 852, 862: Bias unit

Detailed ways

[First embodiment]

Please refer to FIG. 1A , which shows a multi-view liquid crystal display module according to the first embodiment of the present invention, which includes a liquid crystal panel 100 , a source driver 102 and a gate driver 104 . Wherein, the liquid crystal panel 100 includes n*m pixels 101, the source driver 102 transmits the display data to a plurality of pixels 101 through the data lines D(1)-D(n), and the gate driver 104 transmits the display data to a plurality of pixels 101 through the scan lines S(1)-D(n). S(m) transmits the scanning signal to the liquid crystal panel 100 to turn on the pixels of each row in sequence, and passes through the first bias lines B1(1)~B1(m) and the second bias lines B2(1)~B2(m) respectively The first bias signal and the second bias signal are transmitted to each pixel 101 on the liquid crystal panel 100 . the

Please refer to FIG. 1B , which shows an equivalent circuit diagram of a part of the liquid crystal panel 100 . It includes a plurality of pixels 101 arranged in a matrix, a first bias line B1 and a second bias line B2 arranged in parallel, a plurality of scanning lines S arranged in parallel, and a plurality of data lines D arranged in parallel, wherein the scanning line S , the first bias line B1 and the second bias line B2 are substantially parallel to each other and perpendicular to the data line D. Each pixel 101 corresponds to one data line D, one scan line S, one first bias line B1 and one second bias line B2. the

The pixel 101 includes a first sub-pixel 1011 and a second sub-pixel 1012 . The first sub-pixel 1011 includes a thin film transistor 10111, a storage capacitor C _st1 , and a parasitic capacitance C _gs1 formed between the gate and source of the thin film transistor 10111, wherein the gate of the thin film transistor 10111 is connected to the scanning line S(1), and the thin film The drain of the transistor 10111 is connected to the data line D(1), the source of the thin film transistor 10111 is connected to one end of the liquid crystal equivalent capacitor C _lc1 and one end of the storage capacitor C _st1 , the potential of the source of the thin film transistor 10111 is v _s1 , The other end of the liquid crystal equivalent capacitor C _lc1 is connected to the common electrode, the voltage on the common electrode is V _com , and the other end of the storage capacitor C _st1 is connected to the first bias line B1(1). The second sub-pixel 1012 includes a thin film transistor 10121, a liquid crystal equivalent capacitance _Clc2 , a storage capacitor C _st2 , and a parasitic capacitance C _gs2 formed between the gate and source of the thin film transistor 10121, wherein the gate of the thin film transistor 10121 is connected to the scanning Line S (1), the drain of the thin film transistor 10121 is connected to the data line D (1), the source of the thin film transistor 10121 is connected to one end of the liquid crystal equivalent capacitor C _lc2 and one end of the storage capacitor C _st2 , and the source of the thin film transistor 10121 The potential of the pole is v _s2 , the other end of the liquid crystal equivalent capacitor C _lc2 is connected to the common electrode, the voltage on the common electrode is V _com , and the other end of the storage capacitor C _st2 is connected to the first bias line B2 (1). The storage capacitor Cst1 of the first sub-pixel 1011 is formed by the source of the TFT 10111 and the first bias line B1(n), and the storage capacitor Cst2 of the second sub-pixel 1012 is formed by the source of the TFT 10121 and the first bias line B1(n). Two bias lines B2(n) are formed.

There are many ways to make the first sub-pixel and the second sub-pixel generate different pixel voltages. In this embodiment, only two examples are given for illustration. Please refer to FIG. 2A and FIG. Signal waveforms of the first sub-pixel 1011 and the second sub-pixel 1012 on the liquid crystal panel 100 in the first driving mode of the invention. Here, take the polarity switching method of dot inversion as an example, that is, in the same pixel, the polarities of the pixel voltages at adjacent frame times are different, and the polarities of the pixel voltages of adjacent pixels are different. Also different. Please refer to FIG. 2A and FIG. 2B at the same time. In the first frame time f1, at time t ₀ , the voltage of the first bias line B1(1) is V _bh , and the voltage of the second bias line B2(1) is V _bl , the voltage of the scanning line S(n) is V _gh , so that the thin film transistor 10111 is turned on and the thin film transistor 10121 is turned on, and the source driver 102 sends the display voltage V _d1 (not shown) through the data line D(1) to To the liquid crystal equivalent capacitance C _lc1 and the liquid crystal equivalent capacitance C _lc2 , due to the capacitive charging effect, the voltage difference v _dif1 between the two ends of the liquid crystal equivalent capacitance C _lc1 slowly changes to (V _d1 -V _com ), and the liquid crystal equivalent capacitance The voltage difference v _dif2 across C _lc2 gradually changes to (V _d1 -V _com ). At time _t1 , the voltage of the first bias line B1(1) is still V _bh , the voltage of the second bias line B2(1) is still V _bl , the voltage of the scan line S(n) is V _gl , The thin film transistor 10111 and the thin film transistor 10121 are turned off. At this instant, the voltage difference between the two ends of the parasitic capacitance C _gs1 and the parasitic capacitance C _gs2 needs to be kept constant, so that the voltage difference v _dif1 between the two ends of the liquid crystal equivalent capacitance C _lc1 is determined by (V _d1 -V _com ) is changed to (V _d1 -V _com -Δv _ft1 ), where ${\mathrm{\&Delta;<figure-callout\; id="1"\; label="v\; ft"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">v</figure-callout>}}_{\mathrm{ft}}=(V_{\mathrm{gh}}-V_{\mathrm{gl}})\&times;\frac{C_{\mathrm{gs}1}}{{\mathrm{<figure-callout\; id="1"\; label="C\; gs"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}+{\mathrm{<figure-callout\; id="1"\; label="C\; lc"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{lc}}+{\mathrm{<figure-callout\; id="1"\; label="C\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}},$ And the voltage difference v _dif2 across the liquid crystal equivalent capacitor C _lc2 changes from (V _d1 -V _com ) to (V _d1 -V _com -Δv _ft2 ), where ${\mathrm{\&Delta;<figure-callout\; id="2"\; label="v\; ft"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">v</figure-callout>}}_{\mathrm{ft}}=(V_{\mathrm{gh}}-V_{\mathrm{gl}})\&times;\frac{C_{\mathrm{gs}2}}{{\mathrm{<figure-callout\; id="2"\; label="C\; gs"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}+{\mathrm{<figure-callout\; id="2"\; label="C\; lc"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{lc}}+{\mathrm{<figure-callout\; id="2"\; label="C\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}},$ This phenomenon is called feed-through effect. At time _t2 , the voltage of the first bias line B1(1) changes from V _bh to V _bl , and the voltage of the second bias line B2(1) changes from V _bl to V _bh . The effect makes the voltage difference v _dif1 across the liquid crystal equivalent capacitance C _lc2 change from (V _d1 -V _com -Δv _ft1 ) to (V _d1 -V _com -Δv _ft1 -Δv _st1 ), where ${\mathrm{\&Delta;<figure-callout\; id="1"\; label="v\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">v</figure-callout>}}_{\mathrm{st}}=(V_{\mathrm{bh}}-V_{\mathrm{bl}})\&times;\frac{C_{\mathrm{st}1}}{{\mathrm{<figure-callout\; id="1"\; label="C\; gs"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}+{\mathrm{<figure-callout\; id="1"\; label="C\; lc"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{lc}}+{\mathrm{<figure-callout\; id="1"\; label="C\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}},$ And make the voltage difference v _dif2 across the liquid crystal equivalent capacitor C _lc2 change to (V _d1 -V _com -Δv _ft2 +Δv _st2 ), where

$\mathrm{<span\; class="notranslate">\; \&Delta;</span>}{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="v\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">v</figure-callout></span><figure-callout\; id="2"\; label="v\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; =</span><span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; bh</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; bl</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; \&times;</span>\frac{{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; st</span>}\mathrm{<span\; class="notranslate">\; 2</span>}}}{{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C\; gs"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="2"\; label="C\; gs"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C\; lc"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="2"\; label="C\; lc"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; <figure-callout\; id="2"\; label="C\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout></span><figure-callout\; id="2"\; label="C\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">\; </figure-callout>}}_{\mathrm{<span\; class="notranslate">\; </span>}}}<span\; class="notranslate">\; .</span>$

In the second frame time f2, at time _t3 , the voltage of the first bias line B1(1) is V _bl , the voltage of the second bias line B2(1) is V _bh , the scan line S(n) The voltage is V _gh , so that the thin film transistor 10111 and the thin film transistor 10121 are turned on, and the source driver 102 sends the display voltage V _d2 (not shown) to the liquid crystal equivalent capacitance C _lc1 and the liquid crystal equivalent through the data line D(1). Capacitor C _lc2 , due to the capacitive charging effect, the voltage difference v _dif1 across the liquid crystal equivalent capacitance C _lc1 gradually changes to (V _d2 -V _com ), and the voltage difference v _dif2 across the liquid crystal equivalent capacitance C _lc2 gradually changes is (V _d2 -V _com ). At time _t4 , the voltage of the first bias line B1(1) is V _bl , the voltage of the second bias line B2(1) is V _bh , and the voltage of the scanning line S(n) is V _gl , so that the film Transistor 10111 and TFT 10121 are turned off. At this moment, the voltage difference between the parasitic capacitance C _gs1 and the parasitic capacitance C _gs2 needs to be kept constant, so that the voltage difference v _dif1 between the two ends of the liquid crystal equivalent capacitance C _lc1 changes to (V _d2 -V _com -Δv _ft1 ), and the voltage difference v _dif2 across the liquid crystal equivalent capacitance _Clc2 is changed to (V _d2 -V _com -Δv _ft2 ). At time _t5 , the voltage of the first bias line B1(1) changes from V _bl to V _bh , and the voltage of the second bias line B2(1) changes from V _bh to V _bl . At this moment, the storage capacitor C The voltage difference between _st 1 and the storage capacitor C _st2 needs to be kept constant, so that the voltage difference v _dif1 between the two ends of the liquid crystal equivalent capacitor C _lc1 changes to (V _d2 -V _com -Δv _ft1 +Δv _st1 ), and the liquid crystal equivalent The voltage difference v _dif2 across the capacitor _Clc2 changes to (V _d2 -V _com -Δv _ft2 -Δv _st2 ).

In the first frame time f1, this driving method will make the voltage difference v _dif1 across the liquid crystal equivalent capacitance _Clc1 of the first sub-pixel 1011 be (V _d1 -V _com -Δv _ft1 -Δv _st1 ), and make the second The voltage difference v _dif2 across the liquid crystal equivalent capacitance C _lc2 of the sub-pixel 1012 is (V _d1 -V _com -Δv _ft2 +Δv _st2 ), so that the voltage difference across the liquid crystal equivalent capacitance of the first sub-pixel and the second sub-pixel Slightly different to achieve the effect of low chromatic aberration. Similarly, in the second frame time f2, this driving method will make the voltage difference v _dif1 across the liquid crystal equivalent capacitance _Clc1 of the first sub-pixel 1011 be (V _d2 -V _com -Δv _ft1 +Δv _st1 ), and The voltage difference v _dif2 across the liquid crystal equivalent capacitance _Clc2 of the second sub-pixel 1012 is (V _d1 -V _com -Δv _ft2 -Δv _st2 ), so the respective liquid crystals of the first sub-pixel 1011 and the second sub-pixel 1012 The voltage difference between the two ends of the equivalent capacitor is slightly different to achieve the effect of low color difference. It is worth noting that, during the first frame time f1 and the second frame time f2, the voltage difference between the respective liquid crystal equivalent capacitors of the first sub-pixel 1011 and the second sub-pixel 1012 is not only during charging and B1(1) and B2 (1) Except for changes when changing, the remaining time remains at a fixed value, so the stability of the picture can be maintained.

3A and 3B show signal waveform diagrams of the first sub-pixel and the second sub-pixel on the liquid crystal panel 100 according to the second driving method, respectively. The main difference between the second driving method and the first driving method is: the first driving method only changes the first bias line B1(1) and the second bias line B2(1) after the scan line S is disabled. state; and the second driving mode is to change the state of the first bias line B1(1) and the second bias line B2(1) when the scan line S is enabled and after it is de-energized. the

In the first frame time f1, at time t ₀ , the voltage of the first bias line B1(1) increases from V _com to V _bh , and the voltage of the second bias line B2(1) decreases from V _com to V _bl , the voltage of the scanning line S(n) is V _gh , so that the thin film transistor 10111 is turned on and the thin film transistor 10121 is turned on, and the source driver 102 sends the display voltage V _d1 (not shown) through the data line D(1) to To the liquid crystal equivalent capacitance C _lc1 and the liquid crystal equivalent capacitance C _lc2 , due to the capacitive charging effect, the voltage difference v _dif1 between the two ends of the liquid crystal equivalent capacitance C _lc1 slowly changes to (V _d1 -V _com ), and the liquid crystal equivalent capacitance The voltage difference v _dif2 across C _lc2 gradually changes to (V _d1 -V _com ). At time _t1 , the voltage of the first bias line B1(1) is still V _bh , the voltage of the second bias line B2(1) is still V _bl , the voltage of the scan line S(n) is V _gl , The thin film transistor 10111 and the thin film transistor 10121 are turned off, and at this moment, due to the tunneling effect, the voltage difference v _dif1 across the liquid crystal equivalent capacitance C _lc1 changes from (V _d1 -V _com ) to (V _d1 -V _com -Δv _ft1 ),in ${\mathrm{\&Delta;<figure-callout\; id="1"\; label="v\; ft"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">v</figure-callout>}}_{\mathrm{ft}}=(V_{\mathrm{gh}}-V_{\mathrm{gl}})\&times;\frac{C_{\mathrm{gs}1}}{{\mathrm{<figure-callout\; id="1"\; label="C\; gs"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}+{\mathrm{<figure-callout\; id="1"\; label="C\; lc"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{lc}}+{\mathrm{<figure-callout\; id="1"\; label="C\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}},$ And the voltage difference v _dif2 across the liquid crystal equivalent capacitor C _lc2 changes from (V _d1 -V _com ) to (V _d1 -V _com -Δv _ft2 ), where ${\mathrm{\&Delta;<figure-callout\; id="2"\; label="v\; ft"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">v</figure-callout>}}_{\mathrm{ft}}=(V_{\mathrm{gh}}-V_{\mathrm{gl}})\&times;\frac{C_{\mathrm{gs}2}}{{\mathrm{<figure-callout\; id="2"\; label="C\; gs"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}+{\mathrm{<figure-callout\; id="2"\; label="C\; lc"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{lc}}+{\mathrm{<figure-callout\; id="2"\; label="C\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}}.$ Later at time t2, the voltage of the first bias line B1(1) drops from V _bh to V _com , and the voltage of the second bias line B2(1) rises from V _bl to V _com . Therefore, the voltage difference v _dif1 across the liquid crystal equivalent capacitance C _lc2 is changed from (V _d1 -V _com -Δv _ft1 ) to (V _d1 -V _com -Δv _ft1 -Δv _st1 '), where $\mathrm{\&Delta;}{{\mathrm{<figure-callout\; id="1"\; label="v\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">v</figure-callout>}}_{\mathrm{st}}}^{\&prime;}=(V_{\mathrm{bh}}-V_{\mathrm{com}})\&times;\frac{C_{\mathrm{st}1}}{{\mathrm{<figure-callout\; id="1"\; label="C\; gs"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}+{\mathrm{<figure-callout\; id="1"\; label="C\; lc"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{lc}}+{\mathrm{<figure-callout\; id="1"\; label="C\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}},$ And make the voltage difference v _dif2 across the liquid crystal equivalent capacitance C _lc2 change to (V _d1 -V _com -Δv _ft2 +Δv _st2 '), where $\mathrm{\&Delta;}{{\mathrm{<figure-callout\; id="2"\; label="v\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">v</figure-callout>}}_{\mathrm{st}}}^{\&prime;}=(V_{\mathrm{com}}-V_{\mathrm{bl}})\&times;\frac{C_{\mathrm{st}2}}{{\mathrm{<figure-callout\; id="2"\; label="C\; gs"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{gs}}+{\mathrm{<figure-callout\; id="2"\; label="C\; lc"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{lc}}+{\mathrm{<figure-callout\; id="2"\; label="C\; st"\; filenames="H061E3267120061115E000011.png,H061E3267120061115E000021.png"\; state="\{\{state\}\}">C</figure-callout>}}_{\mathrm{st}}}.$

In the second frame time f2, at time _t3 , the voltage of the first bias line B1(1) decreases from V _com to V _bl , and the voltage of the second bias line B2(1) increases from V _com to V _bh , the voltage of the scanning line S(n) is V _gh , so that the thin film transistor 10111 is turned on and the thin film transistor 10121 is turned on, and the source driver 102 sends the display voltage V _d2 (not shown) through the data line D(1). To the liquid crystal equivalent capacitance C _lc1 and the liquid crystal equivalent capacitance C _lc2 , due to the capacitive charging effect, the voltage difference v _dif1 between the two ends of the liquid crystal equivalent capacitance C _lc1 slowly changes to (V _d2 -V _com ), and the liquid crystal equivalent capacitance The voltage difference v _dif2 across _Clc2 gradually changes to (V _d2 −V _com ). At time _t4 , the voltage of the first bias line B1(1) is still V _bl , the voltage of the second bias line B2(1) is still V _bh , the voltage of the scan line S(n) is V _gl , The thin film transistor 10111 and the thin film transistor 10121 are turned off. At this moment, due to the tunneling effect, the voltage difference v _dif1 between the two ends of the liquid crystal equivalent capacitance C _lc1 changes to (V _d2 -V _com -Δv _ft1 ), and the liquid crystal equivalent capacitance C _lc2 The voltage difference v _dif2 across both ends changes to (V _d2 -V _com -Δv _ft2 ). Later at time t5, the voltage of the first bias line B1(1) increases from V _bl to V _com , and the voltage of the second bias line B2(1) decreases from V _bh to V _com . Then the effect makes the voltage difference v _dif1 across the liquid crystal equivalent capacitance C _lc1 change to (V _d2 -V _com -Δv _ft1 +Δv _st1 '), and makes the voltage difference v _dif2 across the liquid crystal equivalent capacitance C _lc2 change to (V _d2 -V _com -Δv _ft2 -Δv _st2 ').

The above-mentioned first and second driving methods are to make the phase difference between the potentials of the first bias line B1(1) and the second bias line B2(1) 180 degrees, so that the first sub-pixel 1011 and the second sub-pixel 1012 have slightly different voltage differences across their respective liquid crystal equivalent capacitors to achieve low chromatic aberration. the

In addition to the 180 degrees mentioned in this embodiment, the phase difference between the first bias line B1(1) and the second bias line B2(1) can also be between 180 degrees and 360 degrees. Moreover, in one frame time, the number of switching times between the first bias line B1(1) and the second bias line B2(1) is one in this embodiment, but it may be more than two times. the

It is worth noting that, in the first frame time f1 and the second frame time f2, the voltage difference between the two ends of the respective liquid crystal equivalent capacitances of the first sub-pixel 1011 and the second sub-pixel 1012 changes during charging, and the other time Keep it at a fixed value, so you can maintain the stability of the picture. the

[Second embodiment]

Please refer to FIG. 4 , which shows an equivalent circuit diagram of a multi-view liquid crystal panel according to a second embodiment of the present invention. The liquid crystal panel 400 includes a plurality of pixels 401 arranged in a matrix, bias lines B arranged in parallel, a plurality of scanning lines S arranged in parallel, and a plurality of data lines D arranged in parallel, wherein the bias lines B and the scanning lines S are parallel They are arranged in a staggered manner and perpendicular to the data line D. The pixel 401 includes a data line D, a scan line S, and a bias line B correspondingly. the

The pixel 401 includes a first sub-pixel 4011 and a second sub-pixel 4012 . The first sub-pixel 4011 includes a thin film transistor 40111, a liquid crystal equivalent capacitor C _lc1 and a storage capacitor C _st1 . The second sub-pixel 4012 includes a thin film transistor 40121, a liquid crystal equivalent capacitor C _lc2 and a storage capacitor C _st2 .

The difference between the liquid crystal panel 400 of the second embodiment and the liquid crystal panel 100 of the first embodiment is that the liquid crystal panel 400 combines two adjacent bias lines B into one, that is, one bias line B of the liquid crystal panel 400 The voltage line B simultaneously adjusts the second sub-pixel of the upper pixel and the first sub-pixel of the lower pixel, so the number of bias voltage lines can be reduced by half. The voltage phases of the adjacent bias line B(n) and the bias line B(n+1) are different. the

FIGS. 5A and 5B show waveform diagrams of signals respectively driving the first sub-pixel and the second sub-pixel on the liquid crystal panel 400 according to a third driving method. The signal waveform ( FIG. 5A ) for driving the first sub-pixel 4011 according to the third driving method is the same as the signal waveform ( FIG. 2A ) for driving the first sub-pixel 1011 in the first embodiment. Herein No longer. the

The signal waveform for driving the second sub-pixel 4012 of the liquid crystal panel 400 according to the above-mentioned third driving method is shown in FIG. (FIG. 2B) The difference lies in the signal of the bias line B. In the first frame time f1, at time t ₀ , the voltage of the bias line B(n+1) is V _bl , and the voltage of the scan line S(n) is V _gh , so that the thin film transistor 40111 is turned on and the thin film transistor 40121 is turned on. conduction. At time _t1 , the voltage of the bias line B(n+1) is still V _bl , and the voltage of the scan line S(n) drops to V _gl , so that the thin film transistor 40111 and the thin film transistor 40121 are turned off. It should be noted that since the bias line B(n+1) still needs to adjust the first sub-pixel of the lower pixel, the voltage of the bias line B2 cannot be directly pulled up immediately after the scan line S(n) is de-energized as shown in Figure 2B. High, and after the scan line S(n+1) of the lower pixel is enabled and de-energized, the voltage of the bias voltage line B(n+1) rises from V _bl to V _bh at time t2'.

In the second frame time f2, at time _t3 , the voltage of the bias voltage line B(n+1) is V _bh , and the voltage of the scanning line S(n) is V _gh , so that the thin film transistor 40111 is turned on and the thin film transistor 40121 is turned on. conduction. At time _t4 , the voltage of the bias line B(n+1) is still V _bh , and the voltage of the scan line S(n) drops to V _gl , so that the thin film transistor 40111 and the thin film transistor 40121 are turned off. It should be noted that since the bias line B(n+1) still needs to adjust the first sub-pixel of the lower pixel, the voltage of the bias line B cannot be directly lowered immediately after the scan line S(n) is de-energized as shown in Figure 2B. , and the voltage of the bias line B(n+1) drops from V _bh to V _bl at time t5' after the scan line S(n+1) of the lower pixel is enabled and disabled.

6A and 6B show signal waveform diagrams of the first sub-pixel and the second sub-pixel on the liquid crystal panel 400 according to a fourth driving method, respectively. At the time f1 of the first frame, since the bias line B(n) still needs to adjust the second sub-pixel of the upper pixel, the bias line B( The voltage on n) changes from V _com to V _bh , after the scan line S(n) is deactivated, at time t2, the voltage on the bias line B(n) changes from V _com to V _bl ; the bias line The voltage on B(n+1) changes from V _com to V _bl at time t0, but the bias voltage line B(n+1) still needs to adjust the first sub-pixel of the lower pixel, so it needs to wait for the scan line S( The voltage on the bias line B(n+1) changes from V _bl to V _com at time t2' after n+1) de-energization. At the time f2 of the second frame, since the bias line B(n) still needs to adjust the second sub-pixel of the upper pixel, it is necessary to activate the scan line S(n-1) at time t3', the bias line B( The voltage on n) changes from V _com to V _bl , and after the scan line S(n) is deactivated, at time t5, the voltage on the bias line B(n) changes from V _bl to V _com ; the bias line The voltage on B(n+1) changes from V _com to V _bh at time t3, but the bias voltage line B(n+1) still needs to adjust the first sub-pixel of the lower pixel, so it needs to wait for the scan line S( The voltage on the bias line B(n+1) changes from V _bh to V _com at time t5' after n+1) de-energization.

[Method of driving bias line] 

Two ways of driving the bias line are disclosed here: by a gate driver or by a logic circuit, but those skilled in the art can use any other device or method to realize the required driving method of the present invention. 7A-7D show schematic diagrams of a liquid crystal screen with gate drivers driving bias lines. FIG. 7A is a schematic diagram of a first liquid crystal display panel 700 using a gate driver to drive bias lines. Here, only the liquid crystal panel 400 is taken as an example. The liquid crystal display 700 includes the aforementioned liquid crystal panel 400 and at least one gate driver 710 . The output potential of each pin of the gate driver 710 can be set separately, and is electrically connected to the corresponding scan line S or bias line B, so that these pins output the potential required by the scan signal S and the bias line B respectively. the

FIG. 7B is a schematic diagram of a second type of liquid crystal screen using a gate driver to drive bias lines. The liquid crystal screen 720 includes the above-mentioned liquid crystal panel 400 and gate drivers 721 and 722 . The gate driver 721 is used to generate the scan signal S, and the gate driver 722 is used to generate the potential required by the bias line B. As shown in FIG. the

FIG. 7C is a schematic diagram of a third liquid crystal screen using a gate driver to drive bias lines. The LCD screen 740 includes the above-mentioned LCD panel 400 and gate drivers 741 and 742 . The difference from the LCD screen 720 is that the gate driver 742 drives the bias line B from the other end of the panel. the

FIG. 7D is a schematic diagram of a fourth type of liquid crystal screen using a gate driver to drive bias lines. The liquid crystal screen 760 includes the above-mentioned liquid crystal panel 400 and gate drivers 761 , 762 , 763 and 764 . The gate drivers 761 and 763 jointly drive the bias line B from both ends of the liquid crystal panel 400 , and the gate drivers 762 and 764 jointly drive the scan line S from both ends of the liquid crystal panel 400 . the

Next, an LCD screen using logic circuits to drive bias lines will be described. FIG. 8 is a schematic diagram of the first liquid crystal screen using logic circuits to drive bias lines. The liquid crystal display 800 includes a gate driver 810 , a bias voltage generation circuit 820 and a liquid crystal panel 400 . The bias generating circuit 820 is formed on the glass substrate of the liquid crystal panel 400 . The gate driver 810 is used to drive the scan line S. As shown in FIG. The bias generating circuit 820 is used for driving the bias line B according to the scan line S. Referring to FIG. The bias generating circuit 820 includes a plurality of bias units, and each bias unit generates a voltage potential required by a corresponding bias line according to two adjacent scan lines. There are several methods for the bias voltage unit 822, four of which are briefly mentioned here as examples, as shown in FIGS. The voltage potential required to crimp the wire. the

Please refer to FIG. 9A , which shows a circuit diagram of the first bias unit, taking the bias unit 822 electrically connected to the scan lines S(n) and S(n+1) as an example. The bias unit 822 includes thin film transistors T1-T6 and a capacitor C. Please also refer to FIG. 9B , which shows the signal waveform diagram of the bias voltage unit 822 and the corresponding first sub-pixel and the second sub-pixel. At the time f1 of the first frame, the scan line S(n) is enabled so that the transistors T2, T5, and T6 are turned on, so the potentials on the bias lines B1(n) and B2(n) change to V _b1 and V The potential of _b2 . When the scanning line S(n) is disabled and the scanning line S(n+1) is enabled, the transistors T2, T5, and T6 are not conducting, and the transistors T1, T3, and T4 are conducting, so the bias line B1 ( The potential on n) and B2(n) changes to V' _com . V' _com V' _com may also be the voltage V _com of the common electrode.

If the polarity switching method of dot inversion is used, the voltages V _b1 and V _b2 need to change their polarities with each screen switching. In addition, one of the voltages V _b1 and V _b2 can be equal to the voltage V' _com : if the voltage V _b1 is equal to V' _com , the transistors T3 and T5 can be removed; if the voltage Vb2 is equal to V' _com , the transistors T4 and T6 can be removed .

Please refer to FIG. 10A , which shows a circuit diagram of the second bias unit, taking the bias unit 832 electrically connected to the scan lines S(n) and S(n+1) as an example. The bias unit 832 includes thin film transistors T1 and T2 and capacitors C1 and C2. Please also refer to FIG. 10B , which shows the signal waveform diagram of the bias voltage unit 832 and the corresponding first sub-pixel and the second sub-pixel. At the first frame time f1, the scanning line S(n) is enabled, and the transistors T1 and T2 are not conducting at this time, so the potentials of the bias voltage lines B1(n) and B2(n) are respectively equal to those of the previous frame time f0 The potentials of V _b1 and V _b2 . When the scanning line S(n+1) is enabled, the transistors T1 and T2 are turned on, so the potentials on the bias voltage lines B1(n) and B2(n) change to V _b1 and V at the first frame time f1 respectively. _b2 .

If the polarity switching method of dot inversion is used, the voltages V _b1 and V _b2 need to switch their polarities with each frame: the polarity of V _b1 at the time f0 of the previous frame is different from that of V _b1 at the time f1 of the first frame ; The polarity of V _b2 of the previous frame time f0 is different from that of V _b2 of the first frame time f1. In addition, one of the voltages V _b1 and V _b2 can be equal to the voltage V _com : if the voltage Vb1 is equal to V _com , the transistor T1 and the capacitor C1 can be removed; if the voltage Vb2 is equal to V _com , the transistor T2 and the capacitor C2 can be removed.

Please refer to FIG. 11A , which shows a circuit diagram of the third bias unit, taking the bias unit 842 electrically connected to the scan line S(n) as an example. The bias unit 842 includes thin film transistors T1 - T4 , wherein the transistors T1 and T2 are always turned on and serve as resistors. Please also refer to FIG. 11B , which shows the signal waveform diagram of the bias voltage unit 842 and the corresponding first sub-pixel and the second sub-pixel. At the time f1 of the first frame, the scanning line S(n) is enabled so that the transistors T3 and T4 are turned on, so the potentials of the bias lines B1(n) and B2(n) are changed to the potentials of V _b1 and V _b2 respectively . When the scanning line S(n) is de-energized and the scanning line S(n+1) is enabled, the transistors T3 and T4 are not conducting, so the potentials of the bias voltage lines B1(n) and B2(n) change to V ' _com .

If the polarity switching method of dot inversion is used, the voltages V _b1 and V _b2 need to switch their polarities with each frame: the polarity of V _b1 at the time f0 of the previous frame is different from that of V _b1 at the time f1 of the first frame ; The polarity of V _b2 of the previous frame time f0 is different from that of V _b2 of the first frame time f1. In addition, one of the voltages V _b1 and V _b2 can be equal to the voltage V' _com : if the voltage V _b1 is equal to V' _com , the transistors T2 and T4 can be removed; if the voltage V _b2 is equal to V' _com , the transistors T1 and T3 can be removed remove.

Please refer to FIG. 12A , which shows a circuit diagram of the fourth bias unit, taking the bias unit 852 electrically connected to the scan lines S(n) and S(n+1) as an example. The bias unit 852 includes thin film transistors T1-T4. Please also refer to FIG. 12B , which shows the signal waveform diagram of the bias voltage unit 852 and the corresponding first sub-pixel and the second sub-pixel. At the time f1 of the first frame, the scanning line S(n) is enabled so that the transistors T3 and T4 are turned on, so the potentials of the bias lines B1(n) and B2(n) are changed to the potentials of V _b1 and V _b2 respectively . When the scanning line S(n) is de-energized and the scanning line S(n+1) is enabled, the transistors T3 and T4 are non-conducting, the transistors T1 and T2 are conducting, and the bias lines B1(n) and B2( The potential of n) changes to V' _com .

If the polarity switching method of dot inversion is used, the voltages V _b1 and V _b2 need to be switched every frame. In addition, one of the voltages V _b1 and V _b2 can be made equal to the voltage V' _com : if the voltage V _b1 is equal to V' _com , then the transistor T1 and the transistor T3 can be removed, and B1(n) is directly connected to V'_com; if the voltage Vb2 is equal to Vcom', then transistor T2 and transistor T4 can be removed, and B2(n) is directly connected to V' _com .

[Pixel Layout]

In the first embodiment and the second embodiment, a pixel is divided into a first sub-pixel Pa and a second sub-pixel Pb. The layout of the first sub-pixel Pa and the second sub-pixel Pb can be in any shape, which is omitted here An example is as follows. FIG. 13A shows the layout of the first pixel, in which the first sub-pixel Pa and the second sub-pixel Pb share the upper and lower parts of the pixel, and each of the first sub-pixel Pa and the second sub-pixel Pb includes a TFT. 13B is a layout diagram of the second type of pixel, wherein the first sub-pixel Pa is in the middle of the pixel, the second sub-pixel Pb surrounds the first pixel Pa, and each of the first sub-pixel Pa and the second sub-pixel Pb includes a TFT . 13C is a layout diagram of the third type of pixel, wherein the first sub-pixel Pa is trapezoidal, and the rest is the second sub-pixel Pb, and each of the first sub-pixel Pa and the second sub-pixel Pb includes a TFT. the

13A-13C above are just a few layout examples, however, those skilled in the art can use layouts of other shapes to realize the pixel structure of the present invention. the

[Pixel structure diagram]

The liquid crystal panel 100 of the above-mentioned first embodiment may have several structures, four of which are briefly described here as examples. FIG. 14A is a schematic diagram of the liquid crystal panel 100 of the first embodiment. 14B to 14E are cross-sectional views of various structures of the liquid crystal panel 100 . Fig. 14B is a cross-sectional view along line AA' of the first liquid crystal panel structure. The liquid crystal panel 100 includes an upper substrate 10 , a common electrode 12 , a lower substrate 11 , transparent electrodes 13 , 14 , and a first layer of metal M1 and a second layer of metal M2 . The two second-layer metals M2 are respectively used to couple the transparent electrodes 13 and 14 to the data lines. The two first-layer metals M1 constitute the bias lines B1 and B2. The first metal layer M1 and the corresponding second metal layer M2 form a storage capacitor Cst. the

14C is a cross-sectional view of the second liquid crystal panel structure along line AA', which differs from the first structure in that the transparent electrodes 13 and 14 are electrically connected to the first metal layer M1, while the second metal layer M2 The bias lines B1 and B2 are formed. Fig. 14D is a cross-sectional view of the third liquid crystal panel structure along line AA', which differs from the first structure in that the first metal layer M1 is further electrically connected to the transparent electrodes 15 and 16 to increase the storage capacity Cst capacitance value. Fig. 14E is a cross-sectional view along line AA' of the fourth liquid crystal panel structure, which differs from the first structure in that the second metal layer is missing. the

The above-mentioned liquid crystal panel 400 in the second embodiment may have several structures, four of which are briefly described here as examples. FIG. 15A is a schematic diagram of a liquid crystal panel 400 of the second embodiment. 15B to 15E are cross-sectional views of various structures of the liquid crystal panel 400 . FIG. 15B is a cross-sectional view of the first structure of the liquid crystal panel 400 along line AA'. The liquid crystal panel 400 includes an upper substrate 10 , a common electrode 12 , a lower substrate 11 , transparent electrodes 13 , 14 , and a first layer of metal M1 and a second layer of metal M2 . The two second-layer metals M2 are respectively used to couple the transparent electrodes 13 and 14 to the data lines. The first layer of metal M1 constitutes the bias line B. The first metal layer M1 and the corresponding second metal layer M2 form a storage capacitor Cst. the

15C is a cross-sectional view of the second liquid crystal panel structure along line AA', which differs from the first structure in that the transparent electrodes 13 and 14 are electrically connected to the first metal layer M1, while the second metal layer M2 Constitute the bias line B. 15D is a cross-sectional view of the third liquid crystal panel structure along line AA', which differs from the first structure in that the first metal layer M1 is further electrically connected to the transparent electrode 15 to increase the capacitance value of the storage capacitor Cst . Fig. 15E is a cross-sectional view along line AA' of the fourth liquid crystal panel structure, which differs from the first structure in that the second metal layer is missing. the

The above embodiments can make the multiple sub-pixels in one pixel of the multi-view liquid crystal panel have slightly different driving voltages, so as to reduce the chromatic aberration and improve the stability and display quality of the picture. the

In summary, although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention, and those skilled in the art can make various modifications without departing from the spirit and scope of the present invention. and retouching, so the protection scope of the present invention shall be determined by the claims of the present invention. the

Claims (13)

1. A liquid crystal panel, comprising: a data line formed on the liquid crystal panel in a first direction; a scanning line formed on the liquid crystal panel in a second direction, the first direction being perpendicular to the second direction; A pixel is formed at the intersection of the data line and the scan line, including: A first sub-pixel includes a first switch, a first liquid crystal capacitor and a first storage capacitor, wherein a first end of the first switch is connected to the scanning line, a second end of the first switch connected to the data line, a third terminal of the first switch is connected to a first terminal of the first liquid crystal capacitor and a first terminal of the first storage capacitor; and A second sub-pixel includes a second switch, a second liquid crystal capacitor and a second storage capacitor, wherein a first end of the second switch is connected to the scanning line, a second end of the second switch connected to the data line, a third terminal of the second switch is connected to a first terminal of the second liquid crystal capacitor and a first terminal of the second storage capacitor; a first bias line electrically connected to a second end of the first storage capacitor; and a second bias line electrically connected to a second end of the second storage capacitor; Wherein, when the scanning line is enabled, the first switch and the second switch are turned on, so that the signal of the data line is transmitted to the first sub-pixel and the second sub-pixel, and then, when the scanning line After de-energizing and before the scanning line is enabled again, the potentials of the first bias line and the second bias line are respectively changed once, so that the pixel voltage of the first sub-pixel is the same as the pixel voltage of the second sub-pixel The voltage is different. 2. The liquid crystal panel as claimed in claim 1, wherein the first bias line is at a first potential before the scanning line is enabled, and is also at the first potential when it is enabled, and then changes to a first potential after de-energizing two potentials. 3. The liquid crystal panel as claimed in claim 1, wherein the second bias line is at a third potential before the scanning line is enabled, and is also at the third potential when enabled, and then changes to a first potential after deactivation Four potentials. 4. The liquid crystal panel as claimed in claim 1, wherein the first bias line is at a first potential before the scanning line is enabled, and changes to a second potential when it is enabled, and then changes to the first potential after it is de-energized. a potential. 5. The liquid crystal panel as claimed in claim 1, wherein the second bias line is at a third potential before the scanning line is enabled, and changes to a fourth potential when it is enabled, and then changes to the first potential after it is de-energized. Triple potential. 6. The liquid crystal panel as claimed in claim 1, wherein the liquid crystal panel comprises a first gate driver and a second gate driver, the first gate driver is used to drive the scanning line, and the second gate driver Used to drive the first bias line and the second bias line. 7. The liquid crystal panel as claimed in claim 1, wherein the liquid crystal panel comprises a first gate driver, a second gate driver, a third gate driver and a fourth gate driver, the first gate The driver and the second gate driver are located on opposite sides of the liquid crystal panel for jointly driving the scanning lines, and the third gate driver and the fourth gate driver are located on opposite sides of the liquid crystal panel for jointly driving the The first bias line and the second bias line. 8. The liquid crystal panel as claimed in claim 1 , comprising a plurality of scan lines, defined as a first scan line and a second scan line, and a plurality of corresponding pixels, defined as a first pixel and a second pixel, the The first pixel and the second pixel are vertically arranged; Wherein, the second bias line is shared by the second sub-pixel of the first pixel and the first sub-pixel of the second pixel. 9. The liquid crystal panel as claimed in claim 8, further comprising a bias generating circuit formed on the substrate of the liquid crystal panel to drive the first bias line according to the first scanning line and the second scanning line and the second bias line. 10. The liquid crystal panel as claimed in claim 9, wherein the bias generating circuit comprises at least one bias unit electrically connected to the first scanning line and the second scanning line, and connected to the first bias line and the The second bias line is electrically connected. 11. The liquid crystal panel as claimed in claim 1, wherein the potentials of the first bias line and the second bias line have a phase difference of 180 to 360 degrees. 12. A liquid crystal panel, comprising: a data line formed on the liquid crystal panel in a first direction; a scanning line formed on the liquid crystal panel in a second direction, the first direction being perpendicular to the second direction; A pixel is formed at the intersection of the data line and the scan line, including: A first sub-pixel includes a first switch, a first liquid crystal capacitor and a first storage capacitor, wherein a first end of the first switch is connected to the scanning line, a second end of the first switch connected to the data line, a third end of the first switch is connected to a first end of the first liquid crystal capacitor and a first end of the first storage capacitor; and a second sub-pixel, including a second switch, a second liquid crystal capacitor, and a second storage capacitor, wherein a first end of the second switch is connected to the scan line, a second end of the second switch is connected to the data line, and the second switch A third terminal of the second liquid crystal capacitor is connected to a first terminal of the second storage capacitor and a first terminal of the second storage capacitor; a first bias line electrically connected to a second end of the first storage capacitor; and a second bias line electrically connected to a second end of the second storage capacitor; Wherein, when the scanning line is enabled, the first switch and the second switch are turned on, so that the signal of the data line is transmitted to the first sub-pixel and the second sub-pixel, and then, when the scanning line After de-energizing and before the scanning line is enabled again, the potentials of the first bias line and the second bias line are respectively changed once, so that the pixel voltage of the first sub-pixel is the same as the pixel voltage of the second sub-pixel The voltage is slightly different. 13. A liquid crystal display comprising: a source driver; a gate driver for outputting a scanning signal; a bias generating circuit, outputting a first bias signal and a second bias signal according to the scan signal; and A liquid crystal panel, comprising: a data line formed on the liquid crystal panel in a first direction and electrically connected to the source driver; A scanning line is formed on the liquid crystal panel in a second direction, the first direction is perpendicular to the second direction, and receives the scanning signal; A pixel is formed at the intersection of the data line and the scan line, including: A first sub-pixel includes a first switch, a first liquid crystal capacitor and a first storage capacitor, wherein a first end of the first switch is connected to the scanning line, a second end of the first switch connected to the data line, a third terminal of the first switch is connected to a first terminal of the first liquid crystal capacitor and a first terminal of the first storage capacitor; and A second sub-pixel includes a second switch, a second liquid crystal capacitor and a second storage capacitor, wherein a first end of the second switch is connected to the scanning line, a second end of the second switch connected to the data line, a third terminal of the second switch is connected to a first terminal of the second liquid crystal capacitor and a first terminal of the second storage capacitor; a first bias line, receiving the first bias signal, electrically connected to a second end of the first storage capacitor; and a second bias line, receiving the second bias signal, electrically connected to a second end of the second storage capacitor; Wherein, when the scanning line is enabled, the first switch and the second switch are turned on, so that the signal of the data line is transmitted to the first sub-pixel and the second sub-pixel, and then, when the scanning line After de-energizing and before the scanning line is enabled again, the potentials of the first bias signal and the second bias signal are changed once respectively, so that the pixel voltage of the first sub-pixel is the same as the pixel voltage of the second sub-pixel The voltage is slightly different.

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