CN101169974B

CN101169974B - Operation method of multi-level storage unit memory device and integrated circuit using the method

Info

Publication number: CN101169974B
Application number: CN2007101668848A
Authority: CN
Inventors: 何文乔; 张钦鸿; 刘正淇; 张坤龙; 洪俊雄
Original assignee: Macronix International Co Ltd
Current assignee: Macronix International Co Ltd
Priority date: 2006-10-23
Filing date: 2007-10-23
Publication date: 2011-03-30
Anticipated expiration: 2027-10-23
Also published as: CN101169974A

Abstract

A method for determining read voltage margin in a memory array compares a read sum code generated from data read from the memory array to an expected sum code generated from loaded data. The read voltage (Vt) is stepped and the read sum code is compared to the desired sum code to determine the Vt range that provides a match to the sum code. Read voltage margins (i.e., read voltage margins between program levels of the MLC memory array) are determined in parallel as Vt steps across its range.

Description

The method of operating of multi-level cell memory memory device and use the integrated circuit of this method

Technical field

The invention relates to memory device based on MLC (" MLC "), and particularly relevant in order to read the technology of MLC formula memory device.

Background technology

Known flash cell stores floating grid structure or the constructional electric charge of other Charge Storage.Interior accumulate lotus changes the threshold voltage (Vth) of this internal storage location.Read in the action one, one reads voltage is applied in the grid of internal storage location so far, and the whether conducting (for example conduction current) of this internal storage location, and the perhaps magnitude of current that is conducted is represented the programming state of this internal storage location.For example, the digital numerical value that an internal storage location of the quite high electric current of conduction may designated " 1 " during reading action, and conduction is very little or do not have a digital numerical value that an internal storage location of transmission current may designated " 0 " during reading action.Electric charge be added to this Charge Storage structure and from then on the Charge Storage structure be removed, in order to programming with wipe this internal storage location, that is, this storage values is changed to 0 from 1.This electric charge is by this Charge Storage structure and kept, and till this internal storage location is wiped free of, keeps this data mode not needing to apply continuously under the situation of electric power, is very welcome for flash memory is used.

Can to the Charge Storage structure, represent that the MLC of (storage) a plurality of data values develops gradually by the electric charge that the different quantity of selectivity is provided.Basically, a little negative charge increases the Vth of internal storage location slightly, and more negative charges further increase Vth.One reads action is recharged (programming) in order to determine this internal storage location for which kind of state.For example, in storing 2 four level-cells of data, suppose Vth ₀Be illustrated in the threshold voltage that MLC was not programmed or was wiped free of (it can be not have electric charge in essence at the constructional state of Charge Storage), Vth ₁Be illustrated in quite a spot of negative charge and be transferred to the threshold voltage of Charge Storage when textural, Vth ₂Be illustrated in more negative charges and be transferred to the threshold voltage of Charge Storage when textural, and Vth ₃Be illustrated in more negative charges and be transferred to the threshold voltage of Charge Storage when textural.Be applied to Vth ₀With Vth ₁Between one read (word wired-OR gate) voltage and, will represent that whether this device is programmed, then, is applied to Vth through installing current sensor thus ₁With Vth ₂Between a word line voltage and this device conducting whether of sensing, will represent that this installs whether to be programmed to first level or second level or the like.Perhaps, apply a fixing word line voltage, and the electric current that this element conducted and three reference currents compare simultaneously.Mode can read all four level of this MLC of sensing in the action at one according to this.

Memory array in conjunction with MLC reads with well-known way usually, this well-known way is to apply one to read voltage (Vt) to a selection word line, sensing is coupled to the curtage on the bit line of MLC block then, and the MLC block is by using row's sensing amplifier and being started by word line.Typically reading action is page formula.For example, the memory device (or the memory array among the IC) of two kilomegabits (" 2Gb ") can be designed to 128,000 two kilobyte (" the 2KB ") page.The numerical value of institute's sensing is loaded on a data latches or impact damper, as it is known to be familiar with the technician of flash memory device.For example, see also No. the 6th, 538,923, the United States Patent (USP) that licenses to Parker on March 25th, 2003.One page then is programmed and reads with the sequence of operation on the block of the number that mates sensing amplifier.Sensing amplifier comprises a benchmark under the situation that reads action continuously of a plurality of level, or in order to read in parallel one group of benchmark of these a plurality of level, the voltage of this bit line or electric current be benchmark or this group benchmark comparison therewith, uses the Vth that detects this element, thereby detects this internal storage state.

Yet the Vth of these unit that are programmed to a particular memory state in an array and in the array of single page can spread all in the distribution of threshold voltage and changes.Therefore, be applied in to read one of a MLC and read voltage or be used for the reference current of output current of sensing one MLC, within the spacing between the Vth voltage that must drop in a plurality of program level distributes.This kind spacing is to read voltage range or read margining is represented.Confirm that the MLC device has that enough to read voltage range be very important.

The known technology of read margining on border of distribution of searching each Vth level of each page be positioned at each program level in order to decision is time-consuming and uses a lot of storage volumes (tester internal memory) so that the data that read from chip for different program level logins.Therefore, need a kind of technology that can avoid the problem of these known technologies in order to the decision read margining.

Summary of the invention

According to the present invention, a kind of method of operation one memory array is proposed, memory array comprises MLC, and every unit stores a plurality of positions.The method was crossed the read margining of a plurality of threshold levels of this array in order to decision, and comprise following steps: carry out a programming operation and combine in a tested block in this array to store a given data, and each unit in this tested block stores one yard in one group of a plurality of bit code, wherein organizes each bit code in a plurality of bit codes at this and corresponds to and can be programmed in one of a plurality of threshold levels in this element.About 2 bit codes, this organizes a plurality of bit codes four 2 bit codes, and four threshold levels that are used in internal storage location are to represent this four sign indicating numbers.A plurality of bit codes of concentrating in given data comprise corresponding to a first threshold level and with as be illustrated in the sign indicating number of the known sum that this an expectation sum code represents, and corresponding to sign indicating number of the known sum of one second threshold level or the like.After carrying out this programming operation, use one first word line voltage to read this tested block, decision expression be programmed to one first program level one first internal storage location number one first read summation, and the decision expression be programmed to second program level one second number the unit one second read summation.First read sum code with about the first known sum of first threshold level relatively, and second read sum code with about the second known sum of second threshold level relatively, in order to the sum code comparison information to be provided.Word line voltage reaches the voltage of a particular range with the stepped variation of little increment, or reaches the stepped variation of a part of this particular range, and reading sum code and/or comparison information is each stair-stepping voltage login.In a specific embodiment, word line voltage system reaches the word line voltage of a particular range, for example with the stepped variation of the step of 100mV.Read sum code and/or comparison information about the login of the word line voltage of this scope, in order to the read range of decision between first program level and second program level, wherein this read range is the word line voltage of certain limit, and in this scope, the word line voltage level that is applied produces several sum code, and these sum code and the known sum within the tested block of this array are complementary.

In a specific embodiment, this memory array comprises the MLC (" MLC ") of two positions, every unit, and data set has one the 3rd known sum corresponding to the sign indicating number of one the 3rd threshold level.In the case, the first known sum expression is programmed to a plurality of MLC of first program level, second program level or the 3rd program level, and the second known sum expression is programmed to a plurality of MLC of second program level or the 3rd program level.Read sum code and second and read to calculate one the 3rd again and read sum code the sum code except first.The 3rd has read one the 3rd MLC number that sum code represents to be positioned at the 3rd program level, first has read sum code represents that one the one MLC that is positioned at first program level, second program level and the 3rd program level reads number, and second has read sum code and represent that one the 2nd MLC that is positioned at second program level and the 3rd program level reads number.First has read sum code and the first known sum is made comparisons, and second has read sum code and the second known sum is made comparisons, and the 3rd read sum code and the 3rd known sum is made comparisons, in order to the first sum code comparison information to be provided.

In a specific embodiment, the tested block of unit is MLC (" the MLC ") memory device of a page, or an another part that reads a memory array theme of action, and a page read range uses sum code and/or comparison information and determines between first program level and second program level.Page read range is that afterwards the page reads action and stores.Perhaps, the tested block of memory array is the part of the MLC memory device of a page.

In a specific embodiment, the tested block of memory array is a kind of two kilobyte (2 ¹⁴The position) page is read sum code and is comprised 15＜0:14〉about being stored in each the N-1 level in the N level-cell.Therefore,, can produce three and read sum code, and, can produce three 15 for each page of data (the 2K byte page stores the 16K position) that adds up to 45 and read sum code for the 2K byte page for four level-cells.Therefore, more general speech is for comprising 2 ^N-1The test block of position, first has read sum code, second has read sum code and the 3rd and has read sum code and comprise each N bit code.Use for the analysis that tolerance limit is tested or margin search is used, as be illustrated in this place in this group N bit code, but not in this group 2 ^N-1Finish on the data of position, reduce the needed memory source of test processes in fact.

Sum code and/or comparison information are also selectively in order to confirm correct programming operation.For example, be lower than expectation (known) sum code if read sum code, then can be with another program pulse application selecteed internal storage location in the memory array so far, and read new sum code, and new sum code and expectation sum code are made comparisons.

The technology that is applied to this also is suitable for single level-cell formula memory array.

In a specific embodiment, read the step that the every unit that is positioned at first word line voltage comprises the MLC memory array of two positions, comprise the cell current and a first reference value, one second reference value and one the 3rd reference value that compare an internal storage location simultaneously, to produce two bits output, a programming state of its indication internal storage location.

In one embodiment, integrated circuit (" IC ") with a MLC memory array comprises a built-in self-test (" BIST ") design (comprising logic), a for example state machine and other special circuit, a processor of being controlled by software or the combination of processor and special circuit, it is designed in order to operate this MLC memory array according to above-mentioned technology.In a specific embodiment, the BIST logic provides one to pass through/failure result to a tester from IC, and this IC indicates any page in this array whether to meet specific minimum read margining.

For foregoing of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below:

Description of drawings

Fig. 1 shows that the Vth of a plurality of threshold levels of the MLC product of example distributes.

Fig. 2 A shows the threshold voltage cell distribution of the MLC internal memory product of two different pages.

Fig. 2 B shows the known method that reads voltage range of decision MLC formula internal memory.

Fig. 3 shows the chart that is used for illustrating the sum code generation.

Fig. 4 is the process flow diagram according to the method for operating of the MLC formula memory array of one embodiment of the invention.

Fig. 5 A is the example according to the sensing structure of an embodiment.

Fig. 5 B shows the example sum code calculation block 520 according to an embodiment.

Fig. 5 C shows the sum code comparison information about the MLC internal memory of the page in an IC.

Fig. 6 shows the exemplary plot of test macro that has the IC of BIST logic in order to test.

[primary clustering symbol description]

L0, L1, L2, L3: curve/level

100: figure

102: the one Vt tolerance limits

104: the two Vt tolerance limits

106: the three Vt tolerance limits

200: method

204,206,208,210: curve

212,214,216,218: distribute

220,222,224,226,230,234,238,240,242: step

228,232: circulation

411: method of operating

412,414,416,418,420,424,428: step

500: sensing structure

The 502:MLC unit

504A: load circuit

504B: clamp circuit

512: the data computation block

Comparer stored body in 522: the first

Comparer stored body in 524: the second

Comparer stored body in 526: the three

528: first adder

530: working storage

534: second adder

536: the 2 16 working storages

538: the three totalizers

540: the 3 16 working storages

600: test macro

602：IC

604A, 604B, 604C: selftest BIST logic

The 606:MLC memory array

Embodiment

Please refer to Fig. 1-6, the detailed description of the technology of searching about the read margining in the MLC formula memory array is provided.

Fig. 1 be show every unit store two positions an example the MLC product read Figure 100 that voltage Vt distributes.The longitudinal axis is illustrated in the number of unit in the memory array that is programmed to a threshold level, and transverse axis is the Vt that is applied to these word lines of these MLC, and it will overcome the constructional transmission charge of this Charge Storage of this element and allow this element conduction current.Four distributions are shown as level L0, L1, L2, L3 (state or data value).For convenience of the purpose of discussing, level L0 represents a digital data value of 11, and L1 represents a digital data value of 10, and L2 represents a digital data value of 01, and L3 represents a digital data value of 00; Yet these performances are selectable, and other numerical value definition also is possible.

The state of MLC (numerical value) can read the voltage word line of MLC so far by applying one, and determines via this element current sensor.For example, if this MLC is programmed to threshold level L1, L2 or L3, then in one the one Vt tolerance limit 102 (for example REF1) one read voltage will be can this MLC of conducting (that is, arrive and will conduct to the state of a bit line at the electric current on the reference level) via this element.When an electric current and the benchmark of MLC are made comparisons (for example carrying out by a sensing amplifier) thus, the user knows that MLC is positioned at minimum level L0 (it often represents an erase unit).Utilize a similar mode, in the Vt scope (Window) of the 2nd Vt tolerance limit 104 and the 3rd Vt tolerance limit 106, apply voltages to this word line and distinguish level L1 and L2, and level L2 and L3.

Fig. 2 A shows the threshold voltage distribution of two different pages of a MLC internal memory product.Curve L0, L1, L2, L3 represent the distribution of the threshold voltage of this chip in particular range.Curve 204,206,208 and 210 is represented about different program level, found distribution of reading voltage in the page in this chip.For example, the page 0 (" P0 ") has the distribution 204 about the threshold voltage of level L0, and about the distribution 206 of the threshold voltage of level L1.In the L0 on the P0 and the Vt scope (read range) between the L1 is the voltage differences WL_01_P0 between the lower boundary of 204 high border and distribution 206 of distributing.Similarly, WL_12_P0 is illustrated in the Vt scope between the lower boundary of distribution 208 of threshold voltage of the high border of distribution 206 of threshold voltage of level L1 and the level L2 on the P0, and WL_23_P0 is illustrated in the high border about the distribution 208 of the threshold voltage of level L2, and about the Vt scope between the lower boundary of the distribution 210 of the threshold voltage of the level L3 on the P0.

Second page P4 has the different distributions 212,214,216,218 of each level L0, L1, L2, L3.As mentioned above, these Vt scopes of P4 are WL_01_P4, WL_12_P4 and WL_23_P4.Simplify in the example at this, the narrowest read range of any page between any two level is WL_12_P0.MLC internal memory product generally has a minimum read range specification (for example 300mV).If WL_12_P0 is less than this minimum read range specification (that is less than 300mV), then this product test is failed.The different pages in the one MLC internal memory product may and necessarily have different Vt scopes usually, and have the different voltage ranges that read between the numerical value of different groups.

Known read margining method of testing is by this word line level is stepped to a mxm. from the minimum about a particular range, and is recorded in this stair-stepping word line voltage institute sensed result and searches Vt tolerance limit (read range).These a little results make comparisons with the programming data collection of knowing in advance.The result of these records can be analyzed, to find the up-and-down boundary of this tolerance limit.Page formula reads/stepping WL handles triplicate in two positions of the every unit of each page MLC product (each read range once), up to whole M LC memory array be read with the tolerance limit login till.

This method has several shortcomings.The border of each level of each page is searched to calculate this read range, and it spends the considerable time.Need a large test device internal memory to store the position information (for example being 2,000,000,000 positions) of entire chip in above-mentioned example.Come the logon data of entire chip since then evaluated calculating the border of each reading unit, and this is necessary for each read range carry out (being three times for example) in one or four position MLC device.

Fig. 2 B shows that these that determine a MLC formula internal memory read the process flow diagram of a known technology method 200 of voltage range (Vt margin search).One reference value (for example reference level 1 (" REF1 ")) is set representing one first data value (step 220), and is connected to a sensing amplifier array.Apply the word line level of the page so far and be set to minimum level (step 222) (perhaps to a maximum level or an any level) in the particular range.This page is read (step 224), and these data are output and login in this tester internal memory (step 226).If this full chip is not read (branch 228), then this page number can increase (k+1), and repeats this circulation all pages (branch 230) till this word line level is read in this internal memory.If this word line voltage is not to be positioned at this maximum permissible value (branch 232), then this word line voltage increases (j+1), and repeats this circulation (branch 228) at each word line voltage value, till reaching this maximum word line voltage (branch 234).

If this reference value is not a maximum reference value (for example REF3) (branch 236), then this reference value stepping (i+1) (for example from REF1 to REF2 or from REF2 to REF3), and at each page and each word line level repetitive cycling 228 and 232.After this word line voltage is for all three stepped variations of reference value (branch 238), analyze the logon data (step 240) of entire chip, and the minimum read range (step 242) of decision chip.Minimum read range is the narrowest read range between any two numerical value on any page of device.

Compared with prior art, embodiments of the invention use has read the minimum read range that sum code (as-read sum code) decides MLC formula internal memory product, but not full chip logs on as the processing of using Fig. 2 B.Having read sum code is expressed as each reads level and the number of the unit that is positioned at set threshold level that reads in each page.In one or two MLC, have three to read voltage range, one between L0 and L1, second between L1 and L2, and the 3rd between L2 and L3.Therefore, use three and read sum code.Other embodiment has more or less data level, and reads corresponding the increasing or minimizing of number of voltage range.For the purpose of the convenience of discussing, two MLC will be used in the example, and will illustrate that three have been read sum code SUM1, SUM2, SUM3.

Fig. 3 is presented in the MLC formula memory array sum code with respect to the parallel generation of program level.SUM3 is the number of unit that is sensed at program level three L3.For example, if a page is two kilobyte, and there are two positions every unit, then about SUM3[0:14], we will have 15 bit widths, be 16K (its all MLC that mean in this page have been programmed to L3) because be programmed to the highest number unit of level L3 at this moment.The minimum number of bits of level three was 0 (they mean that all pages do not have the MLC of any L3 of being programmed to).

SUM2 is the number of unit that is sensed at program level L2 and L3.The two kilobyte pages may not be programmed to the MLC (that is each position on the page is positioned at L1 or L0) of the page of L2 or L3, and under this situation, this number is 0, or all MLC are L2 or L3, and under this situation, this number is 16K.Therefore, SUM2 also has 15 bit widths.If SUM 2 is not to be 0, the number that then is positioned at the MLC of L2 can be determined by SUM2 is deducted SUM3.

SUM1 is the number of unit that is sensed at program level L1, L2 and L3.Moreover SUM1 has 15 bit widths, and the number that is programmed to the unit of L1, L2 and L3 may use SUM1, SUM2, SUM3 to decide.If about the figure place of SUM1 is zero, then is positioned at all MLC on this page and is assumed to be and is positioned at L0.Can only use 45 (three level each 15) to represent the whole two kilobyte pages.

The expectation value of SUM1, SUM2, SUM3 is learnt from the data of the page that will be programmed to the MLC array.These expectation sum code were being calculated data load according to distributing to the data value of each MLC to memory array, and these expectation sum code are made comparisons with the sum code that has been read after the MLC page has been programmed.If expectation sum code coupling has been read sum code, then one of this page correctly read and produce.Change speech, be applied to one of word line (it is interior the read margining scope) by use and read voltage and read the page.

Process is read in the test of this internal logic control MLC memory device, in order to carrying out the circulation of reading that repeats, is full of up to a load buffer device till the information (with reference to figure 5A about reading an example of structure) of a page.One expectation sum code of the sum code of the page that is determined by these reading of data values (MLC level) and that page is made comparisons.For example, (SUM1)=(15 ' h 0BFF, 15 ' h 33FF, 15 ' h 3C00), then L3 has 3071 (3K-1) position for SUM3, SUM2 if programmed page has; L2 has 10240 (10K) position; L1 has 2049 (2K+1) position; And L0 has 1024 (1K) position.So, SUM3=(3K-1); SUM2=(13K-1); SUM1 (15K).Yet after one read action, we can obtain new sum code (SUM3, SUM2, SUM1) (15 ' h 0BFD, 15 ' h 33FF, 15 ' h 3C00).New sum code is shown in L3 two positions, and it reads under the bias state (word line voltage) at this and is read as L2.The 3rd layer of reference level (REF3) is wrong, and it means if we go for correct data, just should transfer REF3 lower.

Yet, after one reads action, if for identical data set, we obtain to have read sum code (SUM3, SUM2, SUM1)=(15 ' h 0BFF, 15 ' h 33FF, 15 ' h 3C02), then we will know at this and read under the bias state (word line voltage), have a position in L2, and it is read as L1, and having two positions in L0, it is read as L1.In this example, REF2 and REF1 should be adjusted, so that read the correct data value of full page.

Program level L1 has the upper limit EV1 that a level PV1 (" the Vt limit down ") and a L1 are confirmed in a programming, and programming confirms that level PV1 is usually located at the lower end that the allowed Vth of the MLC of the memory array that is programmed to L1 distributes.Similarly, program level L2 has Vt limit EV2 on the lower limit PV2 and of the MLC that is programmed to L2.The 3rd program level L3 has the similar limit, and for simplified illustration, it is expression in detail not.

Similar techniques can be applied to the internal memory battle array of one of SLC formula, every unit.

Below explanation is according to the method for operating of MLC formula memory array in order to the test read margining of one embodiment of the invention.First and second expectation sum code calculates from array data (that is, will be programmed or be programmed to the data of a MLC test block, for example one of the MLC memory device page of selecting).The first expectation sum code represents to be programmed to the number of the MLC of at least one first program level (that is, be programmed to the sum of the unit of one first program level and one second program level).The second expectation sum code represents to be programmed to the number of one second program level.

MLC in memory array (for example page) reads in various word line voltages, and calculates first and second and read sum code.In one embodiment, initial word line voltage is minimum permission word line voltage, and read MLC after, word line voltage can increase.Perhaps, word line voltage is opened height and is dropped, or is changed into acquisition expectation comparison information in addition.First has read sum code represents the number of the MLCS that reads with first program level or second program level (that is, the sum of the unit that reads with L1 and L2).Second has read the number that sum code is represented the MLC that reads with second program level.

Each word line voltage read sum code and corresponding expectation sum code is made comparisons.In certain embodiments, so be assessed especially in order to the word line voltage of the gamut of sensing program level.Perhaps, the part of ranges of word lines is assessed.Ordinary representation allows to be read sum code and is stored with the sum code comparison information of the word line voltage that conforms to of expectation sum code.Read range between first program level and second program level (Vt tolerance limit) is to determine according to the sum code comparison information.

Fig. 4 shows the process flow diagram according to the method for operating 411 of the MLC formula memory array of one embodiment of the invention, and whether by read margining test, this method of operating is preferably carried out by BIST logic on the chip in order to the expression chip.A kind of data of summation method of checking in order to read based on the page from then on, come 45 sum code of 45 sum code of comparison (being two of every unit) and expectation in the 2K byte page, and this check summation method be used with determine one of a page read action whether by or failure.Be 45 (each SUM1, SUM2, SUM3 are 15), but not be to use the information that the 2K byte is arranged in each page of known method by/failure information.This can improve the test duration, and minimizing need be in order to carrying out the memory source of Vt tolerance limit test, and promotes to have the built-in self-test (" BIST ") of the IC of MLC formula memory array.

According to being shown in the method for Fig. 4, calculate the expectation sum code from the page data value of the MLC array that will be programmed to a page, or this sum code provides otherwise.The expectation sum code is read and stores for test logic access (step 412).The word line level be configured to an initial value (for example especially for one read the action usefulness minimum word line voltage) (step 414).The page is read to produce reading of data (step 416).Utilize this reading of data, can determine to have read sum code and will read sum code and make comparisons, think that each word line level provides a comparative result (step 418) with the numerical value that is loaded in the step 412.Comparative result about the word line level is stored (step 420).Referring to Fig. 5 C, as can be seen comparative result can be stored into simple one by/failure numerical value, it is each the word line level about each threshold level of this element.If entire chip not with this word line level assessment (branch 422), then increases this page numerical value (j+1) and circulation continues till full chip is evaluated (branch 424).

The word line level is assessed, and if be not positioned at the word line level (branch 426) that allows about this maximum that reads action, then these pages are assessed with next word line level (i+1), to increase the data set of similar Fig. 5 C.Perhaps, this word line numerical value starts from its maximum numerical value that allows and reduces at every turn when cycling through, or this word line numerical value starts from an any number and when circulation is passed through, changes to another numerical value, till all interesting word line numerical value are evaluated at every turn.Similarly, before proceeding to the next page, can assess a page with interesting whole word line numerical value.Other embodiment has the step of alternate orders.

After assessing full chip (branch 428) with all interesting word line numerical value, calculate minimum read range (step 430), do further explanation below with reference to 5A-5C figure.

Fig. 5 A is the example that is used to read simultaneously the sensing structure 500 of two positions in every unit.Bit-line voltage load circuit 504A provides load current to MLC unit 502 via clamp circuit 504B, and load current to three reference unit REF1, REF2, REF3 are provided in a similar manner.Load circuit 504A at the bit line of this element is controlled by a sensing enable signal SENB, and these load circuits 504A of these reference unit bit lines always sets in this example.Reference unit uses on a circuit tester, circuit programming device, the chip benchmark programmed circuit or other technology to programme, and each has different threshold voltages to make them.When a word line voltage (WL) is applied to these reference units and MLC unit 502, each will produce different reference current I _REF1, I _REF2, I _REF3, and MLC unit 502 will produce IC _ELL

Read action and represent which in these four program level (L0, L1, L2, L3) MLC unit 502 be programmed to.Reference unit is subjected to bias voltage, makes each reference unit conduct a reference current, and it is inversely proportional to the Vt of relevant program level.

Sensing amplifier 506,508,510 is IC relatively _ELLWith I _REF1, I _REF2And I _REF3To produce data value D1, D2 and D3 respectively.If greater than a reference current, then the Vth of its expression MLC unit is less than the Vth of reference unit through the electric current of MLC unit 502 thus.For example, if IC _ELLGreater than I _REF1, the D1 numerical value of sensing amplifier 506 output logics " 1 " then.Other sensing amplifier is operated in a similar manner, and from the data value of these sensing amplifiers 506,508,510 (that is, logic " 1 " or logic " 0 ") D1, D2, D3 are provided to a data computation block 512 by parallel.

The data computation block produces two bits output D _OUT, it indicates this MLC unit to be programmed to which level.For example, if the MLC unit is positioned at program level L0, then IC _ELLGreater than their I _REF1, greater than I _REF2, and greater than I _REF3, and data computation block output D _OUT=11 (" 11 ").Similarly, D _OUT=10 (" 10 ") represent that this MLC unit is programmed to L1 etc.Table 1 is presented at sensing amplifier output and D _OUTBetween representation relation:

Table 1

D1	D2	D3	D	_OUT
					1	1	1	11
0	1	1	10
				0	0	1	01
0	0	0	00

Fig. 5 B shows the sum code calculation block according to the example of an embodiment.The sum code calculation block is used standard logic formula comparer and totalizer block, therefore omits detailed operation instructions.From one group of data computation block (for example 512, also see also Fig. 5 A, 512, D _OUT) data output (D for example _OUT0), be provided to three comparers using for a plurality of unit and store body 522,524,526.In this example, use 64 sensing amplifier in parallel/data computation blocks to assess 64 unit.Can utilize the known mode of the technician who is familiar with this technology, come the sensing amplifier of other number of operation repetitive.

First comparer stores 522 many data output of body (D _OUT0, D _OUT1..., D _OUT63) and 10,01 or 00 numerical value, its expression is programmed to L1, the unit of L2 or L3 level.Comparer output is provided to a first adder 528 to produce SUM1, and it is stored in 16 working storages 530.Second comparer stores 524 many data outputs of body and 01 or 00 numerical value, and its expression is programmed to the unit of L2 or L3 level; And providing these to export a second adder 534 to produce SUM2, it is stored in one the 2 16 working storage 536.The 3rd comparer stores 526 many data outputs of body and 00 numerical value, and it represents that these unit are programmed to the L3 level; And provide these to export one the 3rd totalizer 538 to produce SUM3, it is stored in one the 3 16 working storage 540.

The the first, the second and the 3rd comparer stores body 522,524,526 operation repetitives, and cooperates totalizer 528,534,538 with parallel generation SUM1, SUM2, SUM3.The number that is programmed to the unit of L3 level is represented with SUM3.The number that is programmed to the unit of L2 level is determined (referring to Fig. 3) by SUM2 is deducted SUM3, and the number that is programmed to the unit of L1 level is determined by SUM1 is deducted SUM2.Remaining unit is positioned at L0 (wiping) level.In other words, during single the reading of 64 MLC, how many sum code SUM1, SUM2, SUM3 represent to have among 64 MLC individual is to be positioned at L1, L2, L3.The sum of learning the unit in this test block also allows to determine to be positioned at the number of the unit of L0, changes speech, and the sum of unit deducts SUM1.Use these technology, can use the single MLC array that order confirms to be programmed to varying level that reads.Do not need to repeat to read array (comparison diagram 2B, label 236) with many word line voltages for each program level.

Fig. 5 C demonstration operation instruction is made the truth table that tolerance limit is measured in this technology, and it is the MLC internal memory about the page among the IC.At first row of this chart, the word line voltage level of demonstration starts from 4.5V and ends at 6.1V and increase with 100 millivolts.Represent word line voltage from 4.5 to 6.1V scope about a particular range of this memory array.Being designated as in this chart " REF1 mistake? " first row, show the sum code comparison information of first reference level, and first reference level represents that the level about the REF1 of that word line voltage is wrong.Perhaps, the number of the unit that reads is shown in " 1 " first tabulation, and its expression level L1 does not mate the desired number of representing with SUM1, and " 0 " represents that these numbers match each other.Being designated as on this chart " REF2 mistake? " secondary series, show sum code comparison information about second reference level, level of its expression REF2 is wrong for that word line voltage.Perhaps, " 1 " secondary series is represented the number unit that reads, and its expression level L2 does not mate the number by the represented expectation of SUM2 and SUM1, and " 0 " represents that these numbers mate mutually.This chart upper mark is " REF3 mistake? " the 3rd row, show sum code comparison information about the 3rd reference level, level of its expression REF3 is wrong about that word line voltage.Perhaps, the number of the unit that reads is shown in " 1 " the 3rd tabulation, and its expression level L3 does not mate the desired number of being represented by SUM3, SUM2 and SUM1, and " 0 " represents that these numbers mate mutually.

From minimum word line voltage (this example, being 4.5V) beginning, carry out a page and read action, and relatively about the sum code of all three level expected code therewith.About this low word line voltage, all three sum code relatively will represent fault, make the people associate REF1, REF2 and REF3 should be adjusted (REF1 may be too high) or this word line voltage leaves suitable tolerance limit.When word line voltage raising (is to arrive 4.8V in this example), SUM1 will become correctly (REF1 mistake=0 (puppet)), because the sum of the number MLC of the correct summation that is programmed to L1, L2 and L3 will be read with this Vt.Yet, do not have with varying level (referring to Fig. 3, the SUM1) difference between the number of programmed cells.SUM2 and SUM3 will be wrong (REF2 mistake=1, REF3 mistake=1), and supposing has some MLC to be positioned at L2 and L3 at this page.When word line voltage continues to be increased to the allowed maximum value that reads action about a page, can obtain to be shown in the result of truth table 500.Numerical value and condition are only made the purpose of example, and the purpose as legend and discussion only is provided.

Between each level, read voltage range to each benchmark about this page, can be from the data decision of the chart of displayed map 5C.From Fig. 5 C as seen, be from 4.8V to 5.2V about the read range of word line voltage to REF1, it means between L0 and L1 400mV.Similarly, be from 5.0V to 5.4V about the read range of word line voltage to REF2, it means between L1 and L2 400mV.Read range about word line voltage is from 5.3V to 5.6V to REF3, and it means has 300mV between L2 and L3.This processing is that the MLC memory array of other page repeats (" full chip reads "), and the acquisition minimum reads voltage range.

BIST can carry out by specific minimum read range numerical value to one tester is provided.BIST logic on chip automatically performs full chip and reads action, and word line voltage crossed the stepped variation of its scope simultaneously.BIST logical OR tester stores and reads the result, calculates these sum code, and compares these sum code (referring to Fig. 6) and the minimum read range that can allow (specific).The BIST logic is selectively transmitted passing through/failure information of this IC chip.Perhaps, can provide tester so far with the passing through of individual pages/failure information, it can be set the MLC memory array for the failure page of " being locked in the outside " and can't be used by the consumer.Though this can reduce consumer's available total internal memory on IC, its permission can't be by the use of the one or more page IC of having of minimum read range specification.

Fig. 6 shows the exemplary plot in order to a test macro 600 of testing an IC 602, and IC 602 have built-in selftest BIST logic 604A, 604B, 604C (for the simplified illustration testing process just, only be shown as a plurality of mac function).For example, the BIST logic can be embedded in silicon or other IC semiconductor material by interior, or temporarily is loaded on the FPGA (Field Programmable Gate Array) portion of IC.BIST logic 604A control MLC memory array 606 and word line voltage during the page reads action, it is provided or is provided on chip by a tester 608.The MLC array 606 of several pages is assessed automatically with these admissible word line voltages, as mentioned above.

BIST logic 604B stores these and reads the result, calculates three sum code, and relatively reads these sum code of action acquisition and the minimum read range of specific (can allow) from these.Selectable BIST logic 604C provides by/miss data to tester 608.Perhaps, these sum code numerical value are provided tester so far, and it is these sum code numerical value and expectation sum code numerical value relatively, and calculate the minimum of using about these a little pages or this IC and read voltage range.In a specific embodiment, if any page in MLC array 606 can't be finished any minimum read range specification, then BIST logic 604C provides a failure numerical value.

Compared to the known technology of being discussed based on Fig. 2 A and Fig. 2 B, embodiments of the invention have several advantages.The first, do not need to seek these word line voltage borders of each level, at this moment because this read range directly from these sum code decisions.The second, do not need to store position information about whole chip (whole memory array), expect sum code and have only to store, with read sum code and make comparisons.The 3rd, logon data is a summation bit comparison information, but not whole chip position information.The 4th, do not need to repeat this and read action three times facing to three different reference values, at this moment be performed to produce sum code because supply with reading in parallel that all three reference levels use.Embodiments of the invention provide the reliable test of reaching the Vt tolerance limit with less testing time, and some embodiment comprises BIST.

The embodiment that is illustrated in this is applied to a plurality of bit locations based on the MLC technology.Also can this technology be applied to single bit location based on the SLC technology.

In sum, though the present invention with preferred embodiment exposure as above, yet it is not in order to limit the present invention.Those skilled in the art can be used for a variety of modifications and variations without departing from the spirit and scope of the present invention.Therefore, protection scope of the present invention is when with appended being as the criterion that claim was limited.

Claims

1. An integrated circuit comprising:

a memory array located on the integrated circuit; and

Logic circuits on the integrated circuit, which include:

a first sub-circuit for programming a data set into a block of memory cells in the memory array, wherein the block of memory cells includes a plurality of memory cells;

A second sub-circuit is used for repeatedly reading the memory cell block located at these word line voltages within the range of a plurality of word line voltages,

A third sub-circuit for calculating the read sum code information for each word line voltage within the range, the read sum code information indicating the number of a read memory cell at the first programming level and the number of memory cells at the second programming level A number of read memory cells of the level;

a fourth subcircuit for performing at least one of storing the read sum code information on the integrated circuit and providing the read sum code information to an output on the integrated circuit; and

A fifth sub-circuit is used for analyzing the read sum code information and providing a pass/fail result.

2. The integrated circuit of claim 1 , wherein the logic circuit stores desired sum code information representing a first number of memory cells at which the data set is programmed to a first programming level, and the data set is programmed to a first programming level. A second number of memory cells is programmed to a second programming level, and the logic circuit includes a logic circuit for comparing the read sum code information with expected sum code information.

3. The integrated circuit of claim 1, wherein the memory cell block is composed of a page of multi-level cells (MLC).

4. The integrated circuit of claim 1, wherein:

The memory block includes multi-level cells having four programming levels; and

The read sum code information includes: a first read sum code, which represents the number of first memory cells in the block where the first programming level is sensed; a second read sum code, which represents The sum of the first number of memory cells for the known data set and the second number of memory cells in the block where the second programming level is sensed; and a third read sum code representing A sum of the first number of memory cells, the second number of memory cells and a third number of memory cells in the block sensed at a third programming level.

5. The integrated circuit as claimed in claim 4, wherein the block comprises 2 ^N-1 bits, and the first read sum code, the second read sum code and the third read sum code comprise respective N bit codes.

6. The integrated circuit of claim 1 , comprising a bank of sense amplifiers configured to compare in parallel a selected cell from the block during application of a word line voltage within said range. A current and a plurality of references are used to indicate the programming level of the selected cell.

7. The integrated circuit of claim 1 , comprising an array of sense amplifiers configured to compare a current from a selected cell in the block with a first reference value, a second reference value value and a third reference value to generate a two-bit data output representing a programming state of the selected cell.

8. A method for operating a memory array, comprising the following steps:

programming a known data set into a memory block;

providing desired sum code information indicating a first number of memory cells programmed to a first programming level for the known set of data and a second number of memory cells programmed to a second programming level for the known set of data number of memory cells;

Executing a test process, which includes: repeatedly reading the memory block located at these word line voltages within a range of multiple word line voltages; calculating the read sum code information for each word line voltage within the range, which indicates the read number of memory cells at the first programming level and the read number of memory cells at the second programming level; and comparing the desired sum code information with the read sum code information for each word line within the range voltage provides sum code comparison information; and

The sum code comparison information is analyzed to determine a read tolerance of the memory block.

9. The operating method as claimed in claim 8, wherein the memory array comprises a plurality of blocks, and the method further comprises performing the programming, providing, executing and analyzing steps on the plurality of blocks to determine the plurality of blocks Whether any of the blocks have a read margin that does not meet the specification.

10. The operation method as claimed in claim 8, further comprising the step of registering the read sum code information.

11. The operating method as claimed in claim 8, wherein the memory block is composed of a page of multi-level cells (MLCs) in a memory device.

12. The operating method as claimed in claim 11, further comprising the step of reading the page by using the read margin.

13. The operating method of claim 8, wherein the memory block is part of a page of an MLC memory device.

14. The operating method of claim 8, wherein:

The memory block contains multi-level cells with four programming levels;

The expected sum code information includes: a first expected sum code, which represents a first memory cell number of the known data set programmed to a first programming level; a second expected sum code, which represents the first the sum of the number of memory cells and a second number of memory cells for which the known data set is programmed to a second programming level; and a third expected sum code representing the first number of memory cells, the number of second memory cells the sum of a third number of memory cells programmed to a third programming level with the known data set; and

The read sum code information includes: a first read sum code, which represents a first memory cell number sensed with the first programming level in the block; a second read sum code, which represents the the sum of the first memory cell number and a second memory cell number sensed in the block by the known data set at the second programming level; and a third read sum code representing the first memory cell number, the second memory cell number, and a third memory cell number sensed at the third programming level in the block.

15. The operation method as claimed in claim 14, wherein the block comprises 2 ^N-1 bits, and the first read sum code, the second read sum code and the third read sum code comprise respective N bit codes.

16. The method of operation of claim 8, wherein for each word line voltage within the range, the step of repeatedly reading includes coupling a cell to a sense amplifier that simultaneously compares a current with multiple references to represent the programmed level of the cell.

17. The method of operation of claim 8, wherein for each word line voltage within the range, the step of repeatedly reading includes coupling a cell to a sense amplifier that simultaneously compares a memory cell to a The cell current is combined with a first reference value, a second reference value and a third reference value to generate a two bit data output representing a programming state of the memory cell.

18. A method for determining a read range tolerance in a memory array of an integrated circuit, the method comprising the steps of:

a) providing a plurality of desired sum codes from the data of the memory array to be loaded into several pages, each desired sum code corresponding to a respective memory cell located in at least more than one of the memory cells programmed to correspond to the plurality of desired sum codes Each page of a programming level;

b) programming the memory array of pages each containing a first number of memory cells programmed to a first programming level on the page and a second memory cell number programmed to a second programming level on the page number of units;

c) setting a word line voltage to a first selected word line voltage;

d) reading the memory array of the page located at the word line voltage to provide read data;

e) calculating a read sum code for the page from the read data;

f) comparing the read sum code with a corresponding expected sum code to generate a comparison result, the expected sum code indicating the pages programmed to at least one of the first programming level and the second programming level the number of memory cells;

g) storing the comparison result,

h) Repeat steps (d) to (h) for the next page until the memory array of all pages has been read;

i) setting the word line voltage to the next selected word line voltage, and repeating steps (d) to (h);

j) repeating step (i) until all selected word line voltages within a selection range have been applied to the pages and the pages have been read; and

k) Calculate a read range tolerance for the IC from the comparison results.

19. The determination method according to claim 18, wherein:

The step (e) of calculating the read sum code for the page comprises: calculating a first read sum code corresponding to a first number of multi-level cells MLC programmed to at least the first programming level, and calculating a second read sum code corresponding to a second number of MLCs programmed to at least the second programming level;

The step (f) of comparing the read summation code with the corresponding expected summation code includes: comparing the first read summation code with a first expected summation code to generate a first comparison result, and comparing the second read summation code the sum code and a second expected sum code to generate a second comparison result; and

The step (g) of storing the comparison result includes: storing the first comparison result and the second comparison result.

20. The determination method of claim 19, wherein the step (k) of calculating the read range tolerance from the comparison results comprises: calculating a first read range tolerance and a second read range tolerance for the IC range tolerance.

21. The determining method of claim 18, wherein the selected range of word line voltages spans a specific maximum read range.

22. The determining method of claim 18, wherein the word line voltages of the selection range extend from a minimum allowable read voltage to a maximum read voltage.

23. The determining method of claim 22, wherein step (k) of calculating the read range tolerance occurs after step (j).

24. The determining method of claim 18, wherein step (f) of comparing the read sum code with the corresponding expected sum code to generate the comparison result occurs on the IC.

25. A method for operating a memory array, comprising the following steps:

applying a programming process to program a known data set into a memory block cell array comprising a plurality of memory block cells;

providing desired sum code information indicating the number of a first memory cell with the known data set programmed to a first programming level and a second memory cell with the known data set programmed to a second programming level number; and

reading the memory block at a word line voltage, calculating read sum code information for each word line voltage within a range, the read sum code information indicating a read number of memory cells at the first programming level and a read number of memory cells at the second programming level, and comparing the desired sum code information with the read sum code information, and

If the read sum code does not match the expected sum code information, an additional programming process is applied to the block of memory cells.