CN101159250A - Display element and method for manufacturing the same - Google Patents

Abstract

A display element and its preparation method, said method comprises providing the base plate, the base plate has area of thin film transistor, area of pixel, area of grid line and area of data line; sequentially forming a transparent conductive layer and a first metal layer on the substrate, and patterning the transparent conductive layer and the first metal layer to form conductive laminated layers respectively in the thin film transistor region, the pixel region, the grid line region and the tail end of the data line region; sequentially forming a first insulating layer and a semiconductor layer on the substrate and covering the conductive lamination, patterning the conductive lamination, and forming a patterned first insulating layer and a patterned semiconductor layer on the conductive lamination in the thin film transistor area; forming a second metal layer on the substrate, covering the patterned semiconductor layer and the conductive stack, and forming a first photoresist layer on the second metal layer; and patterning the second metal layer and the first metal layer by using the first photoresist layer as a mask, wherein a channel is formed in the thin film transistor region. Then, the first photoresist layer is subjected to thermal reflow so that part of the first photoresist layer protects the channel.

Description

Display element and manufacturing method thereof

technical field

The invention relates to a display element and a manufacturing method thereof, and in particular to a display element capable of reducing the number of masks used and a manufacturing method thereof.

Background technique

The traditional thin film transistor display element (TFT Display) uses five or four mask processes in the process, including forming the gate (first metal layer), semiconductor layer, source and drain (second metal layer), Protective layer and transparent electrode (such as ITO), etc. However, in order to simplify the process steps and save the manufacturing cost, the industry still hopes to achieve the same performance of the thin film transistor with fewer masks.

As the panel size of the display element becomes larger and larger, the signal delay caused by the impedance of the electrode wires will become more and more serious, especially the grid signal wires. Therefore, how to reduce the resistance value of the wires has also become one of the issues that related companies need to pay attention to when manufacturing large-size panels.

Contents of the invention

The invention relates to a display element and a manufacturing method thereof. In addition to reducing the number of masks used, the resistance value of wires can also be reduced, which has the advantages of reducing manufacturing costs and increasing the signal transmission speed of the display element.

The technical form of the present invention relates to a method for manufacturing a display element, which includes: providing a substrate having a thin film transistor region, a pixel region, a gate line region and a data line ( data line) area; sequentially forming a transparent conductive layer and a first metal layer on the substrate; patterning the transparent conductive layer and the first metal layer to be respectively in the thin film transistor area, the pixel area, the gate line area and the data line A conductive stack layer is formed in the end of the region, wherein the conductive stack layer includes a transparent conductive layer and a first metal layer; a first insulating layer and a semiconductor layer are sequentially formed on the substrate and cover the conductive stack layer ; Patterning the first insulating layer and the semiconductor layer to form a patterned first insulating layer and a patterned semiconductor layer on the conductive stack of the thin film transistor region; forming a second metal layer on the substrate and covering the patterned semiconductor layer and conductive stack; forming a first photoresist layer on the second metal layer; using the first photoresist layer as a mask to pattern the second metal layer and the first metal layer, wherein A channel is formed in the thin film transistor region; and the first photoresist layer is heated to cause thermal reflow, and part of the first photoresist layer protects the channel.

Another technical form of the present invention relates to a display element, which includes: a substrate having a thin film transistor area, a pixel area, a capacitor area, a gate line area and a data line area; The laminated layer is arranged in the thin film transistor region, the capacitor region and the gate line region of the substrate, wherein the conductive laminated layer includes a transparent conductive layer and a first metal layer, wherein the transparent conductive layer is arranged in the pixel region; a patterned first layer An insulating layer is arranged on the conductive layer of the thin film transistor region and the capacitor region of the substrate; a patterned semiconductor layer is arranged on the patterned first insulating layer of the thin film transistor region of the substrate; a patterned second metal layer, It includes source and drain patterns, a second metal capacitor pattern, a gate line pattern and a data line, wherein the source and drain patterns are arranged on the patterned semiconductor layer of the thin film transistor region, and the second metal capacitor pattern is arranged On the patterned first insulating layer in the capacitor area, the gate line pattern is arranged on the conductive stack in the gate line area, and the conductive stack and the gate line pattern form a gate line, and the data line is located in the data line area and electrically connected to the source pattern, and the patterned second metal layer exposes the transparent conductive layer in the pixel region as a pixel electrode; and a photoresist layer covering the patterned second metal layer, photosensitive The resist layer is an organic material.

In order to make the above content of the present invention more comprehensible, preferred embodiments are specifically cited below, together with the accompanying drawings, and described in detail as follows.

Description of drawings

1A to 1F illustrate a method for manufacturing a display element according to a first embodiment of the present invention.

2A to 2C are top views of FIG. 1A , FIG. 1B and FIG. 1F respectively.

FIG. 3 is a diagram illustrating one of the steps of the manufacturing method of the display device according to the second embodiment of the present invention.

FIG. 4 is a top view of FIG. 3 .

5A to 5E illustrate a manufacturing method to form the structure of the thin film transistor region and the capacitor region in FIG. 3 of the second embodiment.

6A to 6G illustrate a method for manufacturing a display element according to a third embodiment of the present invention.

7A to 7C are top views of FIG. 6A , FIG. 6B and FIG. 6G , respectively.

8A to 8E illustrate a manufacturing method to form the structure of the thin film transistor region and the capacitor region in FIG. 6B of the third embodiment.

Wherein, the reference signs are explained as follows:

9: Substrate 10: Conductive laminate

101: transparent conductive layer 103: first metal layer

11: Gate line area 113: Second metal layer

115: The first photoresist layer 115': The first photoresist layer after thermal reflow

117: Gate pad (pad) 118: Data pad

119: Three-layer conductor stack structure 13: Thin film transistor area

15: Pixel area 17: Capacitor area

19: Data line area 201, 301: Patterning the first insulating layer

203, 303: patterned semiconductor layer 305: patterned second insulating layer

205, 307: patterned ohmic contact layer 207: channel

309: separation area 501, 701: first insulation layer

503, 703: semiconductor layer 505: ohmic contact layer

705: second insulating layer

513, 514, 711, 721, 731: photoresist blocks

513', 711': remaining blocks of photoresist

Detailed ways

The invention provides a display element and a manufacturing method thereof. The manufacturing method of the present invention can be used to manufacture display elements with thin film transistors of different structures, such as back channel etching type structure (Back-Channel Etching (BCE) Type TFT) thin film transistors, or etch stop type structure (Etch Stop Type TFT). TFT) thin film transistor. Furthermore, the manufacturing method of the present invention is to reduce the number of masks used and thus reduce the manufacturing cost. In addition, the electrode wires made by applying the present invention, especially the gate signal wires, have a three-layer conductive structure, which can reduce the resistance of the wires. , to solve the problem of signal delay caused by the high impedance of the traditional large-size panel electrode wires.

The first, second and third embodiments are proposed below as descriptions of the present invention, wherein the thin film transistors in the display elements of the first and second embodiments are back channel etched (BCE) structures, and the display of the third embodiment The thin film transistor in the device is an etch-stop (Island-Stop) structure. However, the steps and display elements provided in these embodiments are for illustrative purposes only, and are not intended to limit the protection scope of the present invention. Furthermore, the drawings in the embodiments also omit unnecessary elements, so as to clearly show the technical characteristics of the present invention. In addition, the same reference numerals are used for the same elements in the first, second and third embodiments.

first embodiment

Please refer to FIG. 1A to FIG. 1F , which illustrate a manufacturing method of a display element according to a first embodiment of the present invention. Please refer to FIG. 2A to FIG. 2C at the same time, which respectively depict top views of FIG. 1A , FIG. 1B and FIG. 1F . FIG. 1A, FIG. 1B and FIG. 1F are schematic cross-sectional views drawn along the section line L-L' in FIG. 2A to FIG. 2C.

The display element has a plurality of scanning signal lines (not shown) and a plurality of data signal lines (not shown) vertically intersecting in an array, and the scanning signal lines and the data signal lines define a plurality of pixels, and each pixel is composed of It is defined by a pair of adjacent scanning signal lines and a pair of adjacent data signal lines. In this embodiment, each pixel is manufactured by having a gate line region 11, a thin film transistor region 13, a pixel region 15, a capacitor region (Cst region) 17 and a data line region (data-line region) 19. A description of the method.

[First mask process]

Please refer to FIG. 1A and FIG. 2A at the same time. Fig. 1A is a schematic cross-sectional view drawn along the section line L-L' in Fig. 2A. Firstly, a substrate 9 is provided, and a transparent conductive layer 101 is formed on the substrate 9 , and then a first metal layer 103 is formed on the transparent conductive layer 101 . Then pattern (such as photolithography and etching process) the first metal layer 103 and the transparent conductive layer 101, so as to be respectively at the ends of the thin film transistor region 13, the pixel region 15, the gate line region 11 and the data line region 19 (ie, FIG. 2A A conductive stack layer 10 is formed in the square area shown in . The material of the transparent conductive layer 101 is, for example, indium tin oxide (ITO).

In this embodiment, when the transparent conductive layer 101 and the first metal layer 103 are patterned, the capacitive conductive stack 10 is formed in the capacitive area 17 at the same time, wherein the capacitive conductive stack 10 also includes the transparent conductive layer 101 and the first metal layer 103. A metal layer 103 .

[Second Mask Process]

Please refer to FIG. 1B and FIG. 2B at the same time. Fig. 1B is a schematic cross-sectional view drawn along the section line L-L' in Fig. 2B. In the second mask process, the first insulating layer and the semiconductor layer are sequentially formed on the substrate 9 and cover the conductive layer 10; then patterning (such as photolithography and etching process) the first insulating layer and the semiconductor layer , so as to respectively form a patterned first insulating layer 201 and a patterned semiconductor layer 203 on the conductive stack 10 of the thin film transistor region 13 . The patterned first insulating layer 201 and the patterned semiconductor layer 203 are formed by the same mask process.

In this embodiment, when patterning the first insulating layer and the semiconductor layer, the patterned first insulating layer 201 and the patterned semiconductor layer 203 are also formed on the capacitive conductive layer 10 in the capacitive region 17 at the same time, as shown in FIG. 1B Show.

In this embodiment, an ohmic contact layer can be optionally formed on the semiconductor layer, and in the step of patterning the first insulating layer and the semiconductor layer, the same mask process is used to form the thin film transistor region 13 and the capacitor region 17 Patterned ohmic contact layers 205 are formed respectively.

In this embodiment, the materials of the patterned first insulating layer 201, the patterned semiconductor layer 203 and the patterned ohmic contact layer 205 are, for example, silicon nitride (SiN) layer, amorphous silicon layer (amorphous silicon layer, a- Si Layer) and n+ amorphous silicon layer (n+a-Si).

[Third mask process]

Next, form the second metal layer 113 on the substrate 9, and cover the patterned semiconductor layer 203 in the thin film transistor region 13 and the capacitor region 17 (in this embodiment, cover the patterned ohmic contact layer 205), and cover the gate The conductive stack 10 in the line area 11 , the pixel area 15 and the data line area 19 . After that, a patterned first photoresist layer 115 is formed on the second metal layer 113 , as shown in FIG. 1C . The first photoresist layer 115 can be an organic material, which has characteristics of etching resistance and thermal reflow at high temperature.

As shown in FIG. 1D, after the second metal layer 113 and the first metal layer 103 are patterned using the patterned first photoresist layer 115 as a mask, a part of the patterned layer is exposed in (a) the thin film transistor region 13. The surface of the ohmic contact layer 205, (b) exposes part of the transparent conductive layer 101 in the pixel region 15 as a pixel electrode, (c) exposes part of the transparent conductive layer 101 at the ends of the gate line region 11 and the data line region 19 respectively. Layer 101, to serve as gate pad 117 and data pad 118, (d) in capacitor region 17, form second metal capacitor pattern 113 on patterned semiconductor layer 203 (the second metal capacitor pattern in this embodiment 113 is located on the patterned ohmic contact layer 205).

Next, as shown in FIG. 1E , part of the patterned ohmic contact layer 205 is removed in the TFT region 13 to expose part of the surface of the patterned semiconductor layer 203 to form a channel 207 .

Finally, the first photoresist layer 115 is heated to reflow (reflow), and part of the first photoresist layer 115 flows into the channel 207 of the TFT region 13 to cover it, as shown in FIG. 1F Show. The photoresist layer 115' after thermal reflow not only covers the channel 207 and the second metal layer 113 in the thin film transistor region 13, but also partly flows into the transparent conductive layer 101 in the pixel region 15 and the gate line region 11. part of the surface, and the second metal capacitor pattern 113 covering the capacitor region 17 . Therefore, the photoresist layer 115' after thermal reflow can completely cover the second metal layer 113 to achieve protection.

Please also refer to FIG. 2C , which is a top view of FIG. 1F . As shown in FIG. 2C , the gate line in the gate line region 11 has a second metal layer 113 , and its end has a gate pad 117 (formed by the transparent conductive layer 101 ). The location of the channel 207 and the second metal layer 113 can be seen in the TFT region 13 . The second metal capacitor pattern 113 is also shown at the capacitor region 17 . There is a data pad 118 (formed by the transparent conductive layer 101 ) at the end of the data line region 19 .

According to the first embodiment, in the gate line area 11, except that the transparent conductive layer 101 is used as the gate pad 117, the gate line (gate line) is a three-layer conductor stack structure 119 (as shown in FIG. 1E ), It includes a transparent conductive layer 101 , a first metal layer 103 and a second metal layer 113 .

To sum up, the photoresist 115' formed by thermal reflow can be used as a protective layer in the display element, thereby eliminating the subsequent step of forming a protective layer and achieving the purpose of reducing the number of masks used. Furthermore, the gate line in the gate line region 11 has a three-layer conductor stack structure 119, which can reduce the impedance of the wire and solve the problem of signal delay caused by the high impedance of the traditional large-size panel electrode wire.

second embodiment

The capacitance structure of the second embodiment is different from that of the first embodiment. In the manufacturing method of the display element of the second embodiment, the detailed implementation of some processes is similar to that disclosed in the previous embodiments, so please refer to FIGS.

Please refer to Figure 3. In the second embodiment, after forming the conductive stack 10 respectively at the ends of the thin film transistor region 13, the pixel region 15, the capacitor region 17, the gate line region 11 and the data line region 19, as shown in FIG. 1A, then Form a patterned first insulating layer 201, a patterned semiconductor layer 203 (and a patterned ohmic contact layer 205) in the thin film transistor region 13, and simultaneously form a patterned first insulating layer on the capacitor conductive stack 10 in the capacitor region 17 201. Please also refer to FIG. 4 , which is a top view of FIG. 3 .

In this embodiment, the materials of the patterned first insulating layer 201, the patterned semiconductor layer 203 and the patterned ohmic contact layer 205 are, for example, silicon nitride (SiN) layer, amorphous silicon layer (a-Si) and n+ amorphous silicon layer (n+a-Si).

In the second embodiment, the patterning of the first insulating layer 201 and the semiconductor layer 203 can be accomplished by a half-tone mask process, a gray-tone mask process, or two mask processes with different exposure energies. The present invention is not limited to this.

Similar to the first embodiment, in the structure manufactured according to the second embodiment, the photoresist formed by thermal reflow can be used as a protective layer in the display element, so as to reduce the number of masks used. The gate lines made of three layers of conductors can reduce the impedance of the wires and solve the problem of signal delay caused by the high impedance of the traditional large-size panel electrode wires. The difference from the first embodiment is that the capacitor structure made according to the second embodiment only has a patterned first insulating layer 201 (for example, silicon nitride) and does not have amorphous silicon, so the capacitance value remains the same when the voltage is changed. Very stable.

In addition, in the second embodiment, the manufacturing method shown in FIG. 5A to FIG. 5E can be used to form the structure of the thin film transistor region and the capacitor region in FIG. 3 . As shown in FIG. 5A , a first insulating layer 501 , a semiconductor layer 503 , and an ohmic contact layer 505 are sequentially formed on the substrate 9 and cover these conductive layers (composed of the transparent conductive layer 101 and the first metal layer 103 ). Then, as shown in Figure 5B, a photoresist layer is formed on the ohmic contact layer 505 of the thin film transistor region 13 and the capacitor region 17 respectively (if the ohmic contact layer 505 is omitted during manufacture, the photoresist is then formed on the semiconductor layer 503), wherein the photoresist layer includes a photoresist block 513 located in the thin film transistor region 13 and a photoresist block 514 located in the capacitor region 17, wherein the photoresist block The thickness of 513 is greater than the thickness of photoresist block 514 . Afterwards, using the photoresist layer as a mask, a first etching process is performed on the ohmic contact layer 505 , the semiconductor layer 503 and the first insulating layer 501 to form a patterned first insulating layer 301 , as shown in FIG. 5C . At this time, the patterned first insulating layer 201 in the thin film transistor region 13 and the capacitor region 17 is the same as that shown in FIG. 3 . Next, reduce the thickness of the photoresist layer, such as by using an ashing process, until the photoresist block 514 of the capacitor region 17 is completely removed, as shown in FIG. 5D . Afterwards, using the remaining photoresist block 513' in the thin film transistor region 13 as a mask, a second etching process is performed on the semiconductor layer 503 in the capacitor region 17 to form a patterned semiconductor layer 201, as shown in FIG. 5E , the ohmic contact layer 505 and the semiconductor layer 503 of the capacitor region 17 are completely removed. Finally, the remaining photoresist block 513' is removed to produce the structure of the thin film transistor region and the capacitor region as shown in FIG. 3 . However, those skilled in the art should know that the manufacturing method shown in FIG. 5A to FIG. 5E is only one technical means of a certain process in the second embodiment, and the present invention is not limited thereto. Other methods for fabricating the structure of the thin film transistor region and the capacitor region as shown in FIG. 3 can also be applied to the second embodiment.

third embodiment

The first and second embodiments use a back channel etching (BCE, Back Channel Etching) structure as the thin film transistor of the display element, while in the third embodiment, an island-stop structure is used as the thin film of the display element Transistor structure for illustration of the present invention.

Please refer to FIG. 6A to FIG. 6G , which illustrate a manufacturing method of a display element according to a third embodiment of the present invention. Please refer to FIG. 7A to FIG. 7C at the same time, which respectively illustrate the top views of FIG. 6A , FIG. 6B and FIG. 6G . Fig. 6A, Fig. 6B and Fig. 6G are schematic cross-sectional views drawn along the section line L-L' in Fig. 7A to Fig. 7C.

The display element has a plurality of scanning signal lines (not shown) and a plurality of data signal lines (not shown) vertically intersecting in an array, and the scanning signal lines and the data signal lines define a plurality of pixels, and each pixel is composed of It is defined by a pair of adjacent scanning signal lines and a pair of adjacent data signal lines. In this embodiment, each pixel has a gate line region 11 , a thin film transistor region 13 , a pixel region 15 , a capacitor region 17 and a data line region 19 to illustrate the manufacturing method of this embodiment.

[First mask process]

Please refer to FIG. 6A and FIG. 7A at the same time. Fig. 6A is a schematic cross-sectional view drawn along the section line L-L' in Fig. 7A. Firstly, a substrate 9 is provided, and a transparent conductive layer 101 is formed on the substrate 9 , and then a first metal layer 103 is formed on the transparent conductive layer 101 . Then patterning (such as photolithography and etching process) the first metal layer 103 and the transparent conductive layer 101, so as to be respectively at the ends of the thin film transistor region 13, the pixel region 15, the gate line region 11 and the data line region 19 (ie, FIG. 7A The conductive stack 10 is formed in the square area shown in ). The material of the transparent conductive layer 101 is, for example, indium tin oxide (ITO).

In this embodiment, when the transparent conductive layer 101 and the first metal layer 103 are patterned, the capacitive conductive stack 10 is formed in the capacitive area 17 at the same time, wherein the capacitive conductive stack 10 also includes the transparent conductive layer 101 and the first metal layer 103. A metal layer 103 .

[Second Mask Process]

Please refer to FIG. 6B and FIG. 7B at the same time. Fig. 6B is a schematic cross-sectional view drawn along the section line L-L' in Fig. 7B. In the second masking process, a first insulating layer, a semiconductor layer and a second insulating layer are sequentially formed on the substrate 9 and cover the conductive stack 10; then patterning (such as photolithography and etching process) is performed to A patterned first insulating layer 301 , a patterned semiconductor layer 303 and a patterned second insulating layer 305 are formed on the conductive stack 10 of the TFT region 13 . The method of forming the patterned first insulating layer 301, the patterned semiconductor layer 303 and the patterned second insulating layer 305 is, for example, through a half-tone mask process, a gray-tone mask process, or two masks with different exposure energies craft.

In the second process of this embodiment, a patterned first insulating layer 301 and a patterned semiconductor layer 303 are also formed on the capacitive conductive stack 10 in the capacitive region 17 at the same time, as shown in FIG. 6B .

In this embodiment, the materials of the patterned first insulating layer 301, the patterned semiconductor layer 303 and the patterned second insulating layer 305 are, for example, silicon nitride (SiN) layer, amorphous silicon layer (a-Si Layer ) and silicon nitride layer.

In this embodiment, as shown in FIG. 6C, a phosphine treatment (PH3 treatment) is preferably performed in the thin film transistor region 13 and the capacitor region 17 to form a patterned ohmic contact on the patterned semiconductor layer 303. Layer 307. The patterned ohmic contact layer 307 is, for example, an n+ amorphous silicon layer (n+a-Si).

[Third mask process]

Next, as shown in FIG. 6D, a second metal layer 113 is formed on the substrate 9, and covers the conductive stack 10 in the gate line area 11, the pixel area 15, and the data line area 19, and covers the pattern in the thin film transistor area 13. The second insulating layer 305 and the patterned ohmic contact layer 307 are covered, and the patterned ohmic contact layer 307 in the capacitive region 17 is covered. After that, a patterned first photoresist layer 115 is formed on the second metal layer 113 , as shown in FIG. 6E . The patterned first photoresist layer 115 can be an organic material, which has characteristics of etching resistance and thermal reflow at high temperature.

Then, as shown in FIG. 6F, the second metal layer 113 and the first metal layer 103 are patterned (such as photolithography and etching process) with the patterned first photoresist layer 115 as a mask, wherein in the thin film transistor region 13 to form a separation region 309 .

As shown in FIG. 6F, after the second metal layer 113 and the first metal layer 103 are patterned using the patterned first photoresist layer 115 as a mask, a part of the patterned layer is exposed in (a) the thin film transistor region 13. The surface of the second insulating layer 305, (b) exposes part of the transparent conductive layer 101 in the pixel region 15 as a pixel electrode, (c) exposes part of the transparent conductive layer 101 at the ends of the gate line region 11 and the data line region 19 respectively. The conductive layer 101 is used as a gate pad (gate pad) 117 and a data pad (data pad) 118, (d) in the capacitor region 17, forming a second metal capacitor pattern 113 above the patterned semiconductor layer 303 ( In this embodiment, the second metal capacitor pattern 113 is located on the patterned ohmic contact layer 307 ).

Finally, heating the first photoresist layer 115 makes it thermal reflow (thermal reflow), and part of the first photoresist layer 115 flows into the separation region 309 of the thin film transistor region 13 to cover it, as shown in FIG. 6G shown. The photoresist layer 115' after thermal reflow not only covers the separation region 309 and the second metal layer 113 in the thin film transistor region 13, but also partly flows into the transparent conductive layer 101 in the pixel region 15 and the gate line region 11. part of the surface, and the second metal capacitor pattern 113 covering the capacitor region 17 . Therefore, the photoresist layer 115' after thermal reflow can completely cover the second metal layer 113 to achieve protection.

Please also refer to FIG. 7C , which is a top view of FIG. 6G . As shown in FIG. 7C , the gate line in the gate line region 11 has a second metal layer 113 , and its end has a gate pad 117 (formed by the transparent conductive layer 101 ). In the thin film transistor region 13 , the location of the separation region 309 and the second metal layer 113 can be seen. The second metal capacitor pattern 113 is also shown at the capacitor region 17 . There is a data pad 118 (formed by the transparent conductive layer 101 ) at the end of the data line region 19 .

According to the above third embodiment, the photoresist 115' formed by thermal reflow can be used as a protective layer in the display element, thereby eliminating the subsequent steps of forming a protective layer and reducing the number of masks used. Furthermore, the gate line in the gate line area 11 has a three-layer conductor stack structure 119 (as shown in FIG. 6F ), including a transparent conductive layer 101, a first metal layer 103 and a second metal layer 113, which can reduce the resistance of the wire. , to solve the problem of signal delay caused by the high impedance of the traditional large-size panel electrode wires.

In addition, in the second mask process of the third embodiment, the manufacturing method shown in FIG. 8A to FIG. 8E can be used to form the structure of the thin film transistor region and the capacitor region in FIG. 6B . As shown in FIG. 8A , a first insulating layer 701 , a semiconductor layer 703 and a second insulating layer 705 are sequentially formed on the substrate 9 . Then, as shown in FIG. 8B, a patterned photoresist is formed in the thin film transistor region 13 and the capacitor region 17, wherein the patterned photoresist of the thin film transistor region 13 has a first photoresist region Block 711 and the second photoresist block 721 located on both sides of the first photoresist block 711, and the thickness of the first photoresist block 711 is greater than the second photoresist Thickness of block 721 . The capacitor area 17 has a photoresist block 731 , and the thickness of the first photoresist block 711 is also greater than the thickness of the photoresist block 731 . Afterwards, as shown in FIG. 8C , using the photoresist as a mask, a first etching process is performed on the second insulating layer 705, the semiconductor layer 703, and the first insulating layer 701, so that the thin film transistor region 13 and the capacitor region 17 A patterned first insulating layer 301 and a patterned semiconductor layer 303 are formed. Then, as shown in FIG. 8D , reduce the thickness of the photoresist, such as using an ashing (ashing) process, until the second photoresist block 721 of the thin film transistor region 13 is completely removed, at this time, the capacitor region The photoresist block 731 of 17 is also completely removed. Afterwards, as shown in FIG. 8E , the second insulating layer 705 is subjected to a second etching process using the remaining first photoresist block 711 ′ as a mask to form a patterned second insulating layer in the TFT region 13 305 , at this time, the second insulating layer 705 of the capacitor region 17 is completely removed. Finally, the remaining first photoresist block 711' is removed to produce the structure of the thin film transistor region and the capacitor region as shown in FIG. 6B. However, those skilled in the art should know that the manufacturing method shown in FIG. 8A to FIG. 8E is only one technical means of the second mask process of the third embodiment, and the present invention is not limited thereto. Other methods for fabricating the structure of the thin film transistor region and the capacitor region as shown in FIG. 6B can also be applied to the third embodiment.

Although the present invention has been disclosed above with embodiments, it is not intended to limit the present invention. Any person skilled in the art should be able to make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be based on the appended claims.

Claims (25)

1. the manufacture method of a display element comprises:

One substrate is provided, and this substrate has a thin film transistor region, a pixel region, a gate line district and a data wire district;

Form a transparency conducting layer and a first metal layer in regular turn on this substrate;

This transparency conducting layer of patterning and this first metal layer, with the terminal interior conductive laminate that forms respectively at this thin film transistor region, this pixel region, this gate line district and this data wire district, wherein this conductive laminate comprises this transparency conducting layer and this first metal layer;

Form one first insulating barrier and semi-conductor layer in regular turn on this substrate, and cover this conductive laminate;

This first insulating barrier of patterning and this semiconductor layer are to form a patterning first insulating barrier and a patterned semiconductor layer on this conductive laminate of this thin film transistor region;

Form one second metal level on this substrate, and cover this patterned semiconductor layer and this conductive laminate;

Form one first photoresist layer on this second metal level;

With this first photoresist layer is this second metal level of mask patterning and this first metal layer, wherein forms a raceway groove in this thin film transistor region; And

The first photoresist layer is carried out hot reflux, make this first photoresist layer of part protect this raceway groove.

2. manufacture method as claimed in claim 1, wherein this patterning second metal level and this raceway groove this first photoresist layer after by hot reflux covers.

3. manufacture method as claimed in claim 1, wherein this first photoresist layer is an organic material.

4. manufacture method as claimed in claim 1, wherein this step of this second metal level of patterning and this first metal layer is to expose this transparency conducting layer of part as a pixel electrode in this pixel region.

5. manufacture method as claimed in claim 1, wherein this patterning first insulating barrier and this patterned semiconductor layer are by being formed with mask process.

6. manufacture method as claimed in claim 1, this step of this second metal level of patterning and this first metal layer wherein makes the end in this gate line district and this data wire district expose this transparency conducting layer of part respectively, with as a connection pad.

7. manufacture method as claimed in claim 1 also comprises forming a patterning ohmic contact layer in this patterned semiconductor layer surface.

8. manufacture method as claimed in claim 1 also comprises:

Form a patterning second insulating barrier on this patterned semiconductor layer; And

Carrying out a hydrogen phosphide handles to form this patterning ohmic contact layer on this patterned semiconductor layer of this thin film transistor region.

9. manufacture method as claimed in claim 8 wherein forms this patterning first insulating barrier, this patterned semiconductor layer and the method for this patterning second insulating barrier and is by half mode mask process, a grey mode mask process or two mask process by different exposure energies.

10. manufacture method as claimed in claim 8 is characterized in that the method that forms this patterning first insulating barrier, this patterned semiconductor layer and this patterning second insulating barrier comprises:

After forming this first insulating barrier and this semiconductor layer, form one second insulating barrier on this semiconductor layer;

Form one second photoresist layer on this second insulating barrier of this thin film transistor region, this second photoresist layer one second photoresist block of having one first photoresist block and being positioned at these first photoresist block both sides wherein, and the thickness of this first photoresist block is greater than this second photoresist block;

With this second photoresist layer is that mask carries out one first etch process to this second insulating barrier, this semiconductor layer and this first insulating barrier, to form this patterning first insulating barrier and this patterned semiconductor layer;

Reduce the thickness of this second photoresist layer, removed fully up to this second photoresist block; And

With remaining this first photoresist block is that mask carries out one second etch process to this second insulating barrier, to form this patterning second insulating barrier.

11. comprising, manufacture method as claimed in claim 10, the method that wherein reduces this photoresist layer thickness carry out a cineration technics.

12. manufacture method as claimed in claim 1 also comprises forming an electric capacity on a capacitive region of this substrate.

13. manufacture method as claimed in claim 12 is characterized in that the step that forms this electric capacity comprises:

When this transparency conducting layer of patterning and this first metal layer, form an electric capacity conductive laminate simultaneously in this capacitive region, wherein this electric capacity conductive laminate comprises this transparency conducting layer and this first metal layer;

When this first insulating barrier of patterning and this semiconductor layer, this patterning first insulating barrier and this patterned semiconductor layer are formed on this electric capacity conductive laminate simultaneously; And

When this second metal level of patterning and this first metal layer, form one second metal capacitance pattern simultaneously on this patterned semiconductor layer of this capacitive region.

14. manufacture method as claimed in claim 13 also comprises forming a patterning ohmic contact layer in this patterned semiconductor layer surface.

15. manufacture method as claimed in claim 12, the step that wherein forms this electric capacity comprises:

When this transparency conducting layer of patterning and this first metal layer, form an electric capacity conductive laminate simultaneously in this capacitive region, wherein this conductive laminate comprises this transparency conducting layer and this first metal layer;

When this first insulating barrier of patterning and this semiconductor layer, this patterning first insulating barrier is formed on this electric capacity conductive laminate simultaneously; And

When this second metal level of patterning and this first metal layer, form one second metal capacitance pattern simultaneously on this patterning first insulating barrier of this capacitive region.

16. manufacture method as claimed in claim 15, the method that wherein forms this patterning first insulating barrier and this patterned semiconductor layer comprises:

Form one the 3rd photoresist layer on this semiconductor layer of this thin film transistor region and this capacitive region, wherein the 3rd photoresist layer comprises one the 3rd photoresist block that is positioned at this thin film transistor region and one the 4th photoresist block that is positioned at this capacitive region, and wherein the thickness of the 3rd photoresist block is greater than the 4th photoresist block;

With the 3rd photoresist layer is that mask carries out one first etch process to this semiconductor layer and this first insulating barrier, to form this patterning first insulating barrier and this patterned semiconductor layer in this thin film transistor region;

Reduce the thickness of the 3rd photoresist layer, removed fully up to the 4th photoresist block; And

Carry out one second etch process with remaining the 3rd photoresist block for the mask of this thin film transistor region and to this semiconductor layer of this capacitive region, to form this patterning first insulating barrier.

17. manufacture method as claimed in claim 16, the method that it is characterized in that reducing the 3rd photoresist layer thickness comprises carries out a cineration technics.

18. manufacture method as claimed in claim 15, wherein this first insulating barrier of patterning and this semiconductor layer are by half mode mask process, a grey mode mask process or the twice mask process by different exposure energies.

19. a display element comprises:

One substrate has a thin film transistor region, a pixel region, a capacitive region, a gate line district and a data wire district;

One conductive laminate is arranged in this thin film transistor region, this capacitive region and this gate line district of this substrate, and wherein this conductive laminate comprises a transparency conducting layer and a first metal layer;

One patterning, first insulating barrier is disposed on this conductive laminate of this thin film transistor region of this substrate and this capacitive region;

One patterned semiconductor layer is arranged on this patterning first insulating barrier of this thin film transistor region of this substrate;

One patterning, second metal level, comprise an one source pole and a drain pattern, one second metal capacitance pattern, an one grid line pattern and a data wire, wherein this source/drain pattern arrangement is on this patterned semiconductor layer of this thin film transistor region, this second metal capacitance pattern arrangement is on this patterning first insulating barrier of this capacitive region, this grid circuit pattern arrangement on this conductive laminate in this gate line district and this conductive laminate and this grid line pattern constitute a gate line, and this data line bit is in the data wire district and be electrically connected to this source electrode pattern, and this pixel region exposes this transparency conducting layer of part as a pixel electrode; And

One photoresist layer is covered on this patterning second metal level and this raceway groove.

20. display element as claimed in claim 19, wherein this patterned semiconductor layer also is arranged between this patterning first insulating barrier and this second metal capacitance pattern of this capacitive region.

21. display element as claimed in claim 19 also comprises a patterning ohmic contact layer, is disposed at this patterned semiconductor layer surface.

22. display element as claimed in claim 19, wherein this gate line district and this data wire district end have this transparency conducting layer of part respectively, with as a connection pad.

23. display element as claimed in claim 19 comprises that also a patterning second insulating barrier is arranged on this patterned semiconductor layer of this thin film transistor region.

24. display element as claimed in claim 19, wherein the material of this patterning first insulating barrier comprises silica, silicon nitride or organic material.

25. display element as claimed in claim 19, wherein this transparency conducting layer is an indium tin oxide layer or an indium-zinc oxide layer.

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