CN101156253A - Semiconductor element and its manufacturing method - Google Patents

Abstract

An object of the present invention is to provide a semiconductor element comprising an n-type gallium nitride-based compound semiconductor and a novel electrode making ohmic contact with the semiconductor. A semiconductor element of the present invention has an n-type gallium nitride-based compound semiconductor and an electrode forming an ohmic contact with the semiconductor, wherein the electrode has a TiW alloy layer to be in contact with the semiconductor. According to a preferred embodiment, the aforementioned electrodes may also be used as contact electrodes. According to a preferred embodiment, the above-mentioned electrodes have excellent thermal resistance. Furthermore, a production method of the semiconductor element is proposed.

Description

Semiconductor element and its manufacturing method

technical field

The invention relates to a semiconductor element and a manufacturing method thereof. The semiconductor element includes an n-type gallium nitride-based compound semiconductor and an electrode in ohmic contact with the semiconductor.

Background technique

Gallium nitride-based compound semiconductor (hereinafter also referred to as "GaN-based semiconductor") is a compound semiconductor composed of group III nitride represented by the following chemical formula:

Al _a In _b Ga _1-ab N (0≤a≤1, 0≤b≤1, 0≤a+b≤1),

The GaN-based semiconductor is exemplified by compounds having such compounds as GaN, InGaN, AlGaN, AlInGaN, AlN, InN, and the like. In the compound semiconductor of the above chemical formula, a part of group III elements is replaced by B (boron), Tl (thallium), etc., and a part of N (nitrogen) is replaced by P (phosphorus), As (arsenic), Sb (antimony), Bi Compounds such as bismuth (bismuth) are also included in GaN-based semiconductors.

In recent years, GaN-based semiconductor light-emitting elements such as light-emitting diodes (LEDs), laser diodes (LDs) and the like that emit light having wavelengths from green to ultraviolet light have been practiced and attracted attention. This light-emitting element has A pn junction diode structure formed by connecting a p-type GaN-based semiconductor and a p-type GaN-based semiconductor is used as the basic mechanism. Briefly, according to the light-emitting mechanism of the light-emitting element, when the electrons injected into the n-type GaN-based semiconductor and the positive holes injected into the p-type GaN-based semiconductor recombine to lose energy at the pn junction and its vicinity, the emitted light and The energy corresponds to light. In this element, an electrode that makes ohmic contact with the n-type GaN-based semiconductor (hereinafter also referred to as "n-type ohmic electrode") is used to efficiently implant the electrode into the n-type GaN-based semiconductor. In LEDs, a structure in which an n-type ohmic electrode is also used as a contact electrode is generally employed. A contact electrode is an electrode to which a bonding wire, solder, or the like for electrically connecting an element to an external electrode of the element is joined. The contact electrodes are required to exhibit good bondability with bonding wires (such as Au wires) or solders (such as Au—Sn eutectic). When the bondability is weak, defects may occur in a chip mounting process.

Conventionally, an Al (aluminum) single-layer film or a multilayer film in which an aluminum layer is laminated on a Ti (titanium) layer has been used as an n-type ohmic electrode (JP-A-7-45867, USP 5,563,422). However, since these electrodes are mainly composed of aluminum layers, they exhibit low thermal resistance and may be easily deformed when heat treatment is applied, for example. This is caused by the fact that aluminum has a low melting point, and since the coefficient of thermal expansion of aluminum is considerably large compared with GaN-based semiconductors and the like, thermal stress tends to develop inside the electrodes. Furthermore, when these electrodes are used as contact electrodes, an oxide film is formed on the surface of aluminum, which degrades the bondability and wettability of Au wires by Au—Sn eutectic solder. Therefore, yield tends to be low during chip mounting. In order to solve this problem, an electrode has been proposed (JP-A-7-221103, USP 5,563,422) in which an Au layer is laminated on an Al layer at a layer composed of a metal having a relatively high melting point. However, the electrode also requires heat treatment at a temperature of about 400° C. to reduce contact resistance because the electrode is in contact with the n-type GaN-based semiconductor at the Al layer. Heat treatment roughens the electrode surface and may degrade bondability with bonding wire or solder. This electrode is associated with the problem of difficulty in producing the same properties with good reproducibility because the diffusion state of Al and Au due to thermal stress affects the contact resistance with n-type GaN-based semiconductor after heat treatment.

As an n-type ohmic electrode not containing Al, JP-A-11-8410 discloses providing an n-type electrode obtained by laminating a TiW alloy layer, a Ge (germanium) layer, and a Rh (rhodium) layer and by heat-treating the lamination. Ohmic electrode. The mechanism by which a good ohmic contact is formed with an electrode of an n-type GaN-based semiconductor is unclear. However, since good ohmic contact is formed regardless of the lamination order of these three metal layers, it is assumed that the product resulting from the chemical reaction involving all three metal layers plays some role. It is thus expected that the properties of the obtained electrode cannot be stabilized unless under the regulation of laminating the three layers and strictly controlling the conditions controlling the subsequent heat treatment upon electrode formation. Therefore, it is considered that semiconductor elements using this electrode are not suitable for mass production.

Contents of the invention

The present invention has been achieved in consideration of such circumstances, and aims to provide a semiconductor element including a novel ohmic electrode that forms a good ohmic contact with an n-type GaN-based semiconductor. The present invention also aims to provide a semiconductor element comprising an n-type ohmic electrode, preferably, the n-type ohmic electrode can be used as a contact electrode. Furthermore, the present invention aims to provide a semiconductor element including an n-type ohmic electrode excellent in thermal resistance. Furthermore, the present invention aims to provide a method for producing the above-mentioned semiconductor element.

The features of the present invention are as follows.

(1) A semiconductor element including an n-type gallium nitride-based compound semiconductor, and an electrode in ohmic contact with the semiconductor, wherein the electrode has a TiW alloy layer in contact with the semiconductor.

(2) The semiconductor element of (1) above, wherein the TiW alloy layer has a Ti concentration of 70 wt % or less.

(3) The semiconductor element of (2) above, wherein the TiW alloy layer has a Ti concentration of 40 wt% or less.

(4) The semiconductor element of (3) above, wherein the TiW alloy layer has a Ti concentration of 8 wt % or less.

(5) The semiconductor element of any one of (1)-(4) above, wherein the TiW alloy layer has a Ti concentration of 4 wt% or more.

(6) The semiconductor element of (1) above, wherein the W-Ti composition ratio of the TiW alloy layer is substantially constant in the thickness direction of the TiW alloy layer.

(7) The semiconductor element of (1) above, wherein the TiW alloy layer is formed by sputtering using a Ti-W target having a Ti content of 90 wt% or less.

(8) The semiconductor element of (1) above, wherein the TiW alloy layer is formed by sputtering using a Ti-W target having a Ti content of 10 wt%.

(9) The semiconductor element of (4) or (8) above, wherein the electrode is heat-treated.

(10) The semiconductor element of any one of (1) to (9) above, wherein the electrode has a metal layer laminated on the TiW alloy layer.

(11) The semiconductor element of (10) above, wherein the metal layer includes an Au layer.

(12) The semiconductor element of (11) above, wherein the layer includes a gold layer laminated directly on the above-mentioned TiW alloy layer.

(13) The semiconductor element of (11) above, wherein the metal layer is composed of a single layer of Au, or a laminated laminate having an Au layer as a top layer.

(14) The semiconductor element of (11) above, wherein the metal layer includes only a metal having the same melting point as Au or a higher melting point than Au.

(15) The semiconductor element of (10) above, wherein the metal layer does not contain Rh.

(16) The semiconductor element of any one of (1) to (15) above, wherein the electrode surface has an arithmetic mean roughness Ra of 0.02 micrometer or less.

(17) A method for producing a semiconductor element, the method including: a step of forming a TiW alloy layer as a part of an electrode on a surface of an n-type gallium nitride-based compound semiconductor.

(18) The production method of the above (17), wherein the TiW alloy layer is formed by sputtering using a Ti-W target.

(19) The production method of (18) above, wherein the TiW alloy layer has a Ti concentration of 70 wt% or less.

(20) The production method of (18) above, further comprising: a step of heat-treating the TiW alloy layer.

In the present invention, the TiW alloy consists substantially only of Ti and W (tungsten). According to the present invention, it is possible to obtain a semiconductor element including an n-type ohmic electrode forming a good ohmic contact with an n-type GaN-based semiconductor. According to a preferred embodiment of the present invention, it is possible to obtain a semiconductor element comprising an n-type ohmic electrode, preferably using said n-type ohmic electrode as a contact electrode. According to a preferred embodiment of the present invention, a semiconductor element including an n-type ohmic electrode with better thermal resistance can be obtained.

Description of drawings

1 is a schematic diagram of the structure of a GaN-based compound semiconductor device according to an embodiment of the present invention, FIG. 1(a) is a top view, and FIG. 1(b) is a cross-sectional view taken along line X-Y of FIG. 1(a).

Fig. 2 shows observation images of electrode surfaces by a differential interference microscope.

Figure 3 shows the compositional analysis results along the electrode direction by Auger electron spectroscopy.

Fig. 4 shows observation images of electrode surfaces by a differential interference microscope.

Fig. 5 shows observation images of electrode surfaces by a differential interference microscope.

Fig. 6 shows the compositional analysis results along the electrode depth direction by Auger electrode spectroscopy.

The meanings of the symbols in Figure 1 are as follows:

1 substrate, 2 first buffer layer, 3 second buffer layer, 4n type contact layer, 5 active layer, 6p type cladding layer, 7p type contact layer, P1n side electrode, P2p side electrode, P21p side ohmic electrode, P22p Side bonding electrodes, 100 semiconductor elements.

Detailed ways

The present invention can be applied to any element including an n-type GaN-based semiconductor and an electrode forming an ohmic contact with the semiconductor, ie, an n-type ohmic electrode. The semiconductor element of the present invention includes a portion composed of a semiconductor other than a GaN-based semiconductor. Typically, the semiconductor element of the present invention is a light emitting element. Alternatively, for example, the semiconductor element may be an electronic element such as a light receiving element or an injection transistor.

In the semiconductor element of the present invention, the n-type GaN-based semiconductor on which the n-type ohmic electrode is formed may have any composition. The n-type GaN-based semiconductor may be undoped or doped with impurities as long as it exhibits n-type conductivity. Preferably, the n-type GaN-based semiconductor in contact with the TiW alloy layer is _{AlxGa1 -xN} (0≤x≤0.2). Furthermore, preferably, the n-type GaN-based semiconductor in contact with the TiW alloy layer has a carrier concentration of 1×10 ¹⁸ /cm ³ to 1×10 ²⁰ /cm ³ , preferably 5×10 ¹⁸ /cm ³ to 5× 10 ¹⁹ /cm ³ carrier concentration. In particular, an n-type GaN-based semiconductor having a carrier concentration controlled in the above-mentioned preferable concentration range by doping an n-type impurity is preferable. This type of n-type impurity is not limited, and any known n-type impurity such as Si, Ge, or the like can be applied to a GaN-based semiconductor. In the semiconductor element of the present invention, it may be formed by, for example, MOVPE (metal organic vapor deposition), HVPE (hydride vapor deposition), MBE (molecular beam epitaxy), or formed thereon by a high pressure method, a liquid phase method, etc. n-type GaN-based semiconductor for n-type ohmic electrodes. The n-type GaN-based semiconductor can be produced as a thin film on a substrate, or can be the substrate.

In the semiconductor element of the present invention, an n-type ohmic electrode is also used as a contact electrode. Alternatively, in addition to the n-type ohmic electrode, the semiconductor element may have one or more contact electrodes electrically connected to the n-type ohmic electrode. When an n-type ohmic electrode is also used as a contact electrode, an electrode having a higher flatness than a surface exhibits a better bonding state of the electrode with a bonding wire or solder, which improves yield in a bonding process using an automatic machine. Specifically, the arithmetic mean roughness Ra of the surface of the n-type ohmic electrode also serving as the contact electrode is preferably equal to or less than 0.02 micrometer.

For the semiconductor element of the present invention, the method of forming the TiW alloy layer contained in the n-type ohmic electrode is not limited, and a conventionally known method of forming a TiW alloy thin film can be appropriately used. Preferably, the TiW alloy layer can be formed by using sputtering. Details of the Ti-W target can be known from JP-A-5-295531 (USP 5,470,527), JP-A-4-193947, JP-A-4-293770 (USP 5,160,534) and gas well-known techniques. In addition to Ti and W, a TiW alloy layer formed using a Ti-W target may include impurities inevitably contained in the target. It is acceptable for the TiW alloy layer to contain such impurities that are difficult to remove from the starting material. In the semiconductor element of the present invention, the film thickness of the TiW alloy contained in the n-type ohmic electrode is, for example, 0.01 μm to 1 μm, preferably, 0.05 μm to 0.5 μm. The Ti concentration of the TiW alloy layer is not particularly limited. However, when the Ti content in the Ti-W target is less than 5 wt% in the case of formation by sputtering, the adhesion between the formed TiW alloy thin film and the substrate becomes weak, and it is said that the film is easy to change from Substrate separation (USP 5,470,527). When the Ti content of the Ti-W target is less than 5 wt%, the formed TiW alloy layer has a Ti concentration of less than 4 wt%, and thus preferably, the TiW alloy layer has a Ti concentration of not less than 4 wt%. As shown in the following experimental examples, the thermal resistance of n-type ohmic electrodes becomes better when the TiW alloy layer in the electrodes has a lower Ti concentration. Therefore, preferably, the Ti concentration of the TiW alloy layer is equal to or less than 40 wt%, more preferably equal to or less than 20 wt%, more preferably equal to or less than 8 wt%.

In the TiW alloy layer, preferably, the composition ratio of W and Ti is substantially constant in the thickness direction of the layer. When the composition ratio of W and Ti is constant, the diffusion of W atoms and Ti atoms does not occur because of the lack of density gradient. Therefore, it is known that the properties of the n-type ohmic electrode change when the semiconductor element is placed in a high-temperature environment.

In the semiconductor element of the present invention, the n-type ohmic electrode may be a laminated laminate composed of a TiW alloy layer in contact with the n-type GaN-based semiconductor and a metal layer laminated on the TiW alloy layer. The metal layer may be formed of any metal material (either a single metal or an alloy). Furthermore, the metal layer may be a single layer or have a laminated structure. In order to reduce the resistance of the electrodes, preferably, the metal layer is formed of a metal with high conductivity, such as Ag, Cu, Au, Al and the like. In order to reduce thermal stress applied to the TiW alloy layer when the n-type ohmic electrode is formed according to such lamination, it is preferable to form the metal layer as an Au layer or a laminated laminate of an Au layer and other metal layers. This is because Au is a soft and easily deformable metal. By reducing thermal stress applied to the TiW alloy layer, problems such as deformation and separation of the n-type ohmic electrode, and contact instability between the n-type ohmic electrode and the n-type GaN-based semiconductor can be prevented from occurring. This effect is considered to be particularly pronounced when an Au layer is directly laminated onto a TiW alloy layer. When the n-type ohmic electrode is the above-mentioned laminated laminate, the layer exposed on the surface of the laminated laminate, that is, the top layer of the metal layer laminated on the TiW alloy layer is chemically stabilized by such as Au, platinum group elements, etc. Metal composition, thereby improving resistance to erosion of n-type ohmic electrodes. When an n-type ohmic electrode is also used as a contact electrode, preferably, the top layer is an Au layer. When the n-type ohmic electrode is the above-mentioned laminated laminate and the metal layer to be laminated on the TiW alloy layer contains an Al layer, the electrode exhibits degraded thermal resistance. Therefore, from the viewpoint of thermal resistance, it is preferable that the metal layer does not contain Al. When laminating a metal layer including an Au layer on a TiW alloy layer, it is preferable to form a metal layer including only a metal layer having the same melting point as Au or a higher melting point than Au in consideration of thermal resistance.

The ohmic contact between the n-type ohmic motor and the n-type GaN-based semiconductor in the semiconductor element of the present invention is not produced by the reaction of the product of the chemical reaction containing Rh, unlike the electrode disclosed in JP-A-11-8410 . Therefore, when the n-type ohmic electrode in the semiconductor element of the present invention is the above-mentioned laminated laminate, the metal layer to be laminated to the TiW alloy layer may not contain Rh.

In the semiconductor element of the present invention, heat treatment of the n-type ohmic electrode can be omitted. This is because an n-type ohmic electrode in contact with an n-type GaN-based semiconductor at the TiW alloy layer exhibits a lower level of contact resistance that causes no practical problems, even without heat treatment. When the heat treatment of the n-type ohmic electrode can be omitted, there are advantages that the time required for production can be shortened, and the degree of freedom in the design of the production process of the semiconductor element can be increased. Furthermore, when heat treatment is omitted, the problem of roughening of the electrode surface due to heat treatment is solved by itself. Therefore, n-type ohmic electrodes are suitable for electrodes that also serve as contact electrodes.

On the other hand, in the semiconductor element of the present invention, heat treatment of the n-type ohmic electrode may be arbitrarily performed. The temperature and time of the heat treatment can be appropriately set depending on the thermal resistance of the electrode as long as the desired properties are not impaired. As the atmospheric gas used for the heat treatment, preferably, an inert gas such as nitrogen, a rare gas, or the like is used. When the n-type ohmic electrode is the above-mentioned laminated laminate, the heat treatment may be applied after the formation of the laminated laminate is completed. Alternatively, for example, the heat treatment may be applied when forming the TiW alloy layer, and then the metal layer may be laminated on the TiW alloy layer. When heat treatment is applied to the n-type ohmic electrode, diffusion of components of the n-type GaN-based semiconductor into the TiW alloy layer or diffusion of components of the TiW alloy into the n-type GaN-based semiconductor may occur. However, such diffusion is acceptable as long as the effects of the present invention are not impaired.

example

The present invention will be explained in detail below by referring to examples, which are not limiting.

<Experimental Example 1, (Example 1, Comparative Example 1)>

A GaN-based semiconductor element having the structure shown in FIG. 1 was prepared and evaluated. The GaN-based semiconductor element 100 shown in FIG. 1 is a light emitting diode having the following structure: a first buffer layer 2, a second buffer layer 3, an n-type contact layer 4, an active layer 5, a p-type capping layer 6, and a p The type contact layer 7 is laminated on the substrate 1 in this order. On the n-type contact layer 4, an n-side electrode P1 that makes ohmic contact with the n-type contact layer 4 is formed. On the p-type contact layer 7, a p-side electrode P2 that makes ohmic contact with the p-type contact layer 7 is formed. The p-side electrode is composed of a p-side ohmic electrode P21 formed on the entire surface of the p-type contact layer 7, and a p-side bonding electrode P22 is electrically connected to the p-side ohmic electrode P21. The GaN-based semiconductor element 100 is prepared as follows.

(crystal growth)

A sapphire substrate 1 (2 inches in diameter) was set in an MOVPE growth furnace, and the substrate temperature was raised to 1100° C. while flowing hydrogen gas, thereby cleaning the surface of the substrate 1 . Then, the substrate temperature was lowered to 500° C., and a first GaN film composed of GaN with a film thickness of about 30 nm was grown on the substrate 1 using hydrogen gas as a carrier gas and ammonia gas and TMG (trimethylgallium) as starting material gases. buffer layer 2. Then, the supply of TMG was stopped, and the substrate temperature was raised to 1000°C. Using TMG and ammonia as starting material gases, a second buffer layer 3 composed of non-doped GaN with a film thickness of about 2 micrometers was grown. Then, silane gas was additionally supplied to grow n-type contact layer 4 having a film thickness of 3 micrometers, composed of GaN doped with Si (silicon) to achieve a concentration of about 5×10 ¹⁸ /cm ³ . Then, the supply of TMG and silane gas was stopped, the substrate temperature was lowered to 800°C, and a barrier composed of _{InxGa1 -xN} was alternately grown using TMG, TMI (trimethylindium), silane gas, and ammonia gas layer and a well layer composed of In _y Ga _1-y N (y>x) to form the active layer 5 of the multi-quantum well structure with barrier layers at both ends. The film thickness of the barrier layer was set to 10 nm, and the film thickness of the well layer was set to 2 nm. In addition, the In composition y in the well layer was adjusted to achieve a lasing wavelength of 400 nm. Then, the supply of TMG, TMI, _and silane gases was stopped, and the substrate temperature was raised to 1000°C again, and the doped The p-type cap layer 6 composed of Al _0.1 Ga _0.9 N of Mg (magnesium) at a concentration of about 5×10 ¹⁹ /cm ³ is grown to a film thickness of 30 nm. Then, the supply of TMA was stopped, and the p-type contact layer 7 made of GaN doped with Mg at a concentration of about 8×10 ¹⁹ /cm ³ was grown to a film thickness of 120 nm. After the growth of p-type contact layer 7 was completed, substrate heating was stopped, supply of starting material gases other than ammonia gas was stopped, and the substrate temperature was lowered to room temperature. Thereafter, in order to activate the magnesium in the Mg-doped p-type cap layer 6 and the Mg-doped p-type contact layer 7 , heat treatment at 900° C. for 1 minute was performed in a nitrogen atmosphere in an RTA apparatus (rapid thermal annealing apparatus).

(Formation of p-side ohmic electrode)

Next, a p-side ohmic electrode P21 is formed in which a Pd layer (film thickness 30 nm), an Au layer (film thickness 100 nm), and a Ni layer (film thickness 10 nm) are laminated in this order to the p-type contact layer 7 by electron beam evaporation (wafer top layer) surface. As shown in FIG. 1( a ), the p-side ohmic electrode P21 has an orthogonal lattice pattern when viewed from the top. In other words, the p-side ohmic electrode P21 is an opening electrode in which a large number of square openings penetrating the electrode film are regularly provided along the length and width of the film, and the surface of the p-side contact layer 7 is exposed from the openings. The size of the opening for one side of the square is 8 micrometers, and the distance between adjacent openings (the width of the electrode portion) is 2 micrometers for the length and width. The p-side ohmic electrode P21 is patterned by a conventional lift-off method. That is, a resist film patterned into a predetermined shape by photolithography is formed on the surface of the p-type contact layer 7, an electrode film having the above-described laminated structure is formed on the resist film, and the resist mask is peeled off. , thereby removing the electrode film deposited on the resist mask. Using RTA equipment, heat treatment is performed on the p-side ohmic electrode P21. Thereafter, the conditions of the heat treatment were a nitrogen atmosphere, 500° C., and 1 minute.

(Formation of n-side electrode)

Next, a resist mask having a given shape is formed on p-type contact layer 7 on which p-side ohmic electrode P21 is formed. The layer was etched from the p-type contact layer 7 side by RIE (Reactive Ion Etching) using chlorine gas to expose the surface of the n-type contact layer 4 as shown in FIG. 1 . After exposure, TiW alloy layer (thickness 100nm), Au layer (thickness 100nm), Pt layer (thickness 80nm), Au layer (thickness 80nm), Pt layer (thickness 80nm), An Au layer (film thickness 80 nm), a Pt layer (film thickness 80 nm), and an Au layer (film thickness 80 nm) are laminated in this order on the surface of n-type contact layer 4 to form n-side electrode P1. For forming a TiW alloy layer by RF sputtering, a Ti-W target (manufactured by Mitsubishi Materials Corporation, product name: 4NW-10wt%Ti target) was used as a target, Ar (argon gas) was used as a sputtering gas, and 200W The RF power is 1.0×10 -1 Pa and the sputtering pressure is 1.0×10 ^-1 Pa. The Ti-W target had a Ti content of 10.16 wt % (analytical value obtained by absorptiometry) and 15 ppm of Fe (iron) as an impurity (analytical value obtained by ICP). The n-side electrode P1 is patterned as in the lift-off method in the patterning of the p-side ohmic electrode P21.

(Formation of p-side junction electrode)

Next, a p-side bonding electrode P22 was formed on the p-side ohmic electrode P21 by electron beam evaporation in which Ti having a film thickness of 20 nm and Au having a film thickness of 600 nm were laminated in this order. Then, using plasma CVD, a passivation film (not shown, film thickness 300 nm) made of SiO ₂ was formed to cover the wafer surface except for the n-side electrode P1 and the p-side bonding electrode P22. Subsequently, using an RTA apparatus, the n-side electrode P1 and the p-side bonding electrode P22 are subjected to heat treatment. The conditions of the heat treatment were a nitrogen atmosphere, 500° C., and 1 minute. In this way, 350 micron square light emitting diodes were formed on the wafer (Example 1).

(Evaluate)

The light-emitting diode elements prepared through the above steps were evaluated as formed on wafers without element separation (dicing into chips). FIG. 2 shows observation images of the surface of the n-side electrode P1 using a differential interference microscope. As shown in FIG. 2, the surface of the n-side electrode P1 is flat and not roughened. Although multiple diagonal lines were observed at the center of the electrode, they were scratches generated during electrical property evaluation when contacted with the probe tip of the automated probe, and did not exhibit surface roughness. Vf (forward voltage) when a forward current of 20 mA was made to flow in the element was measured with an automatic detector, and found to be 3.4V. This value is a standard value as Vf of a light emitting diode having a lasing wavelength of 400 nm. It should thus be understood that the contact resistance of n-side electrode P1 and n-type contact layer 4 is sufficiently low to avoid practical problems. This also means that a good ohmic contact is formed between the n-side electrode P1 and the n-type contact layer 4 . Shown in FIG. 3 is the result of component analysis along the depth direction of the n-side electrode P1, which was obtained using Auger electron spectroscopy (AES). From FIG. 3 , it should be understood that the n-side electrode P1 and the n-type contact layer 4 are in contact at the TiW alloy layer. In addition, it should also be understood that the composition ratio of Ti and W in the TiW alloy layer is substantially constant in the thickness direction.

For comparison, a light emitting diode element (comparative example 1) having the same structure as the above element (example 1) was prepared by the same method as used for the above element except that the n-side electrode was an Al layer formed by electron beam evaporation (film thickness 600nm). As a result of the evaluation of the element of Comparative Example 1, although the Vf measured by the automatic probe was at the same level as that of the element of Example 1, the surface of the n-side electrode was remarkably roughened.

<Experimental Example 2 (Example 2, Comparative Example 2)>

A test wafer GaN buffer was prepared by MOVPE, in which a Si-doped GaN layer was grown at low temperature on a sapphire substrate (2 inches in diameter). The following two types of electrodes of electrode A and electrode B were formed on the buffer layer, and the electrodes were evaluated.

Electrode A: formed by laminating a TiW alloy layer (film thickness 100 nm) and an Au layer (film thickness 100 nm) in this order, and applying heat treatment at 500° C. for 1 minute (Example 2).

Electrode B: formed by laminating an Al layer (film thickness 100 nm) and an Au layer (film thickness 100 nm) in this order, and applying heat treatment at 400° C. for 1 minute (comparative example 2).

The respective metal layers included in the electrodes A and B were formed by RF sputtering. The film formation conditions for the TiW alloy layers contained in the electrodes A and B were the same as those for the TiW alloy layers used in Experimental Example 1. Electrodes are patterned by photolithography and lift-off. For photolithography, the photolithography mask used for the patterning of the n-side electrode P1 in Experimental Example 1 was used.

FIG. 4 shows observation images of the surface of the electrode A by a differential interference microscope. In addition, FIG. 5 shows an observation image of the surface of the electrode B by a differential interference microscope. As shown in Fig. 4, the surface of electrode A formed by first forming a TiW alloy layer on the Si-doped GaN layer and then laminating the Au layer on the TiW alloy layer was flat and did not change even though the heat treatment was 500°C. rough. The arithmetic mean roughness Ra of the surface of the electrode A was measured and found to be 0.014 µm. Since the Ra of the Si-doped GaN layer as the pedestal surface for electrode formation is about 0.004 μm, the Ra of the electrode A surface is 4 times or less than the pedestal surface. In contrast, as shown in FIG. 5, although the heat treatment temperature was 400°C, the surface of the electrode B obtained by forming an Al layer and then laminating a TiW layer and an Au layer on the Al layer was remarkably rough. The arithmetic mean roughness Ra of the surface of the electrode B was measured and found to be 0.07 µm. This is 18 times the surface roughness of the Si-doped GaN layer as the surface of the base.

FIG. 6 shows the results of compositional analysis along the depth direction of electrode B, obtained using Auger electron spectroscopy. As shown in FIG. 6, in electrode B, Au in the Au layer formed on the TiW alloy layer diffuses across the TiW alloy layer to the Al layer side, and Al and Au both. Al also diffuses across the TiW alloy layer to the Au layer side. According to Experimental Example 2, it is understood that the electrode A with the TiW alloy layer in contact with the Si-doped GaN layer exhibits good thermal resistance, but the electrode with no TiW alloy layer in contact with the Si-doped GaN layer B exhibits lower thermal resistance. It is believed that one of the reasons for the lower thermal resistance of electrode B is the presence of an Al layer in electrode B, which has a low melting point and a significantly different coefficient of thermal expansion from GaN.

The known Ti concentration contained in the TiW alloy film formed by sputtering using a Ti-W target tends to be smaller than the Ti content of the target, 80% or less of the Ti content in the target (JP-A-5-295531, USP 5,470,527 ). In the above-mentioned Experimental Example 1 and Experimental Example 2, since a Ti-W target containing 10 wt% of Ti was used, it is considered that Ti in the TiW alloy layer contained in the n-type ohmic electrode of the samples prepared in these Experimental Examples The concentration is less than or equal to 8wt%.

<Experimental Example 3 (Examples 3 and 4, Comparative Examples 3 and 4)>

Sample preparation for evaluation is as follows. In the same manner as in Experimental Example 1, GaN-based semiconductor layers from the first buffer layer to the p-type contact layer were grown on a sapphire substrate to give a GaN-based semiconductor laminated wafer having a light emitting diode structure. Next, the formation of the p-side ohmic electrode was omitted, and an n-side electrode was formed. In the same manner as in Experimental Example 1, an n-side electrode was formed on the surface of the n-type contact layer (doped Sin-type GaN having a Si concentration of about 5×10 ¹⁸ /cm ³ ) exposed by RIE. The n-side electrodes were the following four types (sample A - sample D).

Sample A: An n-side electrode composed of a TiW alloy layer (film thickness 100 nm) and an Au layer (film thickness 100 nm) laminated on the TiW alloy layer (Example 3).

Sample B: n-side electrode composed of a W layer (film thickness 100 nm) and an Au layer (film thickness 100 nm) laminated on the W layer (comparative example 3).

Sample C: n-side electrode composed of a Ti layer (film thickness 100 nm) and an Au layer (film thickness 100 nm) laminated on the Ti layer (comparative example 4).

Sample D: TiW alloy layer (film thickness 100nm) and Au layer (film thickness 100nm), Pt (film thickness 80nm), Au layer (film thickness 80nm), Pt layer laminated on the TiW alloy layer in the following order (thickness 80nm), Au layer (thickness 80nm), Pt layer (thickness 80nm) and Au layer (thickness 80nm) (Example 4).

The respective metal layers contained in the n-side electrodes of the respective samples were formed by RF sputtering. The film formation conditions for the TiW alloy layers contained in Sample A and Sample D were the same as those for the TiW alloy layer used in Experimental Example 1. However, as in Experimental Example 1, the TiW alloy layer of Sample A was formed using a Ti-W target containing 10 wt% Ti, while the TiW alloy layer of Sample D was formed using a Ti-W target containing 90 wt% Ti. It is considered that the Ti concentration of the TiW alloy layer in Sample D is about 70 wt% or less. The n-side electrode was patterned in the same manner as Experimental Example 1 for either sample. A wafer with an n-side electrode formed in this way was used as a sample for evaluation.

(Evaluation before heat treatment)

The contact resistance of the n-side electrode of each sample was evaluated based on the voltage required to flow a current of 20 mA between the n-side electrodes of two adjacent elements on the wafer (hereinafter also referred to as "n-n voltage"). Since the voltage drop co-occurring with the current inside the n-type contact layer is negligibly small, the n-n voltage reflects the contact resistance between the n-side electrode and the n-type contact layer. In other words, samples with higher n-n voltage had higher contact resistance between the n-side electrode and the n-type contact layer. The n-n voltage of each sample having an n-side electrode formed by sputtering was measured using an automatic detector. The result is as follows.

Sample A: 0.3V.

Sample B: 0.7V.

Sample C: 0.2V.

Sample D: 0.3V.

The n-n voltage of Sample A and Sample D is substantially equivalent to the n-n voltage of 0.2 V measured separately from the sample of Example 1. From this, it should be understood that an electrode in contact with the n-type GaN-based semiconductor at the TiW alloy layer can be used as a formed ohmic electrode having a lower contact resistance. The electrode surfaces of samples A and D were observed with a differential interference microscope and found to be quite flat.

Although the electrode of sample A is in contact with the n-type contact layer at the TiW alloy layer containing a relatively low concentration (not more than 8% as mentioned above) of Ti, it is worth noting that the n-n voltage of sample A is not higher than that of sample B with the electrode Half of the n-n voltage of , the electrode is in contact with the n-type contact layer at the W layer. This implies that the properties of the TiW alloy layer in the electrode of Sample A are not a simple average of the properties of Ti and W. It should also be understood that without heat treatment, the contact resistance of the electrode in contact with the n-type GaN-based semiconductor at the TiW alloy layer hardly depends on the Ti concentration of the TiW alloy layer, because the n–n voltage of sample A and sample D is equal. This means that the electrode has stable properties and is easy to produce.

(Evaluation after heat treatment)

Next, each sample was heat-treated at 500° C. for 1 minute in a nitrogen atmosphere. The n-n voltages of the respective samples after heat treatment were as follows.

Sample A: 0.2V.

Sample B: 0.7V.

Sample C: 2.4V.

Sample D: 3.2V.

The electrode surface after heat treatment was observed. As a result, the electrode surfaces of Sample A and Sample B were in good condition, that is, flat without becoming rough, while the electrode surfaces of Sample C and Sample D were rough.

It should be understood that since the surface of the electrode was not roughened by heat treatment and the n-n voltage was not substantially changed by heat treatment in Sample A, the TiW alloy formed by sputtering using a Ti-W target containing 10 wt% Ti would be The electrode at the layer in contact with the n-type GaN-based semiconductor has quite good thermal resistance. It should also be understood that the electrode formed by sputtering can be used after heat treatment under the conditions employed in the laboratory 3 . When heat treatment is applied, the structure of the electrode is stabilized. Therefore, fundamental changes in electrode properties when the element is exposed to high temperatures during use can be prevented.

In contrast, the electrode of sample D in contact with the n-type contact layer at the TiW alloy layer formed using a target with a Ti content of 90 wt% clearly showed increased n–n voltage and degraded surface due to heat treatment. This trend is general for the electrode of sample C where the Ti layer is in contact with the n-type contact layer. From these results, it should be understood that the heat treatment conditions employed in Experimental Example 3 are suitable for the electrode in contact with the n-type GaN-based semiconductor at the TiW alloy layer formed by sputtering using a Ti-W target containing 90 wt% Ti strict.

The present invention is not limited to the above examples, and can be modified in various ways without departing from the gist of the invention. For example, in the GaN-based semiconductor element 100 shown in FIG. 1, the p-side junction electrode P22 may have the same structure as the n-side electrode P1, and in this case the electrodes may be formed through the same steps, thus simplifying production. craft.

This application is based on Patent Application Nos. 2005-112610 and 2006-31741 filed in Japan, the entire contents of which are incorporated herein by reference.

Claims (20)

CLAIMS 1. A semiconductor element comprising a semiconductor element of an n-type gallium nitride-based compound semiconductor, and an electrode in ohmic contact with the semiconductor, wherein the electrode has a TiW alloy layer in contact with the semiconductor. 2. The semiconductor element according to claim 1, wherein the TiW alloy layer has a Ti concentration of 70 wt% or less. 3. The semiconductor element according to claim 2, wherein the TiW alloy layer has a Ti concentration of 40 wt% or less. 4. The semiconductor element according to claim 3, wherein the TiW alloy layer has a Ti concentration of 8 wt% or less. 5. The semiconductor element according to any one of claims 1 to 4, wherein the TiW alloy layer has a Ti concentration of 4 wt% or more. 6. The semiconductor element according to claim 1, wherein a W-Ti composition ratio of the TiW alloy layer is substantially constant in a thickness direction of the TiW alloy layer. 7. The semiconductor element according to claim 1, wherein the TiW alloy layer is formed by sputtering using a Ti-W target having a Ti content of 90 wt% or less. 8. The semiconductor element according to claim 7, wherein the TiW alloy layer is formed by sputtering using a Ti-W target having a Ti content of 10 wt%. 9. The semiconductor element according to claim 4 or 8, wherein the electrode is heat-treated. 10. The semiconductor element according to any one of claims 1 to 9, wherein the electrode has a metal layer laminated on the TiW alloy layer. 11. The semiconductor element according to claim 10, wherein the metal layer comprises an Au layer. 12. The semiconductor element according to claim 11, wherein said layer includes an Au layer laminated directly on said TiW alloy layer. 13. The semiconductor element according to claim 11, wherein the metal layer consists of a single layer of Au, or of a laminated laminate having an Au layer as a top layer. 14. The semiconductor element according to claim 11, wherein the metal layer includes only a metal having the same melting point as Au or a higher melting point than Au. 15. The semiconductor element according to claim 10, wherein the metal layer does not contain Rh. 16. The semiconductor element according to any one of claims 1 to 15, wherein the electrode surface has an arithmetic mean roughness Ra of 0.02 micrometer or less. 17. A method for producing a semiconductor element, the method comprising: a step of forming a TiW alloy layer as a part of an electrode on a surface of an n-type gallium nitride-based compound semiconductor. 18. The production method according to claim 17, wherein the TiW alloy layer is formed by sputtering using a Ti-W target. 19. The production method according to claim 18, wherein the TiW alloy layer has a Ti concentration of 70 wt% or less. 20. The production method according to claim 18, wherein the method further comprises the step of heat-treating the TiW alloy layer.

Images