CN101145729A - DC-DC converter and method - Google Patents
DC-DC converter and method Download PDFInfo
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- CN101145729A CN101145729A CNA2007101542089A CN200710154208A CN101145729A CN 101145729 A CN101145729 A CN 101145729A CN A2007101542089 A CNA2007101542089 A CN A2007101542089A CN 200710154208 A CN200710154208 A CN 200710154208A CN 101145729 A CN101145729 A CN 101145729A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of DC power input into DC power output
- H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
- H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
- H02M3/10—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
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Abstract
A DC-DC converter and method for compensating for errors in the DC-DC converter. The DC-DC converter includes an inductor coupled for receiving a source of operating voltage through a plurality of switches. The switches are controlled by a control circuit that has first and second circuit paths that are substantially parallel to each other. Each circuit path is comprised of two switched capacitor comparators that are connected in series. The circuit paths function such that during one portion of a clock period one of the circuit paths operates in an error correction mode and the other circuit path operates in a normal mode. During a different portion of the clock period the operational modes of the circuit paths switch. This allows for a calibration interval in a sampled system in which at least one circuit path is always active and responsive to the input signals in a desired manner.
Description
Technical field
The present invention relates generally to adjuster circuit, relate in particular to DC to the DC transducer.
Background technology
Battery operated device such as mobile phone, portable computer, calculator, video camera, personal digital assistant (PDAs), PlayStation 3 videogame console/PS3 etc. generally comprise the DC-DC transducer that produces constant supply voltage in load.Though provide constant voltage in load, cell voltage reduces along with battery discharge.These circuit comprise switch, and it is using low loss switching alternately to connect inductor between battery and the load and between load and ground, and described switch operates in fixing frequency usually.In other words, circuit is changed connection like this, so that during the part of clock cycle, inductor is connected between battery and the load, and during another part of clock cycle, switch is connected inductor between load and the ground.As selection, they can alternately connect inductor between battery and the ground and between load and ground.Load is absorbed the large capacitor shunting of interchange (" AC ") component, and this alternating current component makes load voltage that low ripple be arranged.
The DC-DC transducer comprises negative feedback loop, and it makes the part of load voltage conform to reference voltage by the duty factor of revising switch.Stable negative feedback loop is difficult, because it comprises inductor and bridging condenser, and with the wide load current operation of scope.A technology that is used for stablizing feedback loop comprises that this loop of design has two series comparators, wherein first comparator produces electric current output in response to the load voltage error, and the duty factor of the second comparator control switch is so that the peak value inductor current is adapted to the output of first comparator.This technology is called Controlled in Current Mode and Based or electric current sequencing control.
Be connected at inductor during the time interval at load two ends, if load current is too low, its electric current may be oppositely.In order to stop this situation to occur, can in feedback loop, comprise the 3rd comparator.
Current circuit generally uses complementary matal-oxide semiconductor (CMOS) technology to make comparator.This technology provides the comparator that has low loss switching and can enter the low-power ready mode.Yet they use the high resistor of a lot of prices to come the electric current of restriction controller circuit.In addition, use the high resistor of CMOS technology manufacturing price to consume large-area semi-conducting material.Big parasitic capacitance is also introduced in large-area use, and this does not expect, because they have reduced conversion speed and have increased the power consumption of cmos device.
Therefore, exist DC-DC transducer and the needs that compensate the method for offset error in the DC-DC transducer.It is favourable that cost and time make the DC-DC transducer efficiently.
Brief description of drawings
Detailed explanation below reading in conjunction with the accompanying drawings will be better understood the present invention, and wherein identical reference symbol is specified components identical, and wherein:
Fig. 1 is the schematic diagram according to the DC-DC transducer of the embodiment of the invention;
Fig. 2 is the timing diagram that is used for the DC-DC transducer of Fig. 1;
Fig. 3 is the schematic diagram that is configured to the part of the DC-DC transducer of Fig. 1 of bias correcting operation mode;
Fig. 4 is the schematic diagram that is configured to the part of the DC-DC transducer of Fig. 3 of normal manipulation mode operation;
Fig. 5 is the schematic diagram that is configured to another part of the DC-DC transducer of Fig. 3 of bias correcting operation mode;
Fig. 6 is the schematic diagram that is configured to the part of the DC-DC transducer of Fig. 5 of normal manipulation mode operation;
Fig. 7 is the schematic diagram of another part of the DC-DC transducer of Fig. 1;
Fig. 8 is the schematic diagram of DC-DC transducer according to another embodiment of the present invention; With
Fig. 9 is the zero crossing detection circuit schematic diagram partly of the DC-DC transducer of Fig. 8.
Describe in detail
The present invention generally provides switch dc-dc (" DC-DC ") transducer, and it can receive input voltage V from battery
BATTAnd provide the output voltage of adjusting with lower voltage level.According to an embodiment, the present invention includes DC-DC transducer with inductor, this inductor has and is coupled to receive a terminal of input power signals by a plurality of switches and to be coupled to the another terminal of load.The switch repetitive operation is in the clock frequency of expectation, and has in response to the conversion of the signal that produces from control circuit (commutation instant) constantly.Control circuit has two circuit paths and adjusts load voltage makes itself and reference voltage that expected relationship be arranged, and each circuit paths is made up of a plurality of circuit elements.Circuit paths is operated like this, so that make the one or more circuit element in arbitrary path temporarily be transformed into the error correction pattern, and the element in another path remains on normal manipulation mode.This allow to eliminate the error relevant with circuit element, and the state of limit switch not.Preferably, during the first of first clock cycle, the element in path is with error correction pattern operation, and in remainder and all back of first clock cycle or during the second clock cycle, the element in path is operated with normal mode.During the second clock cycle, select output from these circuit elements.The advantage of present embodiment is that the instantaneous disturbing effect that is produced by the conversion from the error correction pattern to normal manipulation mode has been eliminated in fact.
According on the other hand, each circuit paths comprises voltage comparator, and it is in response to the part of load voltage and the difference between the applied reference voltage and produce output.Voltage comparator preferably includes the circuit element with filter, and this filter is suitable for stablizing the loop that (dote) has dynamic property.Filter is coupled so that output signal component to be provided, and this component is publicly-owned to two circuit paths, and obtains by integrated signal, and described signal equally produces from the input signal of the circuit element of two comparators.In addition, each circuit paths comprises second comparator, and it is in response to from the output signal of voltage comparator be provided to difference between the signal of electric charge of load during being illustrated in the concurrent clock cycle.The output of second comparator makes the switch commutation.
According on the other hand, be provided to the signal of the electric charge of load as expression at the voltage of capacitor two ends formation.Capacitor is discharged and quilt and the proportional current charges of the electric current of the inductor of flowing through at the section start of each clock cycle.
According on the other hand, constant electric current merges the proportional electric current of electric current with the described inductor of flowing through, to suppress circuit oscillation.Described constant electric current has the value according to input and load voltage derivation.
It should be noted that term " configuration " is used to describe the position of the switch.Therefore, switch can be configured to the Converting terminal of this switch is connected to another circuit element, that is, switch is closed, or switch can be configured to Converting terminal and be not connected with another circuit element, that is, switch is opened.
Fig. 1 is the schematic diagram according to the DC-DC transducer 10 of the embodiment of the invention.Shown in Fig. 1 is a plurality of switching capacities (" SC ") comparator 12,14,16 and 18, selector circuit 20, drive circuit 22 and voltage balancing circuit 24.SC comparator 12,14,16 and 18, selector circuit 20 and drive circuit 22 cooperations are to form control circuit 23.SC comparator 12 and 16 forms the part of circuit paths or signal, and SC comparator 14 and 18 forms the part of circuit paths or signal.In addition, DC-DC transducer 10 comprises a plurality of transistors 26,28,30 and 32 and integrating condenser 46.More particularly, SC comparator 12 has and is coupled to receive reference voltage V
REFInput 12
1With the input 12 that is coupled to output node 34
2, be coupled input, be coupled with the input of receive clock signal ACTA and the input 16 that is connected to SC comparator 16 with receive clock signal CALA
2Output.SC comparator 14 has and is coupled to receive reference voltage V
REFInput 14
1With the input 14 that is coupled to output node 34
2, be coupled input, be coupled with the input of receive clock signal ACTB and the input 18 that is connected to SC comparator 18 with receive clock signal CALB
2Output.Preferably, SC comparator 12 and 14 mates and comprises attenuating elements, comparator element and filter element mutually.Further describe SC comparator 12 and 14 with reference to figure 3 and Fig. 4.SC comparator 16 has and is coupled to receive input voltage V
INTInput 16
1, be coupled input, be coupled with the input of receive clock signal ACTA and the output that is connected to the input of selector circuit 20 with receive clock signal CALA.SC comparator 18 has and is coupled to receive input voltage V
INTInput 18
1, be coupled input, be coupled with the input of receive clock signal ACTB and the output that is connected to another input of selector circuit 20 with receive clock signal CALB.
The input of the output that selector circuit 20 has the output, the input that is connected to the output of SC comparator 16 that are connected to drive circuit 22, be connected to SC comparator 18 and be coupled input with receive clock signal CLK/2.The frequency that clock signal clk/2 have is the master clock signal CLK that master clock 50 provides
MATRHalf.
The output of voltage balancing circuit 24 is connected to the drain electrode of transistor 32, and the output of drive circuit 22 is connected to the grid of transistor 32.Voltage balancing circuit 24 is coupled with the input of receive clock signal CALA in addition and is coupled input with receive clock signal CALB.The source electrode of transistor 32 is coupled to receive operating voltage source, for example V
SS Store energy element 46 for example capacitor is coupling in transistor 32 two ends, that is, a terminal of capacitor 46 is connected to the source electrode of transistor 32 and a terminal of capacitor 46 is connected to the drain electrode of transistor 32.
Clock signal C ALA, ACTA, CALB, ACTB and CLK/2 are by being coupled to receive master clock signal CLK from master clock 50
MATRClock generator produce.
In operation, battery V
BATTBe coupling between power supply terminal 15 and the reference terminal 35.More particularly, battery V
BATTPlus end be connected to the transistor 26 of common connection and 28 source electrode, and negative terminal is coupled to receive operating voltage source, for example V
SSAs an example, operating voltage source V
SS Ground connection.SC comparator 12 and 14 is coupled to receive load voltage V
LOADWith reference voltage V
REFLoad voltage V
LOADBe also referred to as the transducer output signal.SC comparator 12 is coupled with receive clock signal CALA and ACTA, and SC comparator 14 is coupled with receive clock signal CALB and ACTB.Master clock 50 is with master clock signal CLK
MATRBe transferred to drive circuit 22 and clock generator 38.Be response master clock signal CLK
MATR, clock generator 38 clocking CALA, ACTA, CALB, ACTB and CLK/2.Clock signal C ALA and CALB determine error compensation at interval, and clock signal ACTA and ACTB are respectively as the enabling signal of SC comparator 12 and 14.Clock signal C ALA, ACTA, CALB cooperate with ACTB to place them to voltage V SC comparator 12 and 14
LOADAnd V
REFThe state of response.As an example, SC comparator 12 and 14 logic high states in response to clock signal C ALA, ACTA, CALB and ACTB.Clock signal clk/2 have master clock signal CLK
MATRHalf of frequency.
With reference now to Fig. 2,, it has shown clock signal C ALA, ACTA, CALB, ACTB, CLK/2 and master clock signal CLK
MATRTiming Figure 60.Clock signal C ALA, ACTA, CALB, ACTB and CLK/2 are by being coupled to receive master clock signal CLK from master clock 50
MATR Clock generator 38 produce.According in this example shown in timing Figure 60, master clock 50 has the clock cycle of 0.2 microsecond (μ s).Therefore clock signal clk/2 have the cycle of 0.4 μ s.Clock signal C ALA one group of time interval during replacing the first of clock cycle for high, alternately the time interval during the first of clock cycle be a height and clock signal C ALB is in another group.Clock signal C ALA is called odd cycle during the part of high clock cycle of described group, and clock signal C ALB is called the even cycle during the part of high clock cycle of described group.During clock signal C ALA turned back to after zero and extends to the odd cycle of back idol end cycle, clock signal ACTA was high a period of time.Equally, during clock signal C ALB turned back to after zero and extends to the even cycle of back odd cycle end, clock signal ACTB was high a period of time.
Reference voltage V
REFBe applied to input 12
1With 14
1, and load voltage V
LOADFeed back to input 12 from output node 34
2With 14
2 Input 16
1With 18
1Be coupled the voltage V that appears at capacitor 46 two ends with reception
INTVoltage V
INTBe also referred to as internal reference signal.Comparator 12 receives identical clock signal with 16, that is, and and clock signal C ALA and ACTA, and comparator 14 and 18 receives identical clock signal, that is, and clock signal C ALB and ACTB.SC comparator 12 and 14 makes from the load voltage V of node 34 feedbacks
LOADDecay, the signal and the reference voltage V that relatively decay as the zero offset comparator
REF, and filter comparison signal to produce the filtration output signal that is transferred to SC comparator 16 and 18 respectively.In response to load voltage V
LOADA part and reference voltage V
REFBetween the SC comparator 12 and the 14 filtered input signal V of difference
REFAnd feedback signal, to produce the output signal of integration.SC comparator 12 and 14 output signal are also referred to as control path signal or inferior signal.More particularly, 12 decay of SC comparator and output of filtration transducer or load signal V
LOADWith reference signal V
REF, relatively decay then and the load signal that filters and the reference signal of decay and filtration, and introduce the offset error correction signal to produce time signals from SC comparator 12.Equally, 14 decay of SC comparator and output of filtration transducer or load signal V
LOADWith reference signal V
REF, relatively decay then and the load signal that filters and the reference signal of decay and filtration, and introduce the offset error correction signal to produce time signals from SC comparator 14.Therefore, SC comparator 12 and 14 is in response to load voltage V
LOADA part and reference voltage V
REFBetween difference and produce output.
At the section start of each clock cycle, capacitor 46 is discharged in response to the short pulse that is produced by drive circuit 22.After by discharge, the flowed through reflection of electric current of transistor 26 of capacitor 46 charges.Voltage balancing circuit 24 uses the electric current of the transistor 28 of flowing through to produce the reflection electric current I
IMAGE, it is general more much smaller and proportional with the electric current of the inductor 36 of flowing through than the electric current of the transistor 28 of flowing through.Therefore, drive circuit 22 generates drive signal to produce the reflection electric current I
IMAGE, it is the reflection of electric current of transistor 28 of flowing through.Voltage balancing circuit 24 conforms to during the time interval of its conduction closely by the voltage that makes transistor 26 and 28 drain electrode place, the currents match of electric current with the transistor 26 of flowing through of the transistor 28 of guaranteeing to flow through.Therefore, the voltage at capacitor 46 two ends is as being illustrated in the signal that is applied to the electric charge of load during the concurrent clock cycle.Except the section start in each clock cycle was capacitor 46 discharges, drive circuit 22 also was converted, logic low-voltage is applied to the grid of transistor 26,28 and 30.
In response to the output signal from selector circuit 20, drive circuit 22 changes or conversion appear at the voltage of its output.Therefore, change to logic high voltage level from logic low voltage level, thereby close transistor 26 and 28 and turn-on transistor 30 at the voltage of the grid of transistor 26,28 and 30.So, the electric current of transistor 26 guiding between the initial sum conversion of each clock cycle is instantaneous, and transistor 30 finishes up to the clock cycle from changing instantaneous guide current.Drive circuit 22 comprises device that disable transistor 26 and 30 is conducted electricity simultaneously and provides the device of short pulse at the section start of each clock cycle to the grid of transistor 32 that this short pulse makes capacitor 46 discharges.
Suppose input voltage V
BATT, load voltage V
LOADWith load current I
LOADSelected, so that make the direction of inductor 36 nonreversible its conduction of current, and the DC-DC transducer is stable, that is, and and voltage V
LOADLess than cell voltage V
BATTHalf, capacitor 46 will charge from no-voltage at the flowed through reflection of electric current of inductor 36 of the section start of each clock cycle, its under limit from transistor 26 transmission.Capacitor 46 is charged to the voltage that conforms to the output voltage of SC comparator 12, at this SC comparator 16 signal application is arrived drive circuit 22, this becomes transistor 26 not have conductibility and transistor 30 conductibility that become, to keep the electric current that flows into inductor 36.
The total electrical charge that is sent to load is proportional with the electric charge that is provided by transistor 26, and along with the sub-fraction of clock cycle increases monotonously, this period crystals pipe 26 is held open and guide current.Under limit, transistor 26 has conductibility to appear at the part of each clock cycle to the transistor 30 conductive conversion that becomes, during this period, the electric charge that is provided to load with keep constant load voltage V
LOADElectric charge conform to.Because integrating condenser 46 receives the reflection of the electric current of inflow transistors 26, the reflection of the total electrical charge that its receiving crystal pipe 26 provided in its conduction time interim.Therefore, under limit, the electric charge that SC comparator 12 and 14 output voltage and per clock cycle are provided to load is proportional, thus with load current I
LOADProportional.This linearity is the advantage of the DC-DC transducer of configuration according to the present invention.Another advantage is, as the load voltage V of decay
LOADWith reference voltage V
REFWhen conforming to, SC comparator 12 and 14 output voltage are stable, because they comprise integration filter.Therefore, the DC-DC transducer is stabilized to well-defined load voltage V
LOAD, and with load current I
LOADIrrelevant.
For dynamic behaviour, load current I for example
LOADIncrease produce load voltage V
LOADInstantaneous minimizing, this increases the output voltage of SC comparator 12 and 14.Before switch 26 and 30 conversions, integrating condenser 46 is charged to higher voltage, causes higher electric current to be provided to load 40.Circuit is with constant load voltage V
LOADSettle out, but at higher output voltage place, and increased the conduction cycle of transistor 26 from SC comparator 12 and 14.Similarly, produce load voltage V
LOADThe load current I of instantaneous increase
LOADThe output voltage of SC comparator 12 and 14 is reduced.Before switch 26 and 30 conversions, integrating condenser 46 is charged to lower voltage, causes lower electric current to be provided to load 40.Circuit is with constant load voltage V
LOADSettle out, but at the lower output voltage place from SC comparator 12 and 14, and the conduction cycle of having reduced transistor 26.
Fig. 3 is according to the SC comparator 12 of the embodiment of the invention and 14 schematic diagram, and SC comparator 12 and 14 is configured to operate with the bias correcting pattern.Though SC comparator 12 and 14 preferably structurally is identical, their input terminal 12
1, 12
2, 14
1With 14
2By different reference symbol sign, because they are resolution elements of DC-DC transducer 10 shown in Figure 1.Shown in Fig. 3 is three terminal switch S 41, and it has one as input 12
2, 14
2Terminal, one be coupled to receive such as V
SSThe terminal of operating voltage source and the terminal of a terminal that is coupled to capacitor C41.The another terminal of capacitor C41 is coupled to the terminal of a terminal, two-terminal switch S 42 of capacitor CVL and the first terminal of three terminal switch S 43.The another terminal of capacitor CVL is coupled to receive operating voltage source, for example V
SSSecond terminal of three terminal switch S 43 is as the input separately 12 of SC comparator 12 and 14
1, 14
1, and the 3rd terminal of switch S 43 is coupled to the terminal of capacitor C42 and the first terminal of three terminal switch S 45.Second terminal of capacitor C42 is coupled to the reverse input G41 of trsanscondutor G41
I1A terminal with two-terminal switch S 44.Trsanscondutor G41 also has one to be coupled to receive operating voltage source V
SSNon-return input G41
I2, be coupled to receive such as V
SSThe output G41 of operating voltage source
O1, and the output G41 that is connected to the first terminal of second terminal of switch S 44 and three terminal switch S 46
O2The 3rd terminal of three terminal switch S 46 is coupled to the 3rd terminal of three terminal switch S 45 by capacitor C43.Second terminal of switch S 45 is coupled to second terminal of switch S 46 by capacitor C44.The common terminal that is connected of the 3rd terminal of capacitor C43 and switch S 46 is device 12 and 14 output as a comparison.Though element G41 shows and is described as trsanscondutor that this is not a restriction of the present invention.Trsanscondutor G41 can be inverter, comparator etc.Equally, switch S 41, S42, S43, S44, S45 and S46 can be mos field effect transistor (MOSFET), transmission gate etc.Each all has capacitor C44 to it should be noted that SC comparator 12 and SC comparator 14, and these capacitors are connected in parallel.Therefore, SC comparator 12 and SC comparator 14 are coupled by capacitor C44.In Fig. 1, represented this connection by interconnecting 17.
Fig. 4 is shown in Figure 3 being configured to the SC comparator 12 of aggressive mode operation and 14 schematic diagram.In other words, the circuit structure of Fig. 4 is identical with Fig. 3's, except switch S 41, S42, S43, S44, S45 and S46 in different positions.
The position of switch S 41, S42, S43, S44, S45 and S46 is set by the clock input signal CALA of SC comparator 12 and ACTA and by the clock input signal CALB and the ACTB of SC comparator 14.As an example, as clock input signal CALA during at logic high state, SC comparator 12 is with the operation of bias correcting pattern, and as clock input signal CALB during at logic high state, SC comparator 14 is operated with the bias correcting pattern.Similarly, as clock input signal ACTA during at logic high state, SC comparator 12 is with the aggressive mode operation, and as clock input signal ACTB during at logic high state, SC comparator 14 is operated with aggressive mode.
Refer again to Fig. 3, as clock input signal CALA during at logic high state, SC comparator 12 is with the operation of bias correcting pattern, and as clock input signal CALB during at logic high state, SC comparator 14 is operated with the bias correcting pattern.In this pattern, switch S 41 and S42 are arranged such that the terminal of capacitor C41 is coupled to receive operating voltage source, for example V
SSSwitch S 43 is arranged such that the terminal of capacitor C42 is connected to input 12
1, 14
1, and switch S 44 is arranged such that the another terminal of capacitor C42 is connected to the output G41 of trsanscondutor G41
O2Switch S 45 and S46 are arranged such that capacitor C43 and C44 parallel connection.In this configuration, switch S 41, S42 and S44 are set and think capacitor C41 and CVL discharge.In addition, the output G41 of capacitor C43 and trsanscondutor G41
O2Disconnect connection and in parallel with a pair of integrating condenser C44.It should be noted that the meaning representation of capacitor C44, because it relates to the capacitor 44 that appears in SC comparator 12 and 14 with plural number.Input coupling capacitor C42 is coupled to receive reference voltage V
REF, it is charged at reference voltage V
REFReverse input G41 with trsanscondutor G41
I1On voltage between difference, its output current is adjusted to zero.Electric charge among the capacitor C43 before being stored in the aggressive mode and the charge bonded that is stored among the capacitor C44.
As discussing hereinbefore, as clock input signal ACTA during at logic high state, SC comparator 12 is with the aggressive mode operation, and as clock input signal ACTB during at logic high state, SC comparator 14 is operated with aggressive mode.In this pattern, switch S 41, S42 and S45 are arranged such that the terminal of capacitor C41 is coupled to receive load voltage V
LOADAnd the another terminal of capacitor C41 is connected to capacitor CVL, C42 and C43.Switch S 46 is arranged such that the another terminal of capacitor C43 is connected to the output G41 of trsanscondutor G41
O2Switch S 44 is arranged such that capacitor C42 and output G41
O2Disconnect and connecting.In this pattern, keep equaling reference voltage V if be applied to the voltage of the first terminal of capacitor C42
REF, then the output current of trsanscondutor G41 remains on zero.According to law of conservation of charge, when:
V
LOAD＝(1+C
CVL/C
C41)＊V
REF EQT.1
The time, satisfy this condition.Wherein:
C
C41Equal the capacitance of capacitor C41; With
C
CVLEqual the capacitance of capacitor CVL.
If the output voltage of DC-DC transducer 10 is different from the EQT.1 specified value, then some electric charges will be transferred from capacitor C41 in each active cycle.If the mutual conductance coefficient of trsanscondutor G41 is enough, then this electric charge will be provided by feedback condenser C43, and the integrated value of setting up from former bias correcting pattern is changed its voltage.
Fig. 5 is configured to schematic diagram with the part 21 of the SC comparator 16 of migration pattern operation and selector circuit 20 according to embodiments of the invention.The migration pattern is also referred to as the error correction pattern.Shown in Fig. 5 is three terminal switch S 52, and it has and is coupled to receive input voltage V
INTThe first terminal, be coupled to receive such as V
SSThe operation potential source second terminal and be coupled to the 3rd terminal of the terminal of capacitor C51.The another terminal of capacitor C51 is coupled to the non-return input G51 of balance input trsanscondutor G51
I1The first terminal with two-terminal switch S 54.The another terminal of two-terminal switch S 54 is coupled to receive voltage source V
MINBalance input trsanscondutor G51 has reverse input G51
I2, it is coupled to the first terminal of three terminal switch S 53 and the first terminal of capacitor C52.Second terminal of three terminal switch S 53 is coupled to receive operating voltage source, for example V
SSThe 3rd terminal of three terminal switch S 53 is connected to the terminal of capacitor C53, and the another terminal of capacitor C53 is typically connected to second terminal of capacitor C52.Capacitor C52 and the terminal that C53 is connected jointly are connected to the 3rd terminal of three terminal switch S 51.The first terminal of three terminal switch S 51 is coupled to receive control voltage V
CTRL, and second terminal of three terminal switch S 51 is coupled to receive operating voltage source, for example V
SSSC comparator 16 comprises switch S 51, S52, S53 and S54, capacitor C51 and C52 and balance input trsanscondutor G51.Though element G51 shows and is described as trsanscondutor that this is not a restriction of the present invention.Trsanscondutor G51 can be inverter, comparator etc.Equally, switch S 51, S52, S53, S54 and S55 can be mos field effect transistor (MOSFET), transmission gate etc.
The part 21 that is presented at the selector circuit 20 among Fig. 5 is three terminal switch S 55, and it has the reverse input G51 of the balance of being connected to input trsanscondutor G51
I2The first terminal, second terminal of input 114 that is connected to two input NOT-AND gate U51 and the output G51 that is connected to balance input trsanscondutor G51
O2The 3rd terminal.The input 116 of two input NOT-AND gate U51 is coupled with receive clock signal CLK/2.Balance input trsanscondutor G51 is coupled in addition to receive such as V
SSOperating voltage source second output G51
O1
Fig. 6 is the schematic diagram that is configured to the part 21 of the SC comparator 16 of aggressive mode operation and selector circuit 20 shown in Figure 5.In other words, the circuit structure of Fig. 6 is identical with Fig. 5's, except switch S 51, S52, S53, S54 and S55 in different positions.
The position of switch S 51, S52, S53, S54 and S55 is set by clock input signal CALA and ACTA.Particularly, as clock input signal CALA during at logic high state, SC comparator 16 is with the operation of bias correcting pattern, and as clock input signal ACTA during at logic high state, SC comparator 16 is operated with aggressive mode.
In the bias correcting pattern, switch S 52 and S54 are arranged such that the terminal of capacitor C51 is coupled to receive operating voltage source V
SS, and input G51
I1Be coupled to receive voltage V
MINSwitch S 53 and S51 are arranged such that the terminal of capacitor C53 is coupled to receive operating voltage source, for example V
SsIn addition, the configuration of switch S 54 and S52 is coupled to operating voltage source V with the terminal of capacitor C51
SS, and the another terminal of capacitor C51 is coupled to voltage V
MINSwitch S 51 is configured to be connected the terminal of capacitor C52 to receive operating voltage source V with S55
SS, and with the another terminal of capacitor C52 and the input G51 of trsanscondutor G51
I2Be connected to output G51
O2Therefore trsanscondutor G51 is configured in the negative feedback structure.Because negative feedback structure and being coupled to receive voltage V
MINNon-return input G51
I1, oppositely import G51
I2Set up similar voltage.Preferably, voltage V
MINBe selected as a value in the opereating specification of trsanscondutor G51.Capacitor C51 is charged to voltage V
MINAnd capacitor C52 is charged to voltage V
MIN, voltage V
MINBy any offset voltage change of trsanscondutor G51.Capacitor C53 is discharged and the trsanscondutor outputting current steadily arrives zero.
In aggressive mode, the capacitor C53 that is discharged is connected in parallel on capacitor C52 two ends, so that the voltage that is stored in the combination is offset from initial voltage, such initial voltage makes the output signal of trsanscondutor G51 reduce to zero.This skew allows the filtering part of voltage comparator and SC comparator 12 not extend to zero output voltage range operation.Because the input 116 of two input NOT-AND gate U51 is coupled with receive clock signal CLK/2 (shown in Figure 1), to have only when clock signal CLK/2 is high, the output of two input NOT-AND gate U51 just responds the output of trsanscondutor G51.Integrating condenser 46 (shown in Figure 1) is discharged by transistor 32 at each transfer point of clock signal clk/2, so, the reflection electric current I that provides when voltage balancing circuit 24
IMAGE Capacitor 46 is charged to equals V approx
CTRLWhen deducting the voltage of offset voltage, two input NOT-AND gate U51 are transformed into the transfer point logic low voltage level afterwards of clock signal clk/2.Therefore, reflection electric current I
IMAGEBe used to produce internal reference signal V
INT
Though the appropriate section of SC comparator 18 and selector circuit 20 is not shown, it should be noted that the circuit arrangement of SC comparator 18 is identical with the part of Fig. 5 of expression SC comparator 16.Owing to increased the inverter that is coupling between input terminal 116 and clock signal clk/2, the part 21 that is coupled to the selector circuit 20 of SC comparator 18 is different from the part 21 of the selector circuit 20 that is coupled to SC comparator 16.Be further noted that for SC comparator 18, when clock input signal CALA is high, sets up the bias correcting pattern, and when clock input signal ACTA is high, set up aggressive mode.
With reference now to Fig. 7,, it illustrates the schematic diagram according to the voltage balancing circuit 24 of the embodiment of the invention.Voltage balancing circuit 24 comprises electronic circuit 70 and 72.Electronic circuit 70 comprises three three terminal switch S 61, S63 and S65, P passage FET M61, electric current receiver 161 and capacitor C61.Electronic circuit 72 comprises three three terminal switch S 62, S64 and S66, P passage FET M62, electric current receiver I62 and capacitor C62.Refer again to electronic circuit 70, three terminal switch S 61 have be connected to transistor 26 and 28 source electrode (transistor 26 with 28 be connected with reference to figure 1 be described) and receive input voltage V
BATTSecond terminal of the first terminal of first input end, the drain electrode that is connected to transistor 26 and switch S 62 and the 3rd terminal that is connected to the source electrode of P passage FET M61.The grid of P passage FET M61 is connected to the first terminal of three terminal switch S 65 and a terminal of capacitor 61, and the drain electrode of P passage FET M61 is connected to the 3rd terminal and the electric current receiver I61 of three terminal switch S 65.The another terminal of capacitor 61 is connected to the 3rd terminal of three terminal switch S 63.The first terminal of three terminal switch S 63 is connected to the source electrode of transistor 26 and 28 and receives voltage V
BATT, and second terminal of three terminal switch S 63 is connected to the drain electrode of P channel transistor 28, the source electrode of P passage FET M63 and the first terminal of switch 64.The drain coupled of P passage FET M63 is used the reflection electric current I to transducer 10
IMAGEPart, and the grid of P passage FETM63 is connected to second terminal of switch S 65 and S66.It should be noted that P passage FETM63 can be replaced by a plurality of P channel transistors, common connection of the grid of described a plurality of P channel transistors and source electrode thereof connect jointly, with the electric current I I that will video
MAGEThe fraction component that is divided into desired amt is used in the different piece of DC-DC transducer 10.
Three terminal switch S 62 have the drain electrode that is connected to transistor 26 the first terminal, be connected to the source electrode of transistor 26 and 28 and receive voltage V
BATTSecond terminal and the 3rd terminal that is connected to the source electrode of P passage FET M62.The grid of P passage FET M62 is connected to second terminal of three terminal switch S 66 and is coupled to the 3rd terminal of three terminal switch S 64 by capacitor C62, and the drain electrode of P passage FET M62 is connected to the 3rd terminal and the electric current receiver I62 of three terminal switch S 66.The first terminal of three terminal switch S 64 is connected to the source electrode of transistor 26 and 28 and receives voltage V
BATT, and second terminal of three terminal switch S 64 is connected to the drain electrode of P channel transistor 28, the source electrode of P passage FET M63 and second terminal of switch 63.
In operation, the electric current that voltage balancing circuit 24 will be derived from transistor 28 is sent to the other parts of DC-DC transducer 10, guarantees that simultaneously the drain-to-source voltage of transistor 28 conforms to the drain-to-source voltage of transistor 26. Electronic circuit 70 and 72 is with bias correcting and aggressive mode operation.When clock input signal CALA was high, a sub-circuit conversion was to the bias correcting pattern, and when clock input signal CALB was high, another electronic circuit was transformed into the bias correcting pattern.In aggressive mode, electronic circuit 70 and 72 parallel work-flows.
In the embodiment shown in fig. 7, electronic circuit 70 is configured to bias correcting pattern operation, reference sub-circuit 72, and capacitor C62 is charged to the needed grid of electric current that P passage FET M62 obtains to be received by electric current receiver I62 to source voltage.Foundation comprises the negative feedback loop of FET M61, switch S 61, S63 and S65 and capacitor C61, and it forces P passage FET M61 that the electric current that is received by electric current receiver I61 is provided.Capacitor C61 is charged to grid to source voltage, so that transistor M62 can provide electric current.This voltage remains in the aggressive mode, because the first terminal of capacitor C61 is connected to the grid of P passage FET M61, this does not provide conducting path.The voltage of drain electrode place of supposing transistor 26 and 28 is equal substantially, and P passage FET M62 will obtain electric current.The negative feedback loop that comprises FET M62 and M63, switch S 66 and S64 and capacitor C41 makes the grid voltage of P passage FET M63 be suitable for setting up this condition.Therefore, the current delivery that will be provided by transistor 28 as P passage FET M63 is during to the other parts of DC-DC transducer 10, and transistor 26 and 28 drain voltage keep equating.
Fig. 8 is the schematic diagram according to the DC-DC transducer 100 of the embodiment of the invention.Because increased at the current feedback circuit 102 of capacitor 46 two ends couplings and the zero crossing detector 104 that is coupled between the drain electrode of N passage FET 30 and source electrode, DC-DC transducer 100 is different from the DC-DC transducer 10 of Fig. 1.Current feedback circuit 102 has the input 106 that is connected to node 34, the source electrode that is connected to transistor 26 and 28 and voltage source V
BATTInput 108, the output 110 of a terminal that is connected to capacitor 46 and the output 112 of being coupled to the another terminal of capacitor 46.Therefore, output 110 is connected to the input of SC comparator 16 and 18.
Zero crossing detector 104 has the input of the drain electrode that is connected to N passage FET 30, the input of source electrode that is connected to N passage FET 30 and the output 116 that is connected to drive circuit 22.In addition, zero crossing detector 104 has the input that is coupled with receive clock input signal CALA and CALB.
In operation, when the current conversion by inductor 36 when flowing through transistor 30, drain-to-source voltage is initially negative.The current reversal of inductor 36 if flow through, then the drain-to-source voltage of transistor 30 is fallen zero and is just become.The drain-to-source voltage of zero crossing detector 104 monitoring transistors 30 also transfers signals to driver, and is with the voltage at the grid place of removing transistor 30, zero because its grid approaches to source voltage.Because in fact drain-to-source voltage be zero and very little ideally, so preferably have a low skew also can to work in any moment during the clock cycle to zero crossing detector 104.Because transistor 30 can be in all clock cycle conduction, two comparators are used, a rectification error during the strange clock cycle, a rectification error during the idol clock cycle.During not having the time interval of error correction, can comparator in parallel.Therefore, when input clock signal CALA was high, a comparator was disconnected and connects and rectification error, and when input clock signal CALB was high, another comparator was disconnected and connects and rectification error.The combination of two comparators is always in response to the drain-to-source voltage of transistor 30, because input clock signal CALA and CALB are non-overlapped and shorter than the clock cycle.
In addition, when the half of load voltage greater than cell voltage, DC-DC transducer 100 may become unstable owing to low load.By electric current being increased to electric current, can suppress this unsteadiness into integrating condenser 46 chargings.The electric current that increases can be provided by current feedback circuit 102.Specify additional electric current to be:
I＝((V
LOAD2)＊T)V
BATT＊M＊L) EQT.2
Wherein:
L equals the value (Henry) of inductor;
T is clock cycle (second); With
M is the electric current of inflow transistor 26 and the ratio of the electric current that charges for capacitor 46.
Fig. 9 is the schematic diagram according to the zero crossing detector 104 of the embodiment of the invention.Zero crossing detector 104 comprises the electronic circuit 104A in parallel with electronic circuit 104B.Electronic circuit 104A comprises three three terminal switch S 71A, S72A and S74A, single two-terminal switch S 73A and a plurality of capacitor C71A, C72A, C73A and C74A.Three terminal switch S 71A have the drain electrode of being coupled to transistor 30 the first terminal, be coupled to receive such as V
SSSecond terminal of operating voltage source and the 3rd terminal that is connected to the terminal of capacitor C71A.The connection that is shown to DRAIN30 among Fig. 9 shows the connection of terminal to the drain electrode of transistor 30.Three terminal switch S 72A have and are coupled to receive bias voltage V
BIASThe first terminal, be coupled to receive such as V
SSSecond terminal of operating voltage source and the 3rd terminal that is connected to the terminal of capacitor C72A.Second terminal of capacitor C72A is coupled to operating voltage source V by the parallel connection combination of two-terminal switch S 73A and capacitor C73A
SSSecond terminal of capacitor C72A also is coupled to second terminal of capacitor C71A by capacitor C74A.Two input trsanscondutor G71A have the input G71A of second terminal of second terminal that is connected to capacitor C71A and three-input switch S74A
I1, and be coupled to receive such as V
SSThe input G71A of operating voltage source
I2Second terminal of three terminal switch S 74A is connected to drive circuit 22 (shown in Figure 1), and the 3rd terminal of switch S 74A is connected to the output G71A of trsanscondutor G71A
O1, and the output G71A of trsanscondutor G71A
O2Be coupled to receive operating voltage source, for example V
SSThe connection to DRAIN22 that shows among Fig. 9 has shown the connection of second terminal of three terminal switch S 74A.
Electronic circuit 104B comprises three three terminal switch S 71B, S72B and S74B, single two-terminal switch S 73B and a plurality of capacitor C71B, C72B, C73B and C74B.Three terminal switch S 71B have the drain electrode of being coupled to transistor 30 the first terminal, be coupled to receive such as V
SSSecond terminal of operating voltage source and the 3rd terminal that is connected to the terminal of capacitor C71B.The connection to DRAIN30 that shows among Fig. 9 has shown the connection of terminal to the drain electrode of transistor 30.Three terminal switch S 72B have and are coupled to receive bias voltage V
BIASThe first terminal, be coupled to receive such as V
SSSecond terminal of operating voltage source and the 3rd terminal that is connected to the terminal of capacitor C72B.Second terminal of capacitor C72B is coupled to operating voltage source V by the parallel connection combination of two-terminal switch S 73B and capacitor C73B
SSSecond terminal of capacitor C72B also is coupled to second terminal of capacitor C71B by capacitor C74B.Two input trsanscondutor G71B have the input G71B of second terminal of second terminal that is connected to capacitor C71B and three-input switch S74B
I1, and be coupled to receive such as V
SSThe input G71B of operation potential source
I2Second terminal of three terminal switch S 74B is connected to drive circuit 22 (shown in Figure 1), and the 3rd terminal of switch S 74B is connected to the output G71B of trsanscondutor G71B
O1, and the output G71B of trsanscondutor G71B
O2Be coupled to receive operating voltage source, for example V
SSThe connection to DRAIN22 that shows among Fig. 9 has shown the connection of second terminal of three terminal switch S 74B.
In operation, when clock input signal CALA was high, electronic circuit 104A was transformed into the bias correcting pattern, and when clock input signal CALB was high, electronic circuit 104B was transformed into the bias correcting pattern.When not in the bias correcting pattern, electronic circuit 104A and 104B parallel work-flow, each electronic circuit is all in aggressive mode.In the bias correcting pattern, switch S 71A is configured to the first terminal of capacitor C71A is connected to operating voltage source V
SSSwitch S 72A and S73A are arranged such that the terminal of capacitor C72A is connected to identical operations voltage source, for example V
SSIn addition, switch S 73A is connected to the identical operations voltage source with the another terminal of capacitor C73A, and the terminal of its first terminal and capacitor C74A is connected to operating voltage source simultaneously, for example V
SSSwitch S 74A is configured to the lead-out terminal G71A with trsanscondutor G71A
O1Be connected to input terminal G71A
I1In this configuration, capacitor C71A and C74A are recharged and are coupling in the parallel-connection structure, make voltage that the output current of trsanscondutor G71A is adjusted to zero.Capacitor C72A and C73A are discharged.
In the aggressive mode operation of electronic circuit 104B, lead-out terminal G71B
O1Be connected to drive circuit 22, and the input terminal G71B of trsanscondutor G71B
I1Be coupled to the drain electrode of transistor 30 by capacitor C71B.Lead-out terminal G71B
O1The capacitor T network coupled of also passing through to be formed by capacitor C72B, C73B and C74B is to voltage V
BIASElectric charge is passed to capacitor C71B by this network, has increased at input terminal G71B
I1Voltage.Preferably, it is little that capacitor C72B compares with C73B with capacitor C71B with C74B, so that small voltage increment is at input terminal G71B
I1Produce.When big from the voltage of the drain electrode of transistor 30 and when negative, output voltage will be height, when input voltage still when negative, therefore this output voltage drops to zero.
Because electronic circuit 104A is identical with 104B and in parallel, zero crossing detector 204 operations, and be indifferent to one or two electronic circuit in aggressive mode.Therefore, arbitrary electronic circuit can be switched to the bias correcting pattern, and does not disturb the function of intact part.
It should be understood that the method that the DC-DC transducer is provided and has been used for compensating DC-DC transducer offset error till now.The DC-DC transducer comprises the inductor that is coupled with by a plurality of switches reception voltages.The control circuit of two circuit paths by having the parallel work-flow of being configured to is controlled described switch.This configuration provides duplicating of control circuit path so that at least one path always movable and in response to input signal.Comprise that two paths consider the migration of the system that will be applied to when lacking scale interval.The circuit paths cooperation provides the offset cancellation of error in the element of circuit paths.The present invention is suitable for being used for electric charge control model structure and current control mode structure.
Though disclosed herein is some preferred embodiment and method, obviously for a person skilled in the art,, such embodiment and method can be changed and revise, and do not depart from the spirit and scope of the invention according to the foregoing disclose content.This means that the present invention should only be limited to claims and the article of suitable law and the degree of principles and requirements.
Claims (10)
1. method is used for compensating the error of DC-DC transducer, comprising:
First signal path with at least one circuit element is provided;
Secondary signal with at least one circuit element path is provided; With
With described first or one of secondary signal path be transformed into the error correction pattern, with the error of at least one circuit element described in described first or the secondary signal path of compensation in described error correction pattern, wherein said first or another signal path in secondary signal path in normal manipulation mode.
2. the method for claim 1, further be included in during the first of first clock cycle with described first or one of secondary signal path be transformed into described error correction pattern, and during the second portion of described first clock cycle with described first or one of secondary signal path be transformed into described normal mode.
3. method as claimed in claim 2, the described second portion of wherein said first clock cycle is the remainder of described first clock cycle, and wherein said with described first or one of the secondary signal path step that is transformed into described normal mode further be included in during the whole second clock cycle with described first or one of secondary signal path be transformed into described normal mode; And further be included in during the described second clock cycle from described first or described at least one element in secondary signal path select output signal.
4. the method for claim 1 further comprises:
The signal integration that will obtain from input signal to described first signal path to produce the first integral signal;
The signal integration that will obtain from input signal to described secondary signal path to produce the second integral signal;
Produce the first and second comparator output signal components from described first and second integrated signals;
Produce the first control path signal by more described first comparator output signal and electric charge index signal, described electric charge index signal indication is provided to the electric charge of load during the concurrent clock cycle;
Produce the second control path signal by more described second comparator output signal and described electric charge index signal, described electric charge index signal indication is provided to the described electric charge of load during the described concurrent clock cycle; And
Use the described first and second control path signals to produce the output voltage that interrelates with a plurality of switches.
5. method as claimed in claim 4 further comprises:
The place that begins in each clock cycle is the discharge of the first store energy element;
With first electric current is described first store energy element charging, wherein said first electric current is proportional with second electric current of the second store energy element of flowing through, and wherein said electric charge index signal is the voltage that forms at the described first store energy element two ends, and described electric charge index signal indication is provided to the described electric charge of load during the described concurrent clock cycle; And further comprise
The 3rd electric current is provided, and described the 3rd electric current merges and the proportional electric current of described second electric current, and wherein said the 3rd electric current suppresses the formation of oscillation mode.
6. method, the offset error that is used for correcting the DC-DC transducer comprises:
In response to reference signal and transducer output signal and produce first signal, described first signal comprises first subsignal and second subsignal;
In response to described reference signal and described transducer output signal and produce secondary signal, described secondary signal comprises the 3rd subsignal and the 4th subsignal;
During the period 1 of clock signal, correct first offset error in described first signal; With
Correct second offset error in the described secondary signal during the second round of described clock signal, described first and second cycles are the different cycles.
7. method as claimed in claim 6, the step of described first signal of wherein said generation comprises:
Decay is also filtered described reference signal and described transducer output signal;
The transducer output signal of the reference signal of more described decay and filtration and described decay and filtration is to produce described first subsignal, and the reference of wherein said more described decay and filtration comprises with the step of transducer output signal introduces into first subsignal with the first offset error correction signal;
More described first subsignal and internal reference voltage are to produce described second subsignal, and the step of wherein said more described first subsignal and described internal reference voltage comprises introduces into second subsignal with the second offset error correction signal;
Decay is also filtered described reference signal and described transducer output signal;
The transducer output signal of the reference signal of more described decay and filtration and described decay and filtration is to produce described the 3rd subsignal, and the reference of wherein said more described decay and filtration comprises with the step of transducer output signal introduces into the 3rd subsignal with the 3rd offset error correction signal; And
More described the 3rd subsignal and described internal reference voltage are to produce described the 4th subsignal, and the step of wherein said more described the 3rd subsignal and described internal reference voltage comprises introduces into the 4th subsignal with the 4th offset error correction signal.
8. method as claimed in claim 7 further comprises:
Select one of described first signal or described secondary signal to produce selected signal;
From described selected signal, produce driver signal;
Use described driver signal to produce the reflection electric current; With
Use described reflection electric current to produce described internal reference signal.
9. DC-DC transducer comprises:
Control circuit, it has a plurality of inputs and a plurality of output, and wherein said control circuit comprises:
First circuit paths, it has first and second input and outputs; With
The second circuit path, it has first and second input and outputs,
The wherein said first and second circuit paths cooperations provide the offset cancellation of the error in the element of described first and second circuit paths; And
Switching network, it is coupled to described control circuit.
10. DC-DC transducer as claimed in claim 9, wherein:
Described first circuit paths comprises first comparator, and described first comparator is in response to the part of load voltage and the difference between the reference voltage and produce output;
Described second circuit path comprises second comparator, and described second comparator is in response to the part of load voltage and the difference between the reference voltage and produce output;
Described first and second comparators comprise filter, and described filter is respectively applied for stablizes described first and second circuit paths; And
Described filter comprises integrator, and described integrator is used to provide described first and second circuit paths total output signal component.
Applications Claiming Priority (2)
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| US11/530,983 | 2006-09-12 | ||
| US11/530,983 US7439716B2 (en) | 2006-09-12 | 2006-09-12 | DC-DC converter and method |
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| CN101145729B CN101145729B (en) | 2011-08-31 |
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| US (1) | US7439716B2 (en) |
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| US6040686A (en) * | 1999-01-07 | 2000-03-21 | Linear Technology Corporation | Low noise step-down switching regulator circuits with programmable slew rate limiter and methods of use |
| US6813173B2 (en) * | 2000-10-26 | 2004-11-02 | 02Micro International Limited | DC-to-DC converter with improved transient response |
| JP2004173421A (en) * | 2002-11-20 | 2004-06-17 | Matsushita Electric Ind Co Ltd | Dc/dc converter |
| TW595076B (en) * | 2003-05-19 | 2004-06-21 | Richtek Technology Corp | Delta-sigma DC to DC converter and its method |
| KR100577325B1 (en) * | 2003-11-14 | 2006-05-10 | 마쯔시다덴기산교 가부시키가이샤 | Dc-dc converter |
| TWI301686B (en) * | 2004-08-30 | 2008-10-01 | Monolithic Power Systems Inc | Dc/dc switch mode voltage regulator, method implemented thereon and device for short circuit current ratcheting therein |
-
2006
- 2006-09-12 US US11/530,983 patent/US7439716B2/en active Active
-
2007
- 2007-08-27 TW TW096131699A patent/TWI406489B/en active
- 2007-09-11 CN CN2007101542089A patent/CN101145729B/en active Active
-
2008
- 2008-08-20 HK HK08109290.0A patent/HK1118133A1/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CN101145729B (en) | 2011-08-31 |
| US20080062733A1 (en) | 2008-03-13 |
| HK1118133A1 (en) | 2009-01-30 |
| TWI406489B (en) | 2013-08-21 |
| TW200818680A (en) | 2008-04-16 |
| US7439716B2 (en) | 2008-10-21 |
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