CN101145400A

CN101145400A - Embedded memory SOC mapping realization method

Info

Publication number: CN101145400A
Application number: CNA2006100310821A
Authority: CN
Inventors: 陈恩林
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-09-13
Filing date: 2006-09-13
Publication date: 2008-03-19

Abstract

The invention discloses an implementation method of SOC bit map with a built-in storage, which introduces the bit map in a SOC chip with the built-in storage to realize the high-efficiency batch analysis of the SOC chip. The method is completed by the following steps: configuring a virtual two-dimensional storage array and simultaneously establishing the one-to-one correspondence relationship between the virtual two-dimensional storage array and the physical address of the built-in storage in the SOC chip; and displaying the address in correspondence to the serial output data in the relevant position on the virtual two-dimensional storage array.

Description

The SOC position mapping implementation method of embedded memory

Technical field

The present invention relates to a kind of mapping implementation method, relate in particular to a kind of position mapping implementation method that is embedded with the SOC of storer.

Background technology

For simple storer, as DRAM, SRAM, FLASH etc., because it has address wire and parallel data line, therefore on general engineering analysis test platform, can both realize the function of position mapping (BITMAP) basically, and its mapping can be with the test data of each storage unit in the mode display chip of figure, and form certain failure mode according to the physical arrangement of chip, it has following advantage:

(1) graphical data, directly perceived;

(2) failure mode relative fixed relatively is beneficial to statistical study;

(3) in case exploitation is provided with success, the most of test automatically by the ATE platform finished in the application process, can satisfy large batch of analyze demands.

Yet, for embedded memory (as Flash, EEPROM, SRAM etc.) SOC (System-on-Chip, SOC (system on a chip)), because it does not have address wire and parallel data line, therefore all be to use EMMI to do electrical analysis basically, and by the infrared and radium-shine inefficacy anchor point that obtains, but this method exists following several problem:

(1) data result of Shi Xiaoing is unfixing, can't do statistical study;

(2) success ratio of Fen Xiing is relatively low; (3) analytic process all is with manual mode basically, and is consuming time, can't satisfy the large batch of analyze demands of foundries.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of SOC position mapping implementation method of embedded memory, analytical approach at the position mapping of simple storer can be incorporated in the test of SOC of embedded memory, to realize to SOC chip high-level efficiency, large batch of analytical approach.

For solving the problems of the technologies described above, the method for the invention may further comprise the steps:

(1) structure one virtual two-dimensional storage array, and realize reflecting one by one and should concern between the physical address of internal memory in this virtual two-dimensional array and the SOC chip;

(2) the corresponding addressing of the data of serial output is shown on the described virtual two-dimensional storage array relevant position.

The row address of described virtual two-dimensional memory array and column address are that capacity and the physical layout according to internal memory in the SOC chip distributes.

Described reflecting one by one should concern it is address decoder according in the SOC chip, sets up then that the address correspondence rule realizes.

Step (2) is to realize according to the address corresponding relation between the demoder of address counter and described internal memory.

The present invention has adopted technique scheme, has following beneficial effect, and promptly by having introduced the analytical approach of position mapping in being embedded with the SOC chip of storer, thereby the mode with figure of having realized shows the storage data of embedded memory, and is relatively more directly perceived; The positional alignment of disabling unit forms relatively-stationary pattern, helps doing the statistical study of inefficacy; Solve too much operation manually in the EMMI analysis, can satisfy the demand that the foundries typical products in mass production is analyzed.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Accompanying drawing is a schematic diagram of realizing the position mapping of internal memory among the SOC according to the present invention.

Embodiment

As shown in drawings, the schematic diagram for realizing that according to the present invention the position of internal memory is shone upon among the SOC.

At first, capacity and physical layout according to storer embedded among the SOC, on ATE (ATE (automatic test equipment)) test platform, distribute virtual row address and column address, construct a virtual two-dimensional storage array, then according to address decoder, on ATE, set up the address correspondence rule, the mapping relations one by one between the physical address of realization virtual two-dimensional array and internal memory.In one embodiment, for a storer that has 1M Bit, just need to distribute 20 virtual address wire A0～A19, but virtual address is a logical address, corresponding one by one with the actual physical address of storer but be not equal fully, that is to say that (A0～A19=0) is not corresponding the grade with physical column (PY) with physical line (PX) and 0 address to logical address 0, but must there be a physical address corresponding with it, such as maximum address (PX=MAX, PY=MAX), this is because there is the reason of demoder in the SOC chip internal.Realize logical address and the counter one to one algorithm of decoding of chip physical address so in the ATE system, will set up one, Here it is by automatic APG (the Algorithmic PatternGenerator that produces of ATE, the logical schema generator) address (X, Y) and the corresponding relation between logical address A0～A19.Still be example with top example, if want last data is write in last address of chip physical address, then allow X, the address of the maximum of Y is corresponding to the start address of A0～A19, when last data (with X, the data of the maximum address coupling of Y) give chip before through anti-decoding algorithm, these data are just mated the start address of having given logic, and chip just has been written to last address of physics through demoder after receiving these data.

Because, the SOC product of embedded memory generally triggers inner address counter by clock signal and realizes addressing, therefore, then on the ATE test platform, according to the address corresponding relation between the demoder of address counter and embedded memory, the corresponding addressing of the data of serial output is shown on the relevant position of virtual two-dimensional storage array, thereby realizes the function that the position is shone upon.For example, 8 continuous data have been read from chip, the a certain according to this rule match of this 8 number to be given 8 logical addresses with the decision of logical address line earlier by virtual address A2A1A0, suppose order to increase progressively, the demonstration physical address of position mapping and the relation of logical address are the orders of successively decreasing, also be the logic lowest address corresponding with the physics maximum address, so in the final mapping on the throne of these 8 data with last data topmost, first data show at nethermost physical location.

Claims

1. mapping implementation method in the SOC position of an embedded memory is characterized in that, comprising:

2. mapping implementation method in the SOC position of embedded memory according to claim 1 is characterized in that, the row address of described virtual two-dimensional memory array and column address are that capacity and the physical layout according to internal memory in the SOC chip distributes.

3. mapping implementation method in the SOC position of embedded memory according to claim 1 is characterized in that, described reflecting one by one should concern it is address decoder according in the SOC chip, sets up then that the address correspondence rule realizes.

4. mapping implementation method in the SOC position of embedded memory according to claim 1 is characterized in that step (2) is to realize according to the address corresponding relation between the demoder of address counter and described internal memory.

5. according to the SOC position mapping implementation method of each described embedded memory in the claim 1 to 4, it is characterized in that described method is finished on the ATE test platform.