CN101145393A - EEPROM erasing and writing high voltage conversion control cache suitable for low voltage data writing - Google Patents

Abstract

The present invention provides an EEPROM erasing high-voltage conversion control buffer applicable to low-voltage data writing. The buffer comprises a MaskBuf module, a DataBuf module and a data writing-in control logical module. The true value end and the complementary value end of a SRAM memory are respectively connected with an earthed NMOS pipe; SET and RESET signals are respectively used to control NMOS pipe gates and write data into the SRAM memory. When the turn threshold of the SRAM memory is in proximity of 1/2VDD, the data which is written in has properties including stability, reliability, etc. In the process of the internal EEPROM erasion, the buffer outputs high-voltage control signals following the lifting conversion of the output high voltage of the EEPROM charge pump, and a data writing control logic is realized with a transmission gate (low-voltage pipe) logic. So with simple circuits and compact structure, the buffer optimizes the chip area to the largest extent and realizes the aim of the present invention.

Description

Be applicable to the erasable high pressure conversion and control of the EEPROM buffer that the low-voltage data write

Technical field

The present invention relates to the erasable high pressure conversion and control of a kind of EEPROM buffer, the particularly a kind of erasable high pressure conversion and control of EEPROM buffer that is applicable to that the low-voltage data write.

Background technology

Along with the development of technology and widening of application, the requirement of working under the low-voltage of sorts of systems to chip is also more and more higher.The eeprom memory chip is because in many low voltage application field widespread uses, therefore the operating voltage that reduces the eeprom memory chip becomes a current big problem of needing solution badly, and is applicable to that the erasable high pressure conversion and control of the EEPROM buffer (hereinafter to be referred as buffer) that the low-voltage data write is to realize one of reliable and stable key in application factor of low-voltage EEPROM.

The main effect of EEPROM buffer is: after will treating that write data writes this buffer memory block, in the inner erasable process of EEPROM, buffer is followed the lifting conversion output high voltage control signal of EEPROM charge pump output high-pressure, with the data that are pre-stored in the buffer memory block is the EEPROM storage unit that unit writes certain selected page address with one page, realizes that the page or leaf of EEPROM is write function; Can make EEPROM realize the one-time write of the whole page data of 1 byte to 1 by buffer.

The capacity of EEPROM buffer is identical with the byte number of each page of EEPROM, and for example each page of EEPROM physical store capacity is 32 bytes, and capacity register also is 32 bytes (referring to 32 * 1Bytes PageBuf among Fig. 1).The EEPROM buffer is basic storage cell with byte, and the EEPROM buffer of 1 byte is made up of 1 MaskBuf and 8 DataBuf, and wherein MaskBuf controls the wiping high pressure of EEPROM, and DataBuf controls the high pressure of writing of EEPROM.If write " 1 ", then in the erasable process of EEPROM, can control wiping respectively, write high pressure output among MaskBuf and the DataBuf; If write " 0 ", then do not export wiping, write high pressure.The control gate of 1 corresponding 1 byte EEPROM unit of MaskBuf output control, the bit line of 8 corresponding 8 EEPROM of DataBuf output control.

As shown in Figure 2, existing EEPROM buffer adopts the single-ended buffer that writes usually, and wherein the MaskBuf of EEPROM buffer is identical with the DataBuf structure.In the erasable process of EEPROM, MaskBuf and DataBuf must bear high pressure, so all metal-oxide-semiconductors must use high-voltage tube in MaskBuf and the DataBuf circuit.After the erasable startup of EEPROM, VPP rises to high pressure, and VPP is a supply voltage during other states; The SRAM storer 5 of 4 tubular constructions is used to store data, and wherein Mp1, Mp2 are the high voltage PMOS pipe, and Mn1, Mn2 are the high pressure NMOS pipe, and high pressure NMOS pipe Mn3 is the zero clearing pipe; High pressure NMOS pipe Mn4 enables pipe for writing SRAM storer 5; High pressure NMOS pipe Mn5 is for wiping (writing) high voltage control pipe; Data write control 8 and comprise impact damper 6 and DataPath 7, the effect of impact damper 6 is to make to treat that write data has certain driving force, DataPath 7 comprises the transmission gate logic of decoded signal control for data write path, is used for control and selects target buffer to be written unit; Treat that write data writes before the buffer, the CLR signal is effective, with node 2 zero clearings; When writing buffer, write enable signal WRRAM signal for high, the Mn4 conducting, treat write data DATA behind impact damper 6, output has the data of driving force, imports from node 4 (node 4 writes and wipe, writes the public cabling of high-pressure passage for data) again, behind the Mn4 pipe, arrive node 2, if node 2 writes " 0 ", then node 2 is kept " 0 " state; If node 2 writes " 1 ", then between Mn4, Mn2 and GND, form current return, make node 2 be raised on the turn threshold of SRAM storer 5, change node 2 states into " 1 ", node 1 state changes " 0 " into.After write data was finished, the WRRAM invalidating signal started erasablely afterwards, and vpp voltage rises to the high pressure about 15V gradually, and node 2 is also lifted to 15V, and the high pressure of Mn5 pipe transmission node 3 is wiped, write the EEPROM storage unit to node 4.

For guaranteeing the reliability and stability of SRAM storer 5, the turn threshold of SRAM storer 5 all is made as 1/2Vdd usually; This buffer structure is under high voltage, and during as 1.8V, if node 2 is rewritten as " 1 ", then there is big problem in comparable data that write more smoothly, but under low voltage:

1) Mn4 pipe is the high pressure NMOS pipe, and as WRRAM when being high, the voltage that can transmit is Vdd-Vt, the Vt of high-voltage tube Mn4 pipe is usually about 0.8V, under the prerequisite of the inclined to one side effect of lining of not considering the Mn4 pipe, when 1.8V, the voltage that node 4 high thresholds transfer to node 2 is about 1V.

2) when node 2 writes " 1 ", the current return that forms between Mn4, Mn2 and the GND is inevitable to form pressure drop on the Mn4 pipe, cause node 2 further to reduce; Therefore when node 2 write " 1 ", the voltage on the node 2 almost turnover voltage with SRAM storer 5 was identical, thereby causes may writing one state hardly at node 2 under the low pressure situation.

For solving the problem that when the low-voltage single-ended EEPROM buffer that writes can't accurately writing data, its solution is to reduce Mn2 pipe size as far as possible, increase Mn1 pipe size, make the turn threshold of the SRAM storer 5 that writes from node 2 be reduced under the 1/2Vdd; After Mn2 pipe size reduces, electric current when node 2 writes " 1 " on Mn4, Mn2 and the GND reduces, increase the driving force of node 4 simultaneously, and (or the Mn4 pipe adopts low threshold value high pressure NMOS pipe design to increase Mn4 pipe size, but it is higher to technological requirement, have that reliability is uncertain, the more high shortcoming of technology cost), make that the pressure drop on the Mn4 pipe reduces; According to the degree of adjusting, the general single-ended minimum operating voltage of EEPROM buffer that writes can be reduced to about 1.5V.

But still there is big defective in above-mentioned solution, feedback as the Mp1 in the SRAM storer 5, Mp2, Mn1 and Mn2 pipe is extremely asymmetric, turn threshold is lower, very easily is subjected to the parasitic effects of laying out pattern cabling and wire capacitances, has the problem that is subjected to the correct write state of coupling change between line easily; But simultaneously owing to making accurately writing data under low-voltage, Mn3 pipe size must transfer to enough little, electric current when the turn threshold of reduction SRAM storer 5 and node 2 write " 1 ", and Mn4 pipe size also must be enough big, the pressure drop when writing " 1 " to reduce node 2 on the Mn4 pipe; Therefore, will cause MaskBuf and DataBuf chip area bigger, be unfavorable for chip cost control.

At the problems referred to above, need a kind of EEPROM buffer structure that is applicable to low voltage operating, stability and safety especially, this EEPROM buffer size is less simultaneously, helps the optimization of chip area more, reduces chip cost.

Summary of the invention

The purpose of this invention is to provide a kind of erasable high pressure conversion and control of EEPROM buffer that is applicable to that the low-voltage data write, simple in structure, reliable operation, technology easily realize, have the optimal layout area.

Technical matters solved by the invention can realize by the following technical solutions:

A kind of erasable high pressure conversion and control of EEPROM buffer that is applicable to that the low-voltage data write, it comprises the MaskBuf module, DataBuf module and data write control logic module, it is characterized in that, the true value of the SRAM storer in described MaskBuf module and DataBuf module and complementary end are respectively equipped with NMOS pipe over the ground, writing control logic module by described data controls the NMOS pipe, data are write MaskBuf module and DataBuf module, in the inner erasable process of EEPROM, buffer is followed the lifting conversion output of EEPROM charge pump output high-pressure and is wiped, write high voltage control signal.

Described MaskBuf module is made up of SRAM storer, zero clearing pipe, SET pipe and a wiping high voltage control pipe.

Described DataBuf module is write the high voltage control pipe by SRAM storer, zero clearing pipe, SET pipe, RESET pipe and one and is formed.

The turn threshold of described SRAM storer is in 1/2VDD.

Described data write control logic module by enable signal, address signal and treat that write data controls jointly, by forming jointly with non-or non-and transmission gate logic.

Described data write control logic module and adopt the grid of complementary pull-down pattern by the described SET pipe of signal controlling, RESET pipe, and load is extremely light; The SRAM memory data writes does not have the loss of transmission threshold value.

SET pipe in the described DataBuf module and RESET pipe driving force are greater than 2 PMOS pipes in the described SRAM storer.

After writing " 1 " data in the erasable high pressure conversion and control of the described EEPROM buffer, when the SRAM memory power rises to high pressure (about the 15V) state of EEPROM when erasable, the SRAM storer writes an end of " 1 " also can follow rising, and voltage is identical with its voltage, and the SRAM storer writes a terminal voltage of " 0 " and keeps 0V.

Wiping, writing in the process, if write " 1 " data in the erasable high pressure conversion and control of the EEPROM buffer, then can transmit and wipe or write control gate or the BitLine end of high pressure,, then can't transmit and wipe or write high pressure if write " 0 " data in the cache circuit to the EEPROM storage unit.

Described data write control logic module and produce needed SET, RESET control signal in described MaskBuf module and the DataBuf module, and SET pipe and RESET that signal is transferred to respectively in described MaskBuf module and the DataBuf module manage.

Described data write and comprise in the control logic module that serial data writes steering logic and parallel data writes steering logic.

The erasable high pressure conversion and control of the EEPROM buffer that is applicable to that the low-voltage data write of the present invention, connect a NMOS pipe over the ground respectively by true value and complementary two ends at the SRAM storer, utilize SET and RESET signal respectively to these two NMOS tube grid controls, data are write in the SRAM storer, the turn threshold of SRAM storer is near the 1/2VDD, the data that write have characteristics such as stable and reliable, in the inner erasable process of EEPROM, buffer is followed the lifting conversion output high voltage control signal of EEPROM charge pump output high-pressure, data write steering logic and adopt transmission gate (low-voltage tube) logic realization, circuit is simple, structure is simplified, can optimize chip area to the full extent, realize purpose of the present invention.

Description of drawings

Fig. 1 is the EEPROM physical arrangement block diagram that existing 32 byte pages are write;

Fig. 2 is the circuit theory diagrams of the existing single-ended EEPROM buffer that writes;

Fig. 3 is the circuit theory diagrams of the DataBuf circuit of EEPROM buffer of the present invention;

Fig. 4 is the circuit theory diagrams of the MaskBuf circuit of EEPROM buffer of the present invention;

Fig. 5 is that 1 byte data serial of the present invention writes control logic circuit figure;

Fig. 6 is that 1 byte data of the present invention is written in parallel to control logic circuit figure.

Embodiment

For technological means, creation characteristic that the present invention is realized, reach purpose and effect is easy to understand, below in conjunction with concrete diagram, further set forth the present invention.

A kind of erasable high pressure conversion and control of EEPROM buffer that is applicable to that the low-voltage data write, it comprises that MaskBuf module, DataBuf module and data write control logic module.

As shown in Figure 3, described DataBuf module is made up of SRAM storer 5 ', zero clearing pipe Mn3, SET pipe Mn5, RESET pipe Mn4 and a wiping high voltage control pipe Mn6.

4 tubular constructions that described SRAM storer 5 ' is made up of high voltage PMOS pipe Mp1, Mp2 and high pressure NMOS pipe Mn1, Mn2; The drain electrode of SET pipe Mn5 is connected with the node 1 ' of described SRAM storer 5 ', and its source electrode is connected ground connection then with the source electrode of high pressure NMOS pipe Mn1, and its grid connects the SET signal; The drain electrode of RESET pipe Mn4 is connected with the node 2 ' of described SRAM storer 5 ', and its source electrode is connected ground connection then with the source electrode of high pressure NMOS pipe Mn2, and its grid connects the RESET signal; The node 2 ' of described SRAM storer 5 ' is connected with the drain electrode of zero clearing pipe Mn3, and its source electrode is connected with its substrate lead and ground connection GND, and its grid connects the CLR signal; The node 2 ' of described SRAM storer 5 ' is connected with the grid of writing high voltage control pipe Mn6, its substrate lead ground connection GND.

Node 1 ' and node 2 ' at described SRAM storer 5 ' locate to increase respectively high pressure NMOS pipe Mn5 and Mn4 pipe, Mn5 and Mn4 are respectively by SET and REST signal controlling, SET is opposite with the REST signal phase, treat that write data produces SET and RESET signal through decoding logic, after buffer was by the zero clearing of CLR signal, node 2 ' was that " 0 ", node 1 ' are " 1 "; When SET end when high, RESET be " 0 ", Mn5 pipe conducting this moment, the Mn4 pipe ends, node 1 ' is pulled down to " 0 ", node 2 ' is an one state by " 0 " upset, " 1 " data are correctly write; If thinking to change once more " 1 " of node 2 ' be " 0 ", only a need RESET signal be " 1 ", and the SET signal is that " 0 " gets final product; After write data is finished, the WRRAM invalidating signal (is not pointed out among the figure, please replenish), start erasable afterwards, the vpp voltage of SRAM storer 5 ' rises to the high pressure about 15V gradually, node 2 ' is also lifted to 15V, and the high pressure of Mn6 pipe transmission node 3 ' carries out write operation to node 4 ' to the EEPROM storage unit.

The erasable high pressure conversion and control of this EEPROM buffer is the both-end write structure, therefore the turn threshold of SRAM storer 5 ' can be made as 1/2Vdd, two groups of complete symmetrical balances of phase inverter size of intersection feedback have very strong antijamming capability, have solved single-ended write structure and have fed back unbalanced problem; Simultaneously, SRAM storer 5 ' can design according to the minimum feature size of technology, improves the utilization factor of chip area.

As shown in Figure 4, described MaskBuf module is by SRAM storer 5 ", zero clearing pipe Mn3, SET pipe Mn4 and one wipes high voltage control pipe Mn6 and forms.

Described SRAM storer 5 " 4 tubular constructions formed by high voltage PMOS pipe Mp1, Mp2 and high pressure NMOS pipe Mn1, Mn2; The drain electrode and described SRAM storer 5 of SET pipe Mn5 " node 1 " be connected, its source electrode is connected ground connection then with the source electrode of high pressure NMOS pipe Mn1, its grid connects the SET signal; The drain electrode of zero clearing pipe Mn3 and described SRAM storer 5 " node 2 " be connected, its source electrode is connected ground connection then with the source electrode of high pressure NMOS pipe Mn2, its grid connects the CLR signal; Described SRAM storer 5 " node 2 " be connected its substrate lead ground connection GND with the grid of wiping high voltage control pipe Mn6.

Because EEPROM writes the specific (special) requirements of buffer, in case after data were write MaskBuf, data just can not be changed among the MaskBuf, have only the CLR signal effectively after, just can be with the data dump that writes.Therefore there is no the NMOS pipe of RESET control, other devices and DataBuf are identical.Write before the MaskBuf buffer, the CLR signal earlier effectively, to node 2 " zero clearing, the SET end when high, Mn4 pipe conducting this moment, node 1 " be pulled down to " 0 ", node 2 " be one state by " 0 " upset, " 1 " data are correctly write; After write data was finished, the WRRAM invalidating signal started erasable afterwards, SRAM storer 5 " vpp voltage rise to high pressure about 15V gradually; node 2 " also be raised to 15V, Mn6 manages transmission node 3 " high pressure to node 4 ", the EEPROM storage unit is wiped operation.

Zero clearing pipe Mn3 and wiping in described DataBuf module and the MaskBuf module, to write high voltage control pipe Mn6 identical with the cache circuit of single-ended write structure.

As shown in Figure 5, described data write control logic module and are selected signal X_SEL, address signal and treat that write data controls jointly to decoding by buffer enable signal WRRAM, row, by forming jointly with non-or non-and transmission gate logic.

Described data write control logic module and produce the SET signal of 1 bit MaskBuf module and the SET＜7:0 of 8 bit DataBuf modules〉and RESET＜7:0 signal.Write and make buffer enable signal WRRAM and row select signal X_SEL (X_SEL is that byte decoding is selected) by Sheffer stroke gate 6 to decoding " after ' produce 1 byte buffer write enable signal WR_1BYTE; WR_1BYTE is through phase inverter 3 " ', export the SET signal of MaskBuf module; WR_1BYTE with Through rejection gate 4 " ' and 5 " ' back output DataBuf module write enable signal WR_1BIT＜7:0, by treat write data DATA,

Common control transmission gate logic 7 " ', 9 " ' and 8 " ', 10 " ', wherein DATA with

Anti-phase each other relation.(the data of BIT1 to BIT6 not being write steering logic among Fig. 5 draws)

The data of MaskBuf and DataBuf write control:

For the MaskBuf module, as long as X_SEL and WRRAM signal are effective, the SET signal is effective, can write " 1 " data to the MaskBuf module; And the DataBuf module, then relative complex is a little.8 bit DataBuf modules are repetitive in 1 byte, write (being written as example with lowest order among the 1 byte DataBuf) with the DataBuf module data:

If enable signal WR 1BIT＜0 is write in the position of DataBuf module〉invalid (low level " 0 "), no matter then DATA or DATA state are how, SET＜0〉and RESET＜0 signal is 0, can't write data.

When enable signal WR_1BIT＜0 is write in the position of DataBuf module〉effectively (high level " 1 "), write " 0 " process: DATA end and be " 0 ", then Mp0 ' conducting, Mn0 ' ends, Mp0 ' transfers to RESET end with the WR_1BIT high level, and RESET export high level signal, makes that Mn3 manages conducting among Fig. 3, node 2 ' is pulled down to " 0 ", writes " 0 " data;

Anti-phase with DATA, be high level, Mp0 ends, the Mn0 conducting, SET end by drop-down be 0, can Mn4 pipe among Fig. 3 is not drop-down.

One writing process: DATA end is " 1 ", and then Mp0 ' ends, Mn0 ' conducting, the RESET end by drop-down be 0;

End is for " 0 ", and Mn0 ends, and the Mp0 conducting transfers to the SET end with the WR1_1BIT high level, and SET export high level signal, makes Mn5 conducting among Fig. 3 node 1 ' to be pulled down to " 0 ", and node 2 ' upset is " 1 ", writes " 1 " data.

Select signal X_SEL and write under the effective situation of buffer enable signal WRRAM in byte, as long as make BIT_SEL＜7:0 successively〉effective successively, promptly serializable with data to the target buffer address.

As shown in Figure 5, because data write control logic module and write the data that adopt complementary pull-down pattern to change node 1 ', node 2 ', the load of MaskBuf module write data control signal SET and DataBuf module write data control signal SET, RESET end is respectively among Fig. 4 the grid of Mn3, Mn4 among the Mn4 and Fig. 5, load is extremely light, driving force to SET, RESET signal requires extremely low, when therefore writing data, almost need not to consider the data output end load capacity.And because Mn4 and Mn5 pipe are the NMOS pipe, do not have threshold value loss problem when drop-down, its driving force only needs to get final product greatly than Mp1, Mp2.

Steering logic all can adopt minimum dimension design among Fig. 5, to realize the optimal layout area.

Write in serial on the basis of steering logic, remove BIT_SEL＜7:0〉after the control signal, and with data-in port by 1 expand to 8 be after, can be changed to Fig. 6 and be written in parallel to steering logic, WRRAM and X_SEL effectively after, but one-time write 1 byte data, the circuit control principle is identical with the serial writing mode.

Among the present invention, in the described DataBuf module, all pipes all adopt high-voltage MOS pipe to realize, technology minimum feature size according to high tension apparatus, the W/L that determines Mp1 and Mp2 gets 1.9u/1.2u, the W/L of Mn1 and Mn2 gets 0.7u/1.2u, and the W/L of Mn3, Mn4, Mn5 gets 1.9u/1.2u, and the W/L of Mn6 gets 2u/1.2u.

In the described MaskBuf module, all pipes all adopt high-voltage MOS pipe to realize, according to the technology minimum feature size of high tension apparatus, the W/L that determines Mp1 and Mp2 gets 1.9u/1.2u, the W/L of Mn1 and Mn2 gets 0.7u/1.2u, and the W/L of Mn3, Mn4 gets 1.9u/1.2u, and the W/L of Mn6 gets 2u/1.2u.

Described data write in the control logic module, and all pipes all adopt the low pressure metal-oxide-semiconductor to realize that the equal adopting process minimum feature size of the W of PMOS and NMOS pipe and L designs, and the W/L of PMOS and NMOS pipe all gets 0.8u/0.35u

Buffer side circuit test shows in the present embodiment: under required condition of work (temperature, voltage), the about 1V of minimum write data operating voltage of buffer, and can stablize and be converted to charge pump output high-pressure.Adopt the batch process test and the fail-test result of the eeprom chip of this structure buffer to show that the processing compatibility of this structure is good, yield rate is high, reliability performance is good.

More than show and described ultimate principle of the present invention and principal character and advantage of the present invention.The technician of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the instructions just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications; these changes and improvements all fall in the claimed scope of the invention, and the claimed scope of the present invention is defined by appending claims and equivalent thereof.

Claims (11)

1. the erasable high pressure conversion and control of EEPROM buffer that is applicable to that the low-voltage data write, it comprises the MaskBuf module, DataBuf module and data write control logic module, it is characterized in that, the true value of the SRAM storer in described MaskBuf module and DataBuf module and complementary end are respectively equipped with NMOS pipe over the ground, writing control logic module by described data controls the NMOS pipe, data are write MaskBuf module and DataBuf module, in the inner erasable process of EEPROM, buffer is followed the lifting conversion output of EEPROM charge pump output high-pressure and is wiped, write high voltage control signal.

2. the erasable high pressure conversion and control of EEPROM as claimed in claim 1 buffer is characterized in that, described MaskBuf module is made up of SRAM storer, zero clearing pipe Mn3, SET pipe Mn5 and a wiping high voltage control pipe Mn6; 4 tubular constructions that described SRAM storer is made up of high voltage PMOS pipe Mp1, Mp2 and high pressure NMOS pipe Mn1, Mn2; The drain electrode of SET pipe Mn5 is connected with the true value end of described SRAM storer, and its source electrode is connected ground connection then with the source electrode of high pressure NMOS pipe Mn1, and its grid connects the SET signal; The drain electrode of zero clearing pipe Mn3 is connected with the complementary end of described SRAM storer, and its source electrode is connected ground connection then with the source electrode of high pressure NMOS pipe Mn2, and its grid connects the CLR signal; The complementary end of described SRAM storer is connected its substrate lead ground connection GND with the grid of wiping high voltage control pipe Mn6.

3. the erasable high pressure conversion and control of EEPROM as claimed in claim 1 buffer is characterized in that, described DataBuf module is write high voltage control pipe Mn6 by SRAM storer, zero clearing pipe Mn3, SET pipe Mn5, RESET pipe Mn4 and one and formed; 4 tubular constructions that described SRAM storer is made up of high voltage PMOS pipe Mp1, Mp2 and high pressure NMOS pipe Mn1, Mn2; The drain electrode of SET pipe Mn5 is connected with the true value end of described SRAM storer, and its source electrode is connected ground connection then with the source electrode of high pressure NMOS pipe Mn1, and its grid connects the SET signal; The drain electrode of RESET pipe Mn4 is connected with the complementary end of described SRAM storer, and its source electrode is connected ground connection then with the source electrode of high pressure NMOS pipe Mn2, and its grid connects the RESET signal; The complementary end of described SRAM storer is connected with the drain electrode of zero clearing pipe Mn3, and its source electrode is connected with its substrate lead and ground connection GND, and its grid connects the CLR signal; The complementary end of described SRAM storer is connected with the grid of writing high voltage control pipe Mn6, its substrate lead ground connection GND.

4. as claim 2 or the erasable high pressure conversion and control of 3 described EEPROM buffer, it is characterized in that the turn threshold of described SRAM storer is in 1/2VDD.

5. the erasable high pressure conversion and control of EEPROM as claimed in claim 1 buffer is characterized in that, described data write control logic module by enable signal, address signal and treat that write data controls jointly, by forming jointly with non-or non-and transmission gate logic.

6. the erasable high pressure conversion and control of EEPROM as claimed in claim 5 buffer is characterized in that, described data write control logic module and adopt the grid of complementary pull-down pattern by the described SET pipe of signal controlling, RESET pipe, and load is extremely light; The SRAM memory data writes does not have the loss of transmission threshold value.

7. the erasable high pressure conversion and control of EEPROM as claimed in claim 3 buffer is characterized in that, SET pipe in the described DataBuf module and RESET pipe driving force are greater than 2 PMOS pipes in the described SRAM storer.

8. the erasable high pressure conversion and control of EEPROM as claimed in claim 1 buffer, it is characterized in that, after writing " 1 " data in the erasable high pressure conversion and control of the described EEPROM buffer, when the SRAM memory power rises to the high pressure conditions of EEPROM when erasable, the SRAM storer writes an end of " 1 " also can follow rising, and voltage is identical with its voltage, and the SRAM storer writes a terminal voltage of " 0 " and keeps 0V.

9. the erasable high pressure conversion and control of EEPROM as claimed in claim 1 buffer, it is characterized in that, the erasable high pressure conversion and control of described EEPROM buffer is being wiped, is being write in the process, if write " 1 " data in the erasable high pressure conversion and control of the EEPROM buffer, then can transmit and wipe or write control gate or the BitLine end of high pressure to the EEPROM storage unit, if write " 0 " data in the cache circuit, then can't transmit and wipe or write high pressure.

10. the erasable high pressure conversion and control of EEPROM as claimed in claim 5 buffer, it is characterized in that, described data write control logic module and produce needed SET, RESET control signal in described MaskBuf module and the DataBuf module, and SET pipe and RESET that signal is transferred to respectively in described MaskBuf module and the DataBuf module manage.

11. the erasable high pressure conversion and control of EEPROM as claimed in claim 5 buffer is characterized in that, described data write and comprise in the control logic module that serial data writes steering logic and parallel data writes steering logic.

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