CN101136854B - Method and apparatus for implementing data packet linear speed processing - Google Patents

Abstract

The method includes steps: based on certain scheduling strategy to dispatch the port in data stream input requests from current multiple ports to obtain response authority; executing first-in first-out buffering process for the input data packets in data stream at the port obtained response authority; analyzing frame head for data of packet head in data packet, looking up MAC address, and extracting tag of corresponding port ID; based on the tag to obtain the stream ID of the data packet, and modifying VLAN tag of data packet; carrying out early discarding data packets at random based on condition that data being not packet head in the input data packet of the data stream at the port occupy space of buffer memory; carrying out flux supervision treatment for data packets, and restricting speed of data stream input; based on the result to re-assemble and store the data. The invention raises performance for treating input data packets in linear speed, and meets requirement.

Description

A method and device for realizing line-speed processing of data packets

technical field

The invention relates to the field of Ethernet data transmission processing, in particular to a method and device for realizing line-speed processing of Ethernet data packets.

Background technique

In the field of Ethernet data transmission and processing, it is necessary to process and buffer the received data packets, and the strategy of processing first and then buffering tends to be adopted. Before data packet buffering, flow classification and admission control processing are mainly performed. When extracting data stream data packets from each port, if it is found to be packet header data, a copy will be sent to the flow classification unit through the control bus for corresponding processing. The stream ID result returned must be the first extracted packet header. After the flow classification unit receives the first byte data of the data packet, it first analyzes the frame header, then performs MAC address learning and search, performs label extraction based on the port ID, and finally performs flow binary tree search according to the flow label to obtain the flow ID of the data packet.

When receiving the end of the data stream data packet, it is necessary to perform an admission control operation according to the packet information (packet length, data stream ID) of the current data stream to realize traffic supervision. When doing admission control, the flow ID of the data flow must be known to make corresponding decisions such as rate limiting, random early discarding, and so on. Therefore, when the input control unit receives the packet header and it is a packet tail data flow, the admission control can only be performed after the flow classification obtains the corresponding data packet flow classification information. When the data packet needs to be transmitted in batches, at the end of the data packet, the admission control will be performed according to the relevant information of the data flow, that is, the aforementioned data flow ID and packet length information.

Therefore, when the data packet is processed first and then cached, it is necessary to search for the flow classification of the data packet before storing the data packet, and to implement traffic supervision according to the admission control of the flow. Moreover, for the same data packet, the two-step processing is performed in a serial manner. The flow classification processing obtains the flow ID corresponding to the data packet, and the admission control is based on the flow. The timing will depend on the timing of traffic classification and admission control. Especially in the case of multi-port, high-bandwidth wire-speed data stream input, although independent processing flows can be enabled for different port inputs to effectively solve the wire-speed processing of data packets, but this is based on sacrificing logic scale and power consumption. Therefore, when the bandwidth of the line-speed input data stream is relatively large, it is an important performance problem to be solved to realize the line-speed processing of data packets while taking into account the design logic scale and power consumption.

Contents of the invention

The technical problem to be solved by the present invention is to provide a method and device for realizing data packet line-speed processing, so as to solve the problem that performance restricts the entire data packet line-speed processing flow when processing multi-port, high-bandwidth line-speed data flow input data packets The bottleneck problem, but also take into account the logic scale and power consumption.

In order to solve the above-mentioned problem, the present invention provides a kind of device that realizes data packet wire-speed processing, is applied to processing multi-port, high-bandwidth wire-speed data flow input data packet, is characterized in that, comprises:

The input port scheduling unit is used to schedule the ports in the current multi-port data flow input request to obtain the response right according to a certain scheduling policy;

The input port data cache unit is used to cache the packet header data part of the data flow input data packet of the port that obtains the response right in the first-in-first-out buffer unit of the packet header; input data packets for the data flow of different ports that obtain the response right The non-packet header data part is cached in the corresponding non-packet header first-in-first-out cache unit;

The flow classification unit is used to analyze the header data of the data packet, then perform MAC address search, and extract the label based on the corresponding port ID, and obtain the flow ID of the data packet according to the label;

A packet header data modifying unit, configured to modify the VLAN tag of the data packet according to the result of the flow classification unit;

The input port data cache scheduling unit is used to schedule non-packet header data of the port data stream input data packets stored in the input port data cache unit;

The admission control unit is used for random early discarding of the data packets when the non-packet head data of the port data flow input data packets occupies the buffer space, performs flow supervision processing on the data packets, and simultaneously limits the input rate of the data flow;

The slice control unit is used to receive the results of the packet header data modification unit, the admission control unit and the input port data buffer scheduling unit, and reassemble the data in the data stream input data packet of each port;

The data stream data storage is used to store the result output by the slice control unit.

In the device according to the present invention, the admission control unit further includes: the applied algorithm includes a random early discard algorithm and/or a double leaky bucket rate limiting algorithm.

The device according to the present invention, wherein, the scheduling strategy in the input port scheduling unit is a scheduling arbitration strategy with priority or weight or a simple round-robin scheduling arbitration strategy without priority and weight;

Wherein, the input port scheduling unit further includes:

A scheduling policy is selected based on the packet execution processing type and the type of the input data flow data port.

The device of the present invention, further comprising:

A slice data cache unit, configured to cache the data output by the slice control unit according to first-in first-out.

In the device of the present invention, wherein the modification of the VLAN tag in the packet header data modification unit includes: adding, deleting or replacing.

In the device according to the present invention, obtaining the flow ID of the data packet in the flow classification unit is to obtain the flow ID of the data packet according to a flow binary tree search.

In order to solve the above problems, the present invention also provides a method for realizing data packet wire-speed processing, which is applied to processing multi-port, high-bandwidth wire-speed data flow input data packets, and is characterized in that, comprising the following steps:

(1) According to a certain scheduling policy, the ports in the current multi-port data flow input request are scheduled to obtain the right to respond, and the packet header data part of the data flow input data packet of the port that obtains the response right is cached in the first-in-first-out buffer unit at the beginning of the packet Middle; the non-packet header data part of the data flow input data packets of different ports that have obtained the right to respond is cached in the respective corresponding non-packet header first-in-first-out buffer units;

(2) Carry out frame header analysis to the packet header data of data packet, then carry out MAC address search, and carry out label extraction based on corresponding port ID, obtain the stream ID of this data packet according to this label, carry out VLAN tagging to this data packet simultaneously Revise;

(3) When the non-packet head data of the port data flow input data packet occupies the buffer space, the data packet is randomly discarded early, the data packet is flow supervised, and the rate of data flow input is limited;

(4) According to the results of steps (2) and (3), reassemble the data in the data stream input data packet of each port, and then transmit it to the data stream data storage for storage.

The method of the present invention, wherein, the step (3) further comprises:

The applied algorithms are random early drop algorithm and/or double leaky bucket rate limiting algorithm.

In the method of the present invention, wherein the scheduling strategy in step (1) is a scheduling arbitration strategy with priority or weight or a simple round-robin scheduling arbitration strategy without priority and weight;

Wherein, the step (1) further includes: selecting a scheduling strategy based on the execution processing type of the data packet and the type of the data port of the input data stream.

The method of the present invention, wherein, said step (4) comprises:

According to the result of steps (2) and (3), after reassembling the data in the data stream input data packet of each port, the data of the reassembled data packet is carried out first-in-first-out cache processing, and is transmitted to the data stream data memory for storage .

In the method of the present invention, the modification of the VLAN tag in step (2) includes: adding, deleting or replacing.

In the method of the present invention, obtaining the flow ID of the data packet in step (2) is to obtain the flow ID of the data packet according to the flow binary tree search.

The content of the present invention improves the performance of processing line-speed data packet input while taking into account the logic scale and power consumption, and meets the performance requirements of line-speed processing of data packets.

The present invention shows a method and device for realizing line-speed processing of Ethernet data packets. When processing multi-port data flow and high-bandwidth line-speed input, it not only reduces the scale and power consumption of the circuit to the greatest extent, but also improves the processing line speed. The performance of the high-speed data packet has reached the real-time requirement of realizing the line-speed processing of the data packet.

Description of drawings

FIG. 1 is a schematic structural diagram of a device for realizing line-speed processing of data packets according to an embodiment of the present invention;

Fig. 2 is a flow chart of a method for realizing line-speed processing of data packets according to an embodiment of the present invention.

Detailed ways

In order to solve the disadvantages of the traditional technical solutions, the present invention further elaborates a method and device for realizing data packet line-speed processing according to the present invention through the following specific examples. limit.

As shown in Figure 1, it is an embodiment of a device for realizing data packet line-speed processing in the present invention, and the specific content is as follows:

The device described in the embodiment of the present invention includes: an input port scheduling unit 101, an input port data cache unit 102, an input port data cache scheduling unit 103, a flow classification unit 104, a permission control unit 105, a packet header data modification unit 106, and a slice control unit 107 , a slice data cache unit 108 , and a data stream data storage 109 .

The data packet requests from the 4 GE input ports are first scheduled by the input port scheduling unit 101 to select the packet data of a certain GE port in the port input request, and the scheduled data packet data can perform subsequent operations; scheduling The selected data packet is cached in the input port data cache scheduling unit 102; then the packet header data of the data packet passes through the flow classification unit 104 to determine which packet header modification operation and VLAN tag conversion are carried out by the data flow; At the end of the packet, the length of the data packet and the flow ID information are sent to the admission control unit 105, and the admission control unit 105 randomly discards the data packet early according to the situation of the buffer space occupied by the input flow, and performs flow supervision processing on the data packet. At the same time, the rate of the input stream is limited. In the packet header data modification unit 106, according to the execution result of the flow classification unit, to determine which packet header modification operation and VLAN label conversion to perform for the data packet, the data after the packet header modification will be sent to the slice control unit 107 as a slice request; at the same time, the input port data cache scheduling unit 103 schedules the data stored in the non-packet header data cache FIFO corresponding to each port, and the scheduled data will send a slice request to the slice control unit 107; the slice control unit 107 arbitrates the packet header data and non-packet header data slice requests, and send the sliced data to the data stream data memory for storage; due to the restriction of the data storage rate, when the sliced data is too late to be sent to the data memory for storage, the sliced data will be stored by the slice The data cache unit 108 caches; here, the slice data cache unit 108 is composed of two identical FIFOs to perform a ping-pong operation.

Wherein, the input port scheduling unit 101 is configured to schedule a certain port in the current multi-port input request to obtain the right to respond, and perform corresponding processing on the data stream data packets of the ports that have obtained the right to respond. When the number of port requests is greater than or equal to 2, it is necessary to arbitrate all the ports that send out the scheduling requests according to a certain scheduling strategy, so as to choose to serve the data flow of one of the ports. The scheduling strategy referred to here is mainly divided into two types, one is scheduling arbitration with priority or weight, and the other is simple round-robin scheduling without priority and weight. The selection of scheduling strategy is based on packet execution The processing type and the type of the input data stream data port.

The input port data cache unit 102 is used to cache the port data that obtains the response right after the port request. Here, the input port data cache unit is implemented by FIFO, and the port data is cached based on a first-in-first-out sequence to ensure that the data stream is not modified. For the convenience of implementation, the buffer FIFO specification is designed to store the maximum amount of data for a burst operation according to the bit width of the data bus. At the same time, FIFOs are divided into two types according to whether the cached data is header or not. One is the public FIFO that caches the header data of the packet. It is the FIFO for buffering non-packet header data. Different ports have corresponding independent non-packet header data buffer FIFOs. The non-packet header data of different ports will be cached in their corresponding non-packet header data buffer FIFOs.

Described flow classification unit 104, its function is after receiving the first byte of packet of data packet, firstly carry out frame header analysis, then carry out MAC address learning search, carry out label extraction based on port ID, carry out flow binary tree search according to flow label at last , to get the flow ID of the packet.

The admission control unit 105 performs corresponding admission control functions based on the data flow; the admission control unit performs random early discarding of the data packets according to the buffer space occupied by the input stream, performs traffic supervision processing on the data packets, and at the same time rate limiting. The main algorithms used by the admission control unit are the random early discard algorithm and the double leaky bucket speed limit algorithm.

Described packet header data modifying unit 106, its function is the unit that according to the result of flow classification unit 104, packet header data is modified, the modification of data packet mainly carries out the modification of VLAN label, comprises adding, deleting or replacing; What operation is performed on the header data depends on the result of flow classification on the packet header data. After flow classification obtains the packet header data of the data packet, it first analyzes the frame header, then performs MAC address learning and search, performs label extraction based on the port ID, and finally performs flow binary tree search according to the flow label to obtain the flow ID of the data packet; the modified The packet header data sends a slice request to the slice control unit 107 , and the data after the slice operation is completed is cached in the FIFO of the slice data cache unit 108 .

The input port data cache scheduling unit 103 is configured to schedule a certain FIFO in the non-packet header data cache FIFOs storing non-packet header data to send a data slice request to the slice control unit. Here, slicing is a reassembly process of the data stream data. As mentioned above, the data packets of the data stream need to be modified with VLAN tags, including adding, deleting or replacing; and this part of the operation is processed in the packet header data modification unit for the packet header data, and after the corresponding operations are completed, the slice control unit Make a slice request. For the non-packet header data of the data packet, it is necessary to refer to the packet header modification operation of the data packet to reassemble the data, so as to ensure that the valid data bytes of the entire data stream data packet are not lost, but also maintain their positions with each other relationship without causing packet confusion.

The slice control unit 107 completes the reassembly process of the data stream data packets. The data packets of the data flow are divided into packet header data and non-packet header data. The packet header data needs to be modified on the basis of the flow classification result, including adding, deleting or replacing. In particular, the addition or deletion of labels will affect the position of the non-header data of the data packet in the new data packet. Therefore, it is necessary to reassemble the modified data of the label. Based on the above-mentioned structure, the data of the slice control unit has two sources: one is the data that can be sliced after being modified by the packet header modification unit; Non-packet header data in the header data FIFO.

The slice data cache unit 108 is used to cache the output data of the slice control unit, that is, after the data stream data packets of each port are sliced and assembled, the FIFO of new data packet data is cached; the data packets of each port are stored in the After completing a series of tasks such as VLAN tag replacement, addition or deletion and the resulting reassembly of data packets, the data will be sent to the data packet memory for storage. Before the sliced data has time to be stored in the data stream data memory 109, the sliced data will be temporarily buffered in the FIFO. Here, in order to improve the efficiency of data packet processing, we use two slices of the same slice data cache unit 108 to perform ping-pong operation, so as to achieve the purpose of processing data packets at a line speed.

As shown in FIG. 2 , it is a flow chart of a method for realizing line-speed processing of data packets according to an embodiment of the present invention. In conjunction with accompanying drawing 1, its process description is as follows:

Step 201. Scheduling the data of the input ports GE0-GE3 according to the simple round-robin scheduling strategy; enter into step 202;

Step 202, after the scheduling is successful, check whether the packet data is wrong, if wrong, then directly discard; otherwise, enter 203;

Step 203, judge whether this data packet is a packet header, if it is packet header data, enter step 204, if it is non-packet header data, enter step 205;

Step 204, this data is cached in the packet first data cache FIFO 4; Enter step 206;

Step 205, the data packets belonging to GE0-GE3 ports are respectively buffered in the corresponding non-packet header data buffers FIFO0-FIFO3; enter step 211;

Step 206, the packet header data is sent to the flow classification unit to perform corresponding processing, and check whether the flow classification search is passed; if the flow classification search fails, the data packet is discarded; otherwise, if the flow classification search is successful, enter step 207;

Step 207, judging whether the data is the end of the data packet; if it is the end of the packet, enter step 208, otherwise enter step 209;

Step 208, the end of the data packet, perform admission control, and discard if not passed; otherwise, enter step 209;

Step 209, perform packet header modification, the modified packet header data sends a slice request to the slice control unit; enter step 210;

Step 210, cache the completed slice data in the slice FIFO, and send the cached data to the memory;

Step 211, the data buffer FIFO0～FIFO3 scheduling that stores the non-packet header data, after the scheduling is successful, judge whether it is the end of the packet, and then enter step 212 for the end of the packet, otherwise enter step 213;

Step 212, execute admission control, discard if not passed; enter step 213 if passed;

Step 213 , send a slice request to the slice control unit; go to step 210 .

Certainly, the present invention can also have other various embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (14)

1. A device that realizes data packet wire-speed processing, is applied to processing multi-port, high-bandwidth wire-speed data flow input data packets, is characterized in that, comprising: The input port scheduling unit is used to schedule the ports in the current multi-port data flow input request to obtain the response right according to a certain scheduling strategy; The input port data cache unit is used to cache the packet header data part of the data flow input data packet of the port that obtains the response right in the first-in-first-out buffer unit of the packet header; input data packets for the data flow of different ports that obtain the response right The non-packet header data part is cached in the corresponding non-packet header first-in-first-out cache unit; The flow classification unit is used to analyze the header data of the data packet, then perform MAC address search, and extract the label based on the corresponding port ID, and obtain the flow ID of the data packet according to the label; A packet header data modifying unit, configured to modify the VLAN tag of the data packet according to the result of the flow classification unit; The input port data cache scheduling unit is used to schedule non-packet header data of the port data stream input data packets stored in the input port data cache unit; The admission control unit is used for random early discarding of the data packets according to the condition that the non-packet head data of the port data flow input data packets occupies the buffer space, performs flow supervision processing on the data packets, and limits the input rate of the data flow at the same time; The slice control unit is used to receive the results of the packet header data modification unit, the admission control unit and the input port data buffer scheduling unit, and reassemble the data in the data stream input data packet of each port; The data stream data storage is used to store the result output by the slice control unit. 2. The device according to claim 1, wherein the admission control unit further comprises: the applied algorithm includes a random early discard algorithm and/or a double leaky bucket rate limiting algorithm. 3. The device according to claim 1, wherein the scheduling strategy in the input port scheduling unit is a scheduling arbitration strategy with priority or weight or a simple round-robin scheduling without priority and weight Arbitration strategy. 4. The device according to claim 3, wherein the input port scheduling unit further comprises: A scheduling policy is selected based on the packet execution processing type and the type of the input data flow data port. 5. The apparatus of claim 1, further comprising: A slice data cache unit, configured to cache the data output by the slice control unit according to first-in first-out. 6. The device according to claim 1, wherein the modification of the VLAN tag in the packet header data modification unit includes: adding, deleting or replacing. 7. The device according to claim 1, wherein obtaining the flow ID of the data packet in the flow classification unit is to obtain the flow ID of the data packet according to a flow binary tree search. 8. A method for realizing data packet wire-speed processing, applied to processing multi-port, high-bandwidth wire-speed data flow input data packets, is characterized in that, comprising the following steps: (1) According to a certain scheduling policy, the ports in the current multi-port data flow input request are scheduled to obtain the right to respond, and the packet header data part of the data flow input data packet of the port that obtains the response right is cached in the first-in-first-out buffer unit at the beginning of the packet Middle; the non-packet header data part of the data flow input data packets of different ports that have obtained the right to respond is cached in the respective corresponding non-packet header first-in-first-out buffer units; (2) Carry out frame header analysis to the packet header data of data packet, then carry out MAC address search, and carry out label extraction based on corresponding port ID, obtain the stream ID of this data packet according to this label, carry out VLAN tagging to this data packet simultaneously Revise; (3) According to the situation that the non-packet head data of the port data flow input data packet occupies the buffer space, the data packet is randomly discarded early, and the data packet is flow supervised and processed, and the rate of data flow input is limited at the same time; (4) According to the results of steps (2) and (3), reassemble the data in the data stream input data packet of each port, and transmit it to the data stream data memory for storage. 9. method as claimed in claim 8, is characterized in that, described step (3) further comprises: The applied algorithms are random early drop algorithm and/or double leaky bucket rate limiting algorithm. 10. The method according to claim 8, wherein the scheduling strategy in step (1) is a scheduling arbitration strategy with priority or weight or a simple round-robin scheduling arbitration without priority and weight Strategy. 11. The method according to claim 10, characterized in that, the step (1) further comprises: selecting a scheduling strategy based on the data packet execution processing type and the type of the input data flow data port. 12. The method according to claim 8, characterized in that, said step (4) comprises: According to the result of steps (2) and (3), after reassembling the data in the data stream input data packet of each port, the data of the reassembled data packet is carried out first-in-first-out cache processing, and is transmitted to the data stream data memory for storage . 13. The method according to claim 8, wherein the modification of the VLAN tag in step (2) comprises: adding, deleting or replacing. 14. The method according to claim 8, wherein said obtaining the flow ID of the data packet in step (2) is to obtain the flow ID of the data packet according to a flow binary tree search.

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