CN101131586B - M-LVDS high-speed serial communication control method in the manipulator system - Google Patents
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Abstract
机械臂系统中的M-LVDS高速串行通信控制方法，它涉及的是高速串行通信的技术领域。它是为了克服现有机械手的上位机与下位机之间通讯总线的通信速率太低，导致存在下位机不能快速的从上位机中更新关节角度期望值、速度值、加速度值和此时关节所承受的重力数据的问题。它的主M-LVDS驱动收发器(2-2)、M-LVDS驱动收发器(3-1)的串行通信端都依次连接在串行总线(4)上。它的方法步骤为：每个分节点(3)读取自己的地址数据、待机、实时接收串行总线(4)上传送的数据，主节点(2)待机，主节点(2)周期为T的中断发送数据，分节点(3)接收数据、循环冗余校验。本发明能达到500Mbps(百万字节/秒)的传输速度，在实际应用中将数据传输率被设定为25Mbps，就已满足机械臂实时控制的要求。
The M-LVDS high-speed serial communication control method in the mechanical arm system relates to the technical field of high-speed serial communication. It is to overcome the fact that the communication rate of the communication bus between the upper computer and the lower computer of the existing manipulator is too low, which leads to the fact that the lower computer cannot quickly update the expected value of joint angle, velocity value, acceleration value and joint bearing at this time from the upper computer. problem with gravity data. Its main M-LVDS driving transceiver (2-2) and the serial communication terminals of the M-LVDS driving transceiver (3-1) are all sequentially connected to the serial bus (4). Its method steps are: each sub-node (3) reads its own address data, stands by, and receives data transmitted on the serial bus (4) in real time, the master node (2) is on standby, and the master node (2) cycle is T The interrupt sends data, and the sub-node (3) receives data and performs cyclic redundancy check. The present invention can reach a transmission speed of 500 Mbps (megabytes/second). In practical applications, the data transmission rate is set to 25 Mbps, which meets the requirements for real-time control of the manipulator.
Description
Technical field
What the present invention relates to is the technical field of high-speed serial communication.
Background technology
The collapsible robot system of HIT four-degree-of-freedom is made up of mechanical arm and terminal HIT-DLR Dextrous Hand, and overall weight is about 25kg, and the straight configuration height is about 1.3m.Mechanical arm has four rotary joints, and the design in each joint adopts big center pit permanent-magnet brushless DC electric machine to drive, and realizes big moment output by 160: 1 harmonic speed reducer.All cablings all pass from center pit in the system, compact conformation, and avoid producing in the joint coiling phenomenon.By this robot, can replace the people under dangerous, rugged environment, to finish the complex operations task that common unit institute can not finish, will play a significant role in fields such as the nuclear industry environment of abominable space environment, danger and high-level service robots.
Adopt the upper and lower computer structure on the mechanical arm electrical design: slave computer is made up of four joints and Dextrous Hand, and control circuit is integrated in joint and Dextrous Hand inside, and its microprocessor all adopts FPGA; The host computer circuit design is integrated in the principal computer by pci bus, and its microprocessor uses DSP/FPGA, and wherein FPGA mainly realizes the transmission-receiving function of data, is the important component part of system bus.Upper and lower computer adopts two high-speed serial bus, and with mechanical arm and Dextrous Hand separate communications, to realize grand little coordinated manipulation of real-time high-precision, wherein Dextrous Hand adopts point-to-point PPSeCo communication (patent No. 200410013732.0).In addition, host computer DSP and principal computer real-time Communication for Power, DSP receives the operation signal of principal computer, and principal computer is by the state variable of DSP feedback mechanical arm.
Can only carry out fixed-point arithmetic for host computer DSP, lower computer FPGA, the slow and internal microprocessor resource-constrained of arithmetic speed is unfavorable for realizing computings such as system kinematics, dynamics, trajectory planning and dynamic compensation.In order to improve robot system dynamic and stability, slave computer should upgrade joint angles expectation value, velocity amplitude, accekeration and gravity that this moment, the joint was born from host computer with the fastest speed.
Shanghai Communications University has applied for " based on the patent of the individual mechanical arm system (publication number 1434391) of USB (universal serial bus); usb bus is applied to the solid mechanical arm is connected with personal computer; make mechanical arm have plug-and-play feature, but real system still is subjected to the restriction of the cable length and the traffic rate of defined in the usb bus agreement.
Summary of the invention
The present invention is for the traffic rate of communication bus between host computer that overcomes the existing machinery hand and the slave computer is too low, cause existing slave computer can not from host computer, upgrade fast joint angles expectation value, velocity amplitude, accekeration and this moment the gravimetric data that bear in the joint problem.And M-LVDS high-speed serial communication control method in a kind of mechanical arm system has been proposed.
Realize that device of the present invention is made up of host node 2, a plurality of partial node 3, universal serial bus 4, resistance R T1, resistance R T2;
Host node 2 drives transceiver 2-2 by main fpga logic device 2-1, main M-LVDS and forms;
The communication data input/output bus end of fpga logic device 2-1 connects the communication data input/output bus end of the DSP digital signal processor 1 in the host computer, and the M-LVDS Data Control output input bus end of fpga logic device 2-1 connects the Data Control output input bus end that main M-LVDS drives transceiver 2-2;
Each partial node 3 all drives transceiver 3-1, fpga logic device 3-2 by M-LVDS and forms;
M-LVDS drives the M-LVDS Data Control output input bus end of the Data Control output input bus end connection fpga logic device 3-2 of transceiver 3-1, and the communication data input/output bus end of fpga logic device 3-2 is the external data input/output terminal;
Main M-LVDS in the host node 2 drives the serial communication end of transceiver 2-2, the serial communication end that the M-LVDS in each partial node 3 drives transceiver 3-1 all is connected in turn on the universal serial bus 4, between two lines at universal serial bus 4 two ends respectively cross-over connection resistance R T1, resistance R T2 are arranged.
The step of the M-LVDS high-speed serial communication control method in its mechanical arm system is:
Step 1, start, System self-test;
Fpga logic device 3-2 in step 2, each partial node 3 reads the address date of oneself; Address date comprises the address that receives bus address and send to the main fpga logic device 2-1 in the host node 2;
Receiver module among the main fpga logic device 2-1 of step 4, host node 2 is in holding state, the transceiver module of fpga logic device 3-2 in each partial node 3 is in holding state and receives the data that transmit on the universal serial bus 4 in real time, and the sending module of the main fpga logic device 2-1 in the host node 2 begins the timing interruption that the unlatching cycle is T;
The sending module of the main fpga logic device 2-1 of step 5, host node 2 judges whether to enter T and regularly interrupts, and judged result is not for, then standby, and judged result is for being then to enter T timing interrupt procedure; In T timer interrupt routine process, each partial node 3 data that at first will receive are merged into to wrap according to partial node 3 orders and pass the DSP digital signal processor 1 that sends in the host computer, (first cycle data is 0) passes the data of issuing each partial node 3 in the DSP digital signal processor 1 in the host computer then down; Open single partial node 3 data of T1 and send regularly interruption, and open the transmission zone bit, withdraw from the T interrupt procedure and enter holding state;
Step 6, under holding state, judge whether to enter that T1 interrupts and send whether zone bit is 1, judged result is not for, then standby, judged result is for being then to enter T1 timing interrupt procedure; In T1 timing interrupt procedure, at first send single partial node 3 data; Whether the data of judging last partial node 3 then send end, the result then enters holding state and waits for that next T1 interrupts sending the data of next partial node 3 for not, and judged result is for being, then close T1 and regularly interrupt and will send the zone bit zero clearing, continue standby;
Step 7, when the sending module of the main fpga logic device 2-1 of host node 2 sends each partial node 3 data successively, the fpga logic device 3-2 transceiver module in each partial node 3 is in holding state; Under holding state, the fpga logic device 3-2 in each partial node 3 receives on the universal serial bus 4 data that transmit in real time, at first judges whether to detect the SOFO data, and judged result then continues standby for not, and the result is for being, then the receiver address segment data; After receiving the address field data, the fpga logic device 3-2 in the partial node 3 carries out matching addresses and detects, and judged result is for denying, then this partial node 3 is not issued in explanation, continues to hold machine, and judged result is for being, then receive total data, and data are deposited in the corresponding memory; Whether after receiving data, data are carried out cyclic redundancy check (CRC), be used for specified data and wrap in transmission course and make mistakes; Judged result then makes an explanation and deal with data for being, judged result then abandons the data that receive for not; After the cyclic redundancy checking finishes, start at once and interrupt sending this partial node 3 data; After interruption sends self partial node 3 data, continue standby;
Step 8, when having data to return on the universal serial bus 4, the receiver module of the main fpga logic device 2-1 of host node 2 is in holding state; Under holding state, the main fpga logic device 2-1 of host node 2 receives the data of uploading on the universal serial bus 4 in real time, at first judges whether to detect the SOFO data, and judged result then continues standby for not, and judged result is for being, then the receiver address segment data; After receiving the address field data, the main fpga logic device 2-1 of host node 2 carries out matching addresses and detects, judged result is for denying, illustrate that then data send the wrong address field data that do not belong to, continue to hold machine, judged result then judges it is the data which partial node 3 is sent for being, and the reception total data, it is stored in the corresponding memory; Whether partial node 3 Data Receiving will be carried out cyclic redundancy check (CRC) after finishing, be used for specified data and wrap in transmission course and make mistakes; Judged result then makes an explanation and deal with data for being, judged result then abandons the data that receive for not; After the cyclic redundancy checking finishes, continue standby;
Step 9, return operating procedure three.
The present invention can reach the transmission speed of 500Mbps (megabyte/second), in actual applications data transmission rate is set to 25Mbps, has just satisfied the mechanical arm requirement of control in real time.The M-LVDS signal used ± differential signal of 350mV, therefore has minimum electromagnetic interference (EMI), very strong antijamming capability, this is for extremely important sensor data acquisition, and extremely low electromagnetic interference (EMI) makes that high-precision sensor data acquisition is easy to realize more.And has with low cost a, advantage of simple structure of cost.
Description of drawings
Fig. 1 is an integrated circuit structural representation of the present invention.
Embodiment
Embodiment one: in conjunction with Fig. 1 present embodiment is described, realizes that the device of the M-LVDS high-speed serial communication control method in the present embodiment mechanical arm system is made up of host node 2, a plurality of partial node 3, universal serial bus 4, resistance R T1, resistance R T2;
Host node 2 drives transceiver 2-2 by main fpga logic device 2-1, main M-LVDS and forms; The communication data input/output bus end of fpga logic device 2-1 connects the communication data input/output bus end of the DSP digital signal processor 1 in the host computer, and the M-LVDS Data Control output input bus end of fpga logic device 2-1 connects the Data Control output input bus end that main M-LVDS drives transceiver 2-2;
Each partial node 3 all drives transceiver 3-1, fpga logic device 3-2 by M-LVDS and forms; M-LVDS drives the M-LVDS Data Control output input bus end of the Data Control output input bus end connection fpga logic device 3-2 of transceiver 3-1, and the communication data input/output bus end of fpga logic device 3-2 is the external data input/output terminal;
Main M-LVDS in the host node 2 drives the serial communication end of transceiver 2-2, the serial communication end that the M-LVDS in each partial node 3 drives transceiver 3-1 all is connected in turn on the universal serial bus 4, between two lines at universal serial bus 4 two ends respectively cross-over connection resistance R T1, resistance R T2 are arranged.
The step of the M-LVDS high-speed serial communication control method in its mechanical arm system is:
Step 1, start, System self-test;
Fpga logic device 3-2 in step 2, each partial node 3 reads the address date of oneself; Address date comprises the address that receives bus address and send to the main fpga logic device 2-1 in the host node 2;
Receiver module among the main fpga logic device 2-1 of step 4, host node 2 is in holding state, the transceiver module of fpga logic device 3-2 in each partial node 3 is in holding state and receives the data that transmit on the universal serial bus 4 in real time, and the sending module of the main fpga logic device 2-1 in the host node 2 begins the timing interruption that the unlatching cycle is T;
The sending module of the main fpga logic device 2-1 of step 5, host node 2 judges whether to enter T and regularly interrupts, and judged result is not for, then standby, and judged result is for being then to enter T timing interrupt procedure; In T timer interrupt routine process, each partial node 3 data that at first will receive are merged into to wrap according to partial node 3 orders and pass the DSP digital signal processor 1 that sends in the host computer, (first cycle data is 0) passes the data of issuing each partial node 3 in the DSP digital signal processor 1 in the host computer then down; Open single partial node 3 data of T1 and send regularly interruption, and open the transmission zone bit, withdraw from the T interrupt procedure and enter holding state;
Step 6, under holding state, judge whether to enter that T1 interrupts and send whether zone bit is 1, judged result is not for, then standby, judged result is for being then to enter T1 timing interrupt procedure; In T1 timing interrupt procedure, at first send single partial node 3 data; Whether the data of judging last partial node 3 then send end, the result then enters holding state and waits for that next T1 interrupts sending the data of next partial node 3 for not, and judged result is for being, then close T1 and regularly interrupt and will send the zone bit zero clearing, continue standby;
Step 7, when the sending module of the main fpga logic device 2-1 of host node 2 sends each partial node 3 data successively, the fpga logic device 3-2 transceiver module in each partial node 3 is in holding state; Under holding state, the fpga logic device 3-2 in each partial node 3 receives on the universal serial bus 4 data that transmit in real time, at first judges whether to detect the SOFO data, and judged result then continues standby for not, and the result is for being, then the receiver address segment data; After receiving the address field data, the fpga logic device 3-2 in the partial node 3 carries out matching addresses and detects, and judged result is for denying, then this partial node 3 is not issued in explanation, continues to hold machine, and judged result is for being, then receive total data, and data are deposited in the corresponding memory; Whether after receiving data, data are carried out cyclic redundancy check (CRC), be used for specified data and wrap in transmission course and make mistakes; Judged result then makes an explanation and deal with data for being, judged result then abandons the data that receive for not; After the cyclic redundancy checking finishes, start at once and interrupt sending this partial node 3 data; After interruption sends self partial node 3 data, continue standby;
Step 8, when having data to return on the universal serial bus 4, the receiver module of the main fpga logic device 2-1 of host node 2 is in holding state; Under holding state, the main fpga logic device 2-1 of host node 2 receives the data of uploading on the universal serial bus 4 in real time, at first judges whether to detect the SOFO data, and judged result then continues standby for not, and judged result is for being, then the receiver address segment data; After receiving the address field data, the main fpga logic device 2-1 of host node 2 carries out matching addresses and detects, judged result is for denying, illustrate that then data send the wrong address field data that do not belong to, continue to hold machine, judged result then judges it is the data which partial node 3 is sent for being, and the reception total data, it is stored in the corresponding memory; Whether partial node 3 Data Receiving will be carried out cyclic redundancy check (CRC) after finishing, be used for specified data and wrap in transmission course and make mistakes; Judged result then makes an explanation and deal with data for being, judged result then abandons the data that receive for not; After the cyclic redundancy checking finishes, continue standby;
Step 9, return operating procedure three.
In the said method step: T is chosen as 200us, and N is chosen as 7 partial nodes, and each node time spent T1 is chosen as 28us.
The resistance that described resistance R T1, resistance R T2 select for use all is 100 ohm, the model that main fpga logic device 2-1, fpga logic device 3-2 select for use all is an ALTERA Cyclone EP1C20F32417 programmable gate array, the model that main M-LVDS driving transceiver 2-2, M-LVDS driving transceiver 3-1 select for use is MLVDS204 all, and the model that the DSP digital signal processor 1 in the host computer is selected for use is that TMS320C6713, universal serial bus 4 are twisted-pair feeder.
Claims (1)
1. the M-LVDS high-speed serial communication control method in the mechanical arm system realizes that the device of this method is made up of host node (2), a plurality of partial node (3), universal serial bus (4), resistance R T1, resistance R T2;
Host node (2) drives transceiver (2-2) by main fpga logic device (2-1), main M-LVDS and forms;
The communication data input/output bus end of fpga logic device (2-1) connects the communication data input/output bus end of the DSP digital signal processor (1) in the host computer, and the M-LVDS Data Control output input bus end of fpga logic device (2-1) connects the Data Control output input bus end that main M-LVDS drives transceiver (2-2);
Each partial node (3) all is made up of M-LVDS driving transceiver (3-1), fpga logic device (3-2);
M-LVDS drives the M-LVDS Data Control output input bus end of the Data Control output input bus end connection fpga logic device (3-2) of transceiver (3-1), and the communication data input/output bus end of fpga logic device (3-2) is the external data input/output terminal;
Main M-LVDS in the host node (2) drives the serial communication end of transceiver (2-2), the serial communication end that the M-LVDS in each partial node (3) drives transceiver (3-1) all is connected in turn on the universal serial bus (4), between two lines at universal serial bus (4) two ends respectively cross-over connection resistance R T1, resistance R T2 are arranged, it is characterized in that steps of the method are:
Step 1, start, System self-test;
Fpga logic device (3-2) in step 2, each partial node (3) all reads the address date of oneself; Address date comprises the address that receives bus address and send to the main fpga logic device (2-1) in the host node (2);
Step 3, data transmit-receive process time T is set, partial node quantity N is provided with each partial node (3) and sends data time T1;
Receiver module in the main fpga logic device (2-1) of step 4, host node (2) is in holding state, the transceiver module of the fpga logic device (3-2) in each partial node (3) is in holding state and also receives the data that universal serial bus (4) is gone up transmission in real time, and the sending module of the main fpga logic device (2-1) in the host node (2) begins the timing interruption that the unlatching cycle is T;
The sending module of the main fpga logic device (2-1) of step 5, host node (2) judges whether to enter T and regularly interrupts, and judged result is not for, then standby, and judged result is for being then to enter T timing interrupt procedure; In T timer interrupt routine process, each partial node (3) data that at first will receive are merged into to wrap according to partial node (3) order and pass the DSP digital signal processor (1) that sends in the host computer, wherein first cycle data is 0, passes the data of issuing each partial node (3) in the DSP digital signal processor (1) in the host computer then down; Open single partial node (3) data of T1 and send regularly interruption, and open the transmission zone bit, withdraw from the T interrupt procedure and enter holding state;
Step 6, under holding state, judge whether to enter that T1 interrupts and send whether zone bit is 1, judged result is not for, then standby, judged result is for being then to enter T1 timing interrupt procedure; In T1 timing interrupt procedure, at first send single partial node (3) data; Whether the data of judging last partial node (3) then send end, the result then enters holding state and waits for that next T1 interrupts sending the data of next partial node (3) for not, and judged result is for being, then close T1 and regularly interrupt and will send the zone bit zero clearing, continue standby;
Step 7, when the sending module of the main fpga logic device (2-1) of host node (2) sends each partial node (3) data successively, fpga logic device (3-2) transceiver module in each partial node (3) is in holding state; Under holding state, the fpga logic device (3-2) in each partial node (3) receives universal serial bus (4) in real time and goes up the data that transmit, and at first judges whether to detect the SOFO data, judged result is for denying, then continue standby, the result is for being, then the receiver address segment data; After receiving the address field data, the fpga logic device (3-2) in the partial node (3) carries out matching addresses and detects, and judged result is for denying, then this partial node (3) is not issued in explanation, continues to hold machine, and judged result is for being, then receive total data, and data are deposited in the corresponding memory; Whether after receiving data, data are carried out cyclic redundancy check (CRC), be used for specified data and wrap in transmission course and make mistakes; Judged result then makes an explanation and deal with data for being, judged result then abandons the data that receive for not; After the cyclic redundancy checking finishes, start at once and interrupt sending this partial node (3) data; After interruption sends self partial node (3) data, continue standby;
Step 8, when having data to return on the universal serial bus (4), the receiver module of the main fpga logic device (2-1) of host node (2) is in holding state; Under holding state, the main fpga logic device (2-1) of host node (2) receives the data of uploading on the universal serial bus (4) in real time, at first judges whether to detect the SOFO data, judged result is for denying, then continue standby, judged result is for being, then the receiver address segment data; After receiving the address field data, the main fpga logic device (2-1) of host node (2) carries out matching addresses and detects, judged result is for denying, illustrate that then data send the wrong address field data that do not belong to, continue to hold machine, judged result then judges it is the data which partial node (3) is sent for being, and the reception total data, it is stored in the corresponding memory; After a partial node (3) Data Receiving finishes, will carry out cyclic redundancy check (CRC), and be used for specified data and wrap in transmission course and whether make mistakes; Judged result then makes an explanation and deal with data for being, judged result then abandons the data that receive for not; After the cyclic redundancy checking finishes, continue standby;
Step 9, return operating procedure three.
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| CN101834695B (en) * | 2010-03-18 | 2012-10-24 | 中北大学 | Self-adaptive multi-path serial redundant high-speed bus |
| CN101819427B (en) * | 2010-03-29 | 2011-11-09 | 哈尔滨工业大学 | On-chip control system of digital articulation based on FPGA (Field Programmable Gate Array) |
| CN101846986B (en) * | 2010-04-01 | 2011-10-26 | 煤炭科学研究总院上海分院 | Method for detecting serial digital quantity signals |
| CN102621974B (en) * | 2012-04-24 | 2013-11-27 | 上海维宏电子科技股份有限公司 | Industrial automatic real-time control device and method based on communication bus |
| CN104102604B (en) * | 2013-04-12 | 2017-07-04 | 杭州迪普科技股份有限公司 | A kind of business processing device |
| CN104502770B (en) * | 2014-12-23 | 2017-10-20 | 中煤科工集团上海研究院 | A kind of serial signal detection system and detection method |
| CN108234267B (en) * | 2018-02-08 | 2023-11-07 | 卡斯柯信号有限公司 | Communication system based on M-LVDS real-time multi-master high-speed bus |
| CN112100112B (en) * | 2020-09-18 | 2022-05-27 | 中车株洲电力机车研究所有限公司 | Full duplex bus and train |
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