CN101119179B - Transmission system - Google Patents

Abstract

A transmission system includes a receiving device and a transmitting device. The transmitting device is used for transmitting a first data and a second data to the receiving device and comprises a buffer unit, a storage unit and a transmission unit. The buffer unit is used for storing a stop value. The storage unit stores a first data and a second data. The transmission unit collects the first data and transmits the first data to a receiving device, and then collects the second data and transmits the second data to the receiving device after waiting for a preset time according to the stop value.

Description

Transmission system

technical field

The present invention relates to a transmission system, in particular to a transmission system with programmable delay time.

Background technique

In a system on chip (system on chip), a transmission device is usually attached for system communication. A common transmission device is a Universal Asynchronous Receiver/Transmitter (hereinafter referred to as UART). In the system chip of the set-top box (Set Top Box; STB), UART is often used in the conditional access (Conditional Access; CA) system as the controller of the smart card (smart card, IC card, 7816 card).

In this system, if the non-First-In First-Out (FIFO) mode is used for data transmission, it is easy to cause the disadvantages of large system data consumption and many interruptions. If the first-in-first-out mode is used, the smart card usually requires a fixed interval between two bytes when the UART sends data.

However, in known bytes, each byte can have one or two stop bits. The interval between bytes is therefore the duration of one or two stop bits. The interval time required by smart cards is usually greater than the duration of two stop bits.

A known solution is to use software to control the interval between two bit groups. However, when the central processing unit (CPU) is in a busy state, or in the case of sending a large amount of data, it is easy to cause the interval between two bytes to be too long, causing the smart card to timeout (timeout), thus causing Troubleshoot errors etc.

Contents of the invention

In order to solve the above-mentioned problems existing in the prior art, the present invention provides a transmission system, which includes a receiving device and a transmitting device. The transmitting device is used for transmitting a first and a second data to the receiving device, and includes a buffer unit, a storage unit and a transmission unit. The cache unit is used for storing a stop value. The storage unit stores a first data and a second data. The transmission unit collects the first data and sends it to a receiving device, and waits for a preset time according to the stop value, and then collects the second data and sends it to the receiving device.

Description of drawings

Fig. 1 is a schematic diagram of the transmission system of the present invention.

FIG. 2 is the transmission format of data _D1 and _D2 .

Fig. 3 is a possible embodiment of the transmission unit.

Symbol Description:

12: receiving device; 14: transmitting device;

142: cache unit; 144: storage unit;

146: transmission unit; 148: clock generator;

20: start bit; 21~28: data bit;

29: parity bit; 32: bit counter;

34: byte counter; 36: delay counter;

38: Controller.

Detailed ways

In order to make the above-mentioned and other purposes, features, and advantages of the present invention more clearly understood, the preferred embodiments are specifically listed below, together with the accompanying drawings, and are described in detail as follows:

Fig. 1 is a schematic diagram of the transmission system of the present invention. As shown in the figure, the transmission system 10 includes a receiving device 12 and a transmitting device 14 . The transmitting device 14 transmits data to the receiving device 12, and can control the interval time between two data. In this embodiment, the transmitting device 14 is a UART, which transmits the data _D1 and _D2 to the receiving device 12 in an asynchronous manner, wherein the interval time between the data _D1 and _D2 can be controlled.

The transmission device 14 includes a cache unit 142 , a storage unit 144 and a transmission unit 146 . The buffer unit 142 stores a stop value S _S . The storage unit 144 stores data D ₁ and D ₂ . The transmitting unit 146 collects the data D ₁ and transmits it to the receiving device 12 , and waits for a preset time according to the stop value _SS before collecting the data D ₂ and transmitting it to the receiving device 12 .

FIG. 2 is the transmission format of data _D1 and _D2 . The data D ₁ and D ₂ both include a start bit (start bit) 20 , data bits (data bits) 21 - 28 and a parity bit (parity bit) 29 . The present invention does not limit the number of data bits. In this embodiment, the data bits of the data D ₁ and D ₂ are both eight bits. In the data _D1 and _D2 , the duration T of each bit is the same.

Fig. 3 is a possible embodiment of the transmission unit. The transmission unit 146 includes a bit counter 32 , a byte counter 34 , a delay counter 36 and a controller 38 .

The bit counter 32 starts counting according to the clock signal S _CLK . In this embodiment, the clock signal S _CLK is generated by a clock generator 148 . When the bit counter 32 counts to a first default value, the bit trigger signal _ST1 is output to the byte counter 34 and the controller 38 . When the controller 38 receives the bit trigger signal _ST1 , it starts to receive the start bit 20 of the data _D1 .

In this embodiment, the time for the bit counter 32 to count up to the first default value is equal to the duration T of a single bit of the data _D1 . Therefore, when the controller 38 has received the start bit 20 of the data D ₁ , the bit counter 32 will output the bit trigger signal S _T1 again, so that the controller 38 continues to collect the data bit 21 of the data D ₁ , and the data D ₁ The start bit 20 is output to the receiving device 14 .

When the bit counter 32 outputs the bit trigger signal S _T1 , the byte counter 34 starts counting according to the bit trigger signal S _T1 . When the byte counter 34 counts to a second default value, the byte trigger signal S _T2 is output to trigger the delay counter 36 and make the controller 38 stop collecting data in the storage unit 144 .

In this embodiment, the time for counting up to the second default value by the byte counter 34 is equal to the total time 10T of the data _D1 . When the byte counter 34 counts to the second default value, since the controller 38 has collected all bits of the data D ₁ and transmitted the data D ₁ to the receiving device 12 , the collection action of the controller 38 is suspended.

After the byte counter 34 outputs the byte trigger signal _ST2 , the delay counter 36 starts counting. When the delay counter 36 counts to a third default value, the delay trigger signal _ST3 is output, so that the controller 38 starts to collect the data D ₂ in the storage unit 144 .

In this embodiment, when the controller 38 receives the byte trigger signal _ST2 , it will temporarily store the acquisition and storage unit 144; when the controller 38 receives the delay trigger signal _ST3 , it will start to acquire the storage unit 144. Thus, the delay counter 36 counts to the third default value for a time equal to the time the controller 38 pauses.

Since the transmission unit 146 can program the interval between two data to meet the requirements of the smart card, and does not need software timing, thereby reducing the resource consumption of the system, and also avoiding that the central processing unit is too busy to send the data to the transmission device 14 , resulting in the smart card timeout problem.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Anyone skilled in this art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of an invention shall be determined by the scope of the patent application.

Claims (9)

1. hardware transmission system comprises:

One receiving system; And

One conveyer, in order to send first and second data to this receiving system, this conveyer comprises:

One buffer unit stops value in order to store one;

One storage element stores this first and second data; And

One transmission unit is gathered these first data and is sent this receiving system to, and according to this value of stopping, waiting for a Preset Time after, gather these second data again and send this receiving system to.

2. hardware transmission system as claimed in claim 1, wherein these first and second data all have ten.

3. hardware transmission system as claimed in claim 2, wherein ten of these first and second data comprise, one opens beginning position, eight data bit and a coordination position.

4. hardware transmission system as claimed in claim 2 also comprises a clock generator, in order to produce a clock signal.

5. hardware transmission system as claimed in claim 4, this transmission unit wherein comprises:

One controller is gathered these ten of these first data earlier and is sent this receiving system to;

One digit counter, when this controller collects of this first data, then begin counting according to this clock signal, when counting up to one first default value, then export a triggering signal, wherein this digit counter time of counting up to this first default value equals the duration of the single position of these first data;

One byte counter, begin counting according to this triggering signal, when counting up to one second default value, then export a byte triggering signal, make this controller stop to gather the data in this storage element, and this byte counter time of counting up to this second default value equal the total time of these first data; And

One delay counter, begin counting according to this byte triggering signal, when counting up to this value of stopping, then export a delayed trigger signal and send this controller to, make its described a plurality of positions that begin to gather these second data, wherein this delay counter time of counting down to this value of stopping equals the time that this controller suspends.

6. hardware transmission system as claimed in claim 5, wherein this controller is to transmit this first and second data with an asynchronous system.

7. hardware transmission system as claimed in claim 6, wherein when this digit counter was exported this triggering signal, then this controller provided this position of these first data that collected to send this receiving system to.

8. hardware transmission system as claimed in claim 6, wherein this conveyer is a UART Universal Asynchronous Receiver Transmitter.

9. hardware transmission system as claimed in claim 6, wherein this delay counter time of counting up to this value of stopping equals this Preset Time.

Images