CN101118925A - MOS transistor element and its manufacturing method and improving method - Google Patents

Abstract

The invention relates to a Metal Oxide Semiconductor (MOS) transistor element, wherein, a semiconductor substrate comprises an active region and an isolation region, a selective epitaxial layer is arranged between the active region and a gate structure, and a peripheral part of the epitaxial layer covers the upper part of the peripheral part of the isolation region. Thus, the channel width can be increased, and the drain current can be improved.

Description

Metal-oxide-semiconductor transistor element, manufacturing method and improvement method thereof

technical field

The invention relates to a semiconductor device and its manufacturing method and improvement method, in particular to a MOS transistor element, its manufacturing method and the method of improving drain current.

Background technique

With the development of metal oxide semiconductor transistors (MOSFETs) towards miniaturization and entering the deep submicron era, such as processes below 65 nanometers (nm), the improvement of the drive current of MOS transistor elements has become increasingly apparent. important.

It is known to use strained silicon to increase the mobility of holes or electrons to improve the performance of metal-oxide-semiconductor transistors. For example, using the principle that the lattice constant of the silicon germanium layer is different from that of silicon to cause structural strain when silicon is epitaxy on the silicon germanium layer, the relaxed silicon (Si) germanium (Ge) layer is grown on a silicon-on-insulator (SOI) layer. On the substrate or the traditional silicon substrate, silicon epitaxy is grown on the relaxed silicon germanium layer to form strained silicon. Since the lattice constant of the silicon germanium layer is larger than that of silicon, the band structure of silicon is changed, resulting in increased carrier mobility.

In addition, a selective epitaxial growth method is also used. After the gate is formed, doped germanium is embedded in the source/drain region to form a squeezed strained silicon film to improve the electron mobility of the PMOS. Or in the NMOS process, carbon-doped silicon is selectively epitaxy embedded in the source/drain region to form a stretched strained silicon film to enhance electron mobility.

FIG. 1 shows a schematic top view of several conventional MOS transistor devices. FIG. 2 shows a schematic cross-sectional view along line AA' in FIG. 1 , illustrating the structure of a CMOS device. The CMOS semiconductor device 1 includes a semiconductor substrate with a silicon layer 12. The semiconductor substrate includes an active region 13 and an isolation region 16. The isolation region 16 surrounds the active region 13 to electrically insulate the active region. A gate structure is disposed on the active region 13 . The gate structure includes a gate insulating layer 18 , a gate electrode layer 20 , and a spacer 22 . The active region 13 may include a doped well 14 or 15 . Therefore, the channel width is the width when the gate electrode layer overlaps the active area, that is, the channel width of this conventional MOS transistor device structure is limited to the width of the active area 13 .

It is known from the above that there are many methods for improving carrier mobility. For example, FIG. etch stop layer, CESL)21. By applying stress, the channel on the semiconductor substrate is subjected to tensile or compressive strain, thereby improving the mobility. However, as far as the current technology for improving carrier mobility is concerned, the size of the channel is still limited to the size of the device made by the existing technological limit, such as the limit of lithography and etching and the shallow fabrication. The limit of trench filling in the trench isolation structure, etc.

Therefore, there is still a need for a MOS transistor device and its manufacturing method to further improve device performance compared to the prior art.

Contents of the invention

The object of the present invention is to provide a metal oxide semiconductor (MOS) transistor device, a method of manufacturing a MOS transistor device, and a method of improving a drain current of a MOS transistor device. The MOS transistor of the present invention includes an epitaxial layer located between the gate structure and the active region of the semiconductor substrate, and a peripheral portion of the epitaxial layer covers a peripheral portion of the isolation region, so that the channel width under the gate can be It is wider than the original active region width, so the drain current can be increased.

The MOS transistor device according to the present invention includes a semiconductor substrate, a gate structure, and a selective epitaxial layer. The semiconductor substrate includes an active area and an isolation area, and the isolation area surrounds the active area to electrically isolate the active area. The gate structure is disposed on the active area. The epitaxial layer is located between the active region and the gate structure, and a peripheral portion of the epitaxial layer covers a peripheral portion of the isolation region.

A method of manufacturing a MOS transistor device according to the present invention includes the following steps. Firstly, a semiconductor substrate is provided. Secondly, an isolation region is formed in the semiconductor substrate, thereby defining the isolation region and an active region, wherein the active region is adjacent to the isolation region and electrically insulated through the isolation region. Then, a selective epitaxial process is performed to form an epitaxial layer on the surface of the active region, and at the same time, the epitaxial layer grows laterally to extend to the surface of the peripheral portion of the isolation region. Then, a doping well is formed in the semiconductor substrate in the active region. A gate structure is formed on the epitaxial layer. Finally, a source/drain region is formed in the doped well and the epitaxial layer on both sides of the gate structure.

Also, the method of manufacturing a MOS transistor device according to the present invention includes the following steps. First, a semiconductor substrate is provided. Secondly, an isolation region and a doping well are formed in the semiconductor substrate, and the doping well is surrounded by the isolation region. Then, a selective epitaxial process is performed to form an epitaxial layer on the surface of the doping well, and meanwhile, the epitaxial layer grows laterally and extends to the surface of the peripheral portion of the isolation region. Then, a gate structure is formed on the epitaxial layer. Finally, a source/drain region is formed in the doped well and the epitaxial layer on both sides of the gate structure.

According to the method for improving the drain current of a MOS transistor element of the present invention, the MOS transistor element includes a semiconductor substrate and a gate structure, wherein the semiconductor substrate includes an isolation region and an active region, and the isolation region surrounds the active region to make it electrical insulation. This method includes the following steps. First, after forming the isolation region and before forming the gate structure, a selective epitaxial layer is formed on the active region, and the epitaxial layer is grown laterally to extend to the surface of the peripheral part of the isolation region, thereby increasing the MOS transistor element channel width.

Description of drawings

FIG. 1 shows a schematic top view of a conventional MOS transistor device;

Fig. 2 shows the schematic sectional view along AA ' line segment in Fig. 1;

FIG. 3 shows a schematic cross-sectional view of another existing MOS transistor element;

FIG. 4 shows a schematic top view of a specific embodiment of a MOS transistor device according to the present invention;

Fig. 5 shows the sectional schematic diagram along BB ' line segment in Fig. 4;

6 shows a schematic cross-sectional view of another embodiment of a MOS transistor device according to the present invention;

7 to 13 illustrate specific embodiments of the method for manufacturing MOS transistor elements according to the present invention;

FIG. 14 shows a flow chart of a method for manufacturing a MOS transistor device according to the present invention;

Figure 15 shows a transmission electron micrograph after the completion of the epitaxial layer in a specific embodiment of the method for manufacturing a MOS transistor element according to the present invention;

Fig. 16 shows that the current (I _on ) of the HVT PMOS transistor element made according to the method of the present invention and the existing HVT PMOS transistor element is plotted against Ldrawn;

Fig. 17 shows that the current (I _on ) of the HVT NMOS transistor element made according to the method of the present invention and the existing HVT NMOS transistor element is plotted against Ldrawn;

Fig. 18 shows the generic curve obtained by plotting the I _off of the HVT NMOS transistor element and the existing HVTNMOS transistor element according to the method _of the present invention;

Fig. 19 shows the generic curve obtained by plotting I _off versus I _on of the HVT PMOS transistor element manufactured by the method of the present invention and the existing HVT PMOS transistor element.

Description of main component symbols

1 Existing CMOS semiconductor components

10 CMOS semiconductor element of the present invention

12 Silicon layer 13 Active area

14 Doping well 15 Doping well

16 Isolation Region 17 Shallow Junction Source/Drain Extension

18 Gate insulating layer 19 Shallow junction source/drain extension

20 Gate electrode layer 21 Contact hole etch stop layer

22 Spacer 23 Contact hole etch stop layer

24 Epitaxial layer 24a Peripheral part of epitaxial layer

25 salicide layer

26, 27, 28, 29 Source/drain regions

31 Silicon oxide layer 32 Polysilicon layer

101, 102, 103, 104, 105, 112, 113 steps

Detailed ways

The MOS transistor device according to the present invention can be NMOS, PMOS, or CMOS. FIG. 4 shows a schematic top view of a plurality of MOS transistor elements according to the present invention, and FIG. 5 shows a schematic cross-sectional view along line BB' in FIG. 4 , illustrating the structure of a CMOS element. The same elements or parts are still represented by the same symbols. It should be noted that the drawings are for illustration purposes only and are not drawn to original scale. The CMOS transistor device 10 includes a semiconductor substrate. The semiconductor substrate includes an active region 13 and an isolation region 16 , the isolation region 16 surrounds the active region 13 to electrically insulate the active region 13 . A gate structure, for example including a gate insulating layer 18 , a gate electrode layer 20 , and a spacer 22 , is disposed above the active region 13 . An epitaxial layer 24 is located between the active region 13 and the gate structure, and a peripheral portion 24 a of the epitaxial layer 24 covers a peripheral portion of the isolation region 16 .

In the CMOS transistor device 10 , the semiconductor substrate generally includes a silicon layer 12 , such as a silicon substrate or a silicon-on-insulator (SOI) substrate, which is not particularly limited. The isolation region 16 can be, for example, a shallow trench isolation (STI) structure, which can include a material such as silicon oxide, so as to electrically isolate the active region 13 surrounded by it. The active region 13 may include a P-type doped well or an N-type doped well. In NMOS devices, it is a P-type doped well 14 , and in a PMOS device, it is an N-type doped well 15 . The active region 13 may further include source/drain regions 26, 27, or 28, 29, respectively located in the doped wells 14 or 15 and the epitaxial layer 24 on both sides of the gate structure. In an NMOS device, the source/drain regions 26 and 27 are N-type doped, and in a PMOS device, the source/drain regions 28 and 29 are P-type doped. The source/drain region may further include a lightly doped drain (LDD) region. The epitaxial layer 24 is located above the active region 13 and below the gate structure, that is, between the doped well 14 and the gate structure, and between the doped well 15 and the gate structure. It should be noted that the epitaxial layer 24 does not cover the entire isolation region 16 , but is selectively formed on the surface of the substrate having a crystalline structure, and only extends above a peripheral portion of the isolation region 16 with the peripheral portion 24 a.

With such a structure, it can be clearly seen from FIG. 4 that the channel width w is relatively increased compared to the channel width of the prior art with only the active region 13 as the width, so that the value of I _d is increased to achieve an improved The purpose of component performance. In PMOS devices, the epitaxial layer may include Si, SiC, or a mixture of the two, and the like. In NMOS devices, the epitaxial layer may include Si, SiGe, or a mixture of the two, and the like. The epitaxial layer can also be further lightly doped. The thickness of the epitaxial layer is not strictly limited, and can be determined according to needs, for example, it can be between 50 Ȧ and 500 Ȧ. The thicker the epitaxial layer, the wider the width of its peripheral portion extending above the peripheral portion of the isolation region. , the wider the obtained channel width will be. However, it should be noted that the peripheral portions of the epitaxial layers from adjacent MOS transistor elements on an isolation layer cannot meet and contact each other, or be too close together, so as not to affect the electrical isolation requirement between the two MOS transistor elements.

The gate structure may include a gate insulating layer 18 and a gate electrode layer 20 , the gate insulating layer may be a dielectric material such as silicon oxide, and the gate electrode layer may be a conductive material such as polysilicon material. A spacer 22 may be further included. The spacer is used to form a lightly doped extension of the source/drain region, which may remain in the structure or be removed later. The gate structure may further include an L-shaped liner (not shown) formed between the spacer, the gate electrode layer, and the semiconductor substrate.

According to the structure of the MOS transistor element of the present invention, it is characterized in that there is an epitaxial layer between the gate structure and the active region of the semiconductor substrate, and the peripheral portion of the epitaxial layer extends above the peripheral portion of the isolation region adjacent to the active region, Therefore, the channel width can be increased.

It is known that the drain current of a transistor is calculated according to the channel length (L) and width (W) produced in the process. When the transistor operates in saturation mode, the magnitude of the drain current _Id remains fixed after the channel length and width are determined, as shown in the following formula:

${\mathrm{<span\; class="notranslate">\; I</span>}}_{\mathrm{<span\; class="notranslate">\; d</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; W</span>}}{\mathrm{<span\; class="notranslate">\; L</span>}}\mathrm{<span\; class="notranslate">\; \&mu;</span>}{\mathrm{<span\; class="notranslate">\; C</span>}}_{\mathrm{<span\; class="notranslate">\; ox</span>}}\frac{{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; g</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; t</span>}}<span\; class="notranslate">\; )</span>}^{\mathrm{<span\; class="notranslate">\; 2</span>}}}{\mathrm{<span\; class="notranslate">\; 2</span>}}$

W: channel width

L: channel length

μ: Mobility

C _ox : capacitance value

V _g : Gate voltage

V _t : starting voltage

Therefore, as the channel width increases, the I _d value can be increased. The structure of the MOS transistor device according to the present invention as described above is characterized by the structure of the selective epitaxial layer, so that the channel width can be wider than that of the prior art, and therefore, the _Id value can be increased compared with the prior art. However, in the manufacture of the MOS transistor device according to the present invention, in addition to the formation of the selective epitaxial layer, existing processes can be used. The formation of the selective epitaxial layer will not have adverse effects on the original process, but can further increase the I _d value on the basis of the performance based on the original process, so as to achieve the purpose of further improving the performance of the device.

Furthermore, since the upper layer of the channel under the gate insulating layer is composed of a pure epitaxial layer, the dopant that will inevitably diffuse in the process diffuses to a relatively small concentration, which is beneficial to the reduction of the _Vt value. In this way, it is also conducive to the improvement of the I _d value.

The MOS transistor element based on this kind of structure can be applicable to the MOS transistor element of many changes, for example as shown in Figure 6, can further include a self-aligned metal silicide layer (salicide layer) 25, also can further include a contact hole etching Stop layer 23. The contact hole etch stop layer 23 can be, for example, a uniformly deposited silicon nitride capping layer, and its thickness is preferably between 30 to 2000 Ȧ.

Please refer to FIG. 7 to FIG. 13 below to further illustrate the method for manufacturing the MOS transistor device of the present invention. The MOS transistor elements may be NMOS, PMOS, or CMOS transistor elements. 7 to 13 are schematic cross-sectional views of a method for manufacturing a CMOS transistor device according to an embodiment of the present invention, wherein the same components or parts are still represented by the same symbols. It should be noted that the drawings are for illustration purposes only and are not drawn to original scale.

Please refer to FIG. 7 , first prepare a semiconductor substrate including a silicon layer 12 . An isolation region 16 is formed on the silicon layer 12. The isolation region can be, for example, a shallow trench isolation structure. The step of forming the shallow trench isolation structure may include firstly using high temperature oxidation on the silicon layer 12 to generate an oxide on the surface of the silicon layer 12. barrier layer to protect the active area. Next, a silicon nitride layer can be formed on the oxidation barrier layer through chemical vapor deposition, and then a photolithography process is performed to form a photoresist pattern on the silicon nitride layer to etch the groove. After cleaning and drying, a low pressure chemical vapor deposition is performed to fill the trenches with oxide, then chemical mechanical polishing can be performed to remove the excess oxide layer, and then the silicon nitride layer is removed with, for example, hot phosphoric acid, The silicon layer 12 is exposed. In this way, the isolation region 16 is formed, and the isolation region 16 surrounds the active region to electrically isolate the active region.

In the method of the present invention, the epitaxial layer is formed after the isolation region 16 is formed and the silicon nitride layer is removed to expose the silicon layer 12, and it can be performed before or after the formation of the doped well. It is preferable to proceed immediately after the silicon layer 12 is exposed, so as not to damage the crystal structure of the silicon layer and affect the epitaxial quality. Please refer to FIG. 8 . FIG. 8 shows that after the formation of the isolation region 16 and before the formation of the doped wells, an epitaxial layer 24 is formed on the silicon layer 12 by performing a selective epitaxial process.

In a preferred embodiment of the present invention, the gases used in the selective epitaxy process include, for example, dichlorosilane (dichlorosilane, DCS), hydrogen chloride (HCl) and hydrogen, and the process temperature is lower than 800 ° C, for example, decompression Chemical vapor deposition method for the manufacture of silicon epitaxial layers. In other embodiments of the present invention, the selective epitaxy process may also use, for example, silane (SiH ₄ ) and chlorine (Cl ₂ ) as process gases. Other methods can also be used to form the silicon epitaxial layer, such as molecular beam epitaxy or ultra-high vacuum chemical vapor deposition. In other embodiments of the present invention, epitaxial layers of silicon and germanium can also be formed, for example, dichlorosilane (SiH ₂ Cl ₂ ; DCS for short) and germane (GeH ₄ ) can be used for low-pressure chemical vapor deposition (LPCVD). The method is carried out at, for example, 500 to 800° C. and low pressure. Alternatively, silicon and carbon epitaxy can be performed using SiH ₄ and methylsilyl methane (SiH ₃ CH ₃ ) by low-pressure chemical vapor deposition (LPCVD) at, for example, 500 to 800° C. and low pressure. A low-concentration dopant can be added during the epitaxial process to form epitaxy, or a low-concentration dopant can be added by ion implantation after epitaxial growth to adjust the initial voltage (V _t ) of the MOS.

Since the epitaxial layer grows thicker layer by layer with a crystal structure, the formed crystal lattice is similar to the crystal lattice of the exposed semiconductor substrate, and the shallow trench isolation structure is an oxide structure, which is amorphous. Therefore, the epitaxial Layers do not grow on the surface of the isolation region 16 . Therefore, using the method of the present invention, the selective epitaxial process is comprehensively carried out on the semiconductor substrate, and it is enough to carry out once, without the need for segmented, and without the assistance of a pattern mask, it can be conveniently carried out on the substrate. An epitaxial layer is produced at the desired location. It is worth noting that, according to the method of the present invention, the epitaxial layer will not only grow upward on the surface of the active region, but also gradually grow laterally on the side of the thick epitaxial layer, so that the finally obtained epitaxial layer The peripheral portion of the layer extends across the surface of the peripheral portion of isolation region 16 . In this way, the width of the gate channel of the transistor can be increased to increase the amount of drain current.

After the epitaxial layer is formed, an annealing process (anneal) can be further performed to repair the defective epitaxial lattice.

Next, doping wells are fabricated to obtain the structure shown in FIG. 10 . That is, the desired P-type dopant and N-type dopant can be implanted into the silicon layer 12 by implantation using the mask to form the P-type doped well 14 or the N-type doped well 15 . Doping after the epitaxial layer 24 has been formed does not adversely affect the epitaxial layer. Alternatively, an annealing treatment is further performed to repair the defective epitaxial lattice.

In addition, it is also possible to form the doped well first and then form the epitaxial layer. As shown in FIG. 9 , after the isolation region 16 is formed, the epitaxial layer is not formed first, but doped wells 14 and 15 are firstly formed in the semiconductor substrate of the isolation region 16 . Then, referring to FIG. 10 , a selective epitaxial process is performed on the surfaces of the doped wells 14 and 15 to form the above-mentioned epitaxial layer 24 .

After the selective epitaxial layer is formed, desired elements, such as gate structures, can be fabricated on the epitaxial layer. Please refer to FIG. 11, at first, deposit a dielectric layer such as a silicon oxide layer 31 on the isolation region 16 and the epitaxial layer 24, and deposit a conductive layer such as a polysilicon layer 32 on the silicon oxide layer 31, and then use photolithography With an etching process, a gate structure is formed, which includes a silicon oxide layer as the gate insulating layer 18 and a polysilicon layer as the gate electrode layer 20 .

After the gate structure is formed, source/drain regions can be formed in the epitaxial layer and doped wells on both sides of the gate structure. For example, a light drain doping (LDD) process is performed. Referring to FIG. 13 , a shallow junction source/drain extension 17 and a shallow junction source/drain extension 19 are respectively formed in the epitaxial layer 24 and the doped wells 14 and 15 on both sides of the gate structure. Subsequently, a spacer 22 is formed on the sidewalls of the gate electrode layer 20 and the gate insulating layer 18 , and the spacer can be made of materials such as silicon nitride or silicon oxide. Before forming the spacer 22, a liner layer can be formed first, and the liner layer can be made of silicon oxide.

After the spacer 22 is formed, an ion implantation process can be further performed to implant N-type dopant species such as arsenic, antimony or phosphorus into the silicon layer 12, or implant P-type dopant species such as boron into the silicon layer 12. In layer 12, source/drain regions 26, 27 of NMOS elements and source/drain regions 28, 29 of PMOS elements are thereby formed. After the doping of the drain and the source is completed, the semiconductor substrate can generally undergo a thermal process of annealing or activating the dopant. This step is also well known in the industry and will not be described here.

A material layer such as a metal silicide layer 25 may be further formed on the gate electrode layer 20 and the exposed source/drain regions 26 , 27 , 28 , and 29 . The metal silicide layer can be formed by using a self-aligned silicide (salicide) process; for example, after forming the source/drain region, a metal layer is formed to cover it by sputtering or deposition. Above the source/drain region and the gate structure, a rapid high temperature process (RTP) is then performed to react the metal with the silicon in the gate structure and the source/drain region to form a metal silicide. The RTP temperature can be between 700°C and 1000°C.

The spacer 22 can be left in the structure or removed, and only a roughly L-shaped liner layer is left on the sidewall of the gate after removal. The liner layer does not have to be L-shaped, and a milder etching process can also be performed to slightly etch the liner layer to reduce its thickness. In other embodiments, the liner layer may be completely removed.

Further processing such as strained silicon fabrication or other semiconductor process technologies can be performed. For example, a contact etch stop layer 23, such as a uniformly deposited silicon nitride capping layer, may be formed on the semiconductor substrate. The contact hole etching stop layer 23 is first set to be deposited in a compressive stress state (for example, generally between -0.1Gpa to -3Gpa, for PMOS) or a tensile stress state (for example, generally between 0.1Gpa to -3Gpa) during deposition. 3Gpa, for NMOS), so that the channel region has a corresponding compressive strain or tensile strain in the channel direction, which can improve the mobility of carriers in the channel to increase I _d . The stress state of the contact hole etch stop layer can be performed by heat treatment, ultraviolet irradiation, plasma enhanced chemical vapor deposition, or other existing methods.

FIG. 14 shows an example of a possible flowchart of the method for manufacturing a MOS transistor device according to the present invention as described above. In short, according to the method of the present invention, firstly, a step 101 is performed on the semiconductor substrate to form an isolation region; secondly, step 102 can be performed first to form a selective epitaxial layer, and then step 103 can be performed to form a doped well, Or perform step 112 to form a doped well, and then perform step 113 to form a selective epitaxial layer; then perform step 104 to form a gate structure on the epitaxial layer; finally, perform step 105 to form a gate structure Source/drain regions are formed in the semiconductor substrate and the epitaxial layer on both sides.

According to another specific embodiment of the present invention, the epitaxial layer is formed after the doped wells are formed, and the formation order of the isolation region and the doped wells is not limited, and the step 112 can be performed first to form the doped wells, and then the step 101 to form an isolation region, and then proceed to step 113 to form a selective epitaxial layer.

Therefore, it is worth noting that, in the method for forming MOS transistor elements of the present invention, the step of forming the selective epitaxial layer must be performed after forming the isolation region and before forming the gate structure.

FIG. 15 shows a transmission electron micrograph of the completed epitaxial layer in an embodiment, which is the result of selectively forming the epitaxial layer on the semiconductor substrate in the method for manufacturing a MOS transistor device according to the present invention. This selective epitaxial growth is to use the AMAT epitaxial machine (manufactured by Applied Materials, USA), under the pressure of 15 torr, with 200 sccm of dichlorosilane (dichlorosilane (DCS)), 0.04 slm (standard liter/min) of HCl, And 30slm of H ₂ for reduced pressure chemical vapor deposition (reduced pressure chemical vapor deposition). The thickness T of the formed epitaxial layer is about 70nm, and the peripheral portion of the epitaxial layer extends above and covers the periphery of the shallow trench isolation structure (STI) adjacent to the active region, an extension distance of about 140nm.

The above-mentioned embodiment is just one example of possible ways, and there are many variations, for example, molecular beam epitaxy or ultra-high vacuum chemical vapor deposition can be used instead of reduced-pressure chemical vapor deposition, or SiH ₄ can be used instead of dichlorosilane.

Using the wafer number 24 with selective epitaxial layers and isolation regions prepared in the above specific embodiments, high-voltage P-type metal-oxide-semiconductor transistors (HVT PMOS) and HVT NMOS are manufactured, which are not selective to those of the prior art Comparing the HVT PMOS and HVT NMOS made of wafer number 12 of the epitaxial layer, the two have the same channel length, but the transistor element made of wafer number 24 has a wider channel width. Under the same channel length (Ldrawn), as shown in Figure 16, the HVT PMOS transistor element made by wafer number 24 has a higher current (I _on ), when Ldrawn is 0.07, it increases by about 28%, and when Ldrawn is 0.12, it increases by about 21%. As shown in Figure 17, the HVT NMOS transistor element manufactured by wafer number 24 has a higher current (I _on ) than the HVT NMOS transistor element manufactured by wafer number 12 under the applied voltage of 1V. When Ldrawn is 0.07, the increase About 9.6%, at an Ldrawn of 0.12, an increase of about 16%.

Figure 18 shows the off-current (I _off ) versus on-current (I _on ) plots of the HVT NMOS transistor element made by wafer number 24 and the HVT NMOS transistor element made by wafer number 12 at various channel lengths, and a generic curve is obtained (universal curve). It can be seen that under the same I _off value, the transistor element prepared according to the method of the present invention has a higher I _on value.

FIG. 19 shows the HVT PMOS transistor element manufactured by wafer number 24 and the HVT PMOS manufactured by wafer number 12. I _off is plotted against I _on at various channel lengths to obtain a universal curve. It shows that under the same I _off value, the transistor element prepared according to the method of the present invention has a higher I _on value.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the claims of the present invention shall fall within the scope of the present invention.

Claims (42)

1. A metal oxide semiconductor transistor element, comprising: a semiconductor substrate comprising an active region and an isolation region surrounding the active region to electrically insulate the active region; a gate structure disposed on the active region; and An epitaxial layer is located between the active region and the gate structure, and the peripheral portion of the epitaxial layer covers above the peripheral portion of the isolation region. 2. The metal oxide semiconductor transistor device as claimed in claim 1, wherein the epitaxial layer comprises Si or SiGe. 3. The metal oxide semiconductor transistor device as claimed in claim 1, wherein the epitaxial layer comprises Si or SiC. 4. The metal oxide semiconductor transistor device as claimed in claim 1, wherein the gate structure comprises a gate electrode layer and a gate insulating layer interposed between the gate electrode layer and the semiconductor substrate. 5. The metal-oxide-semiconductor transistor device as claimed in claim 4, wherein the gate structure further comprises spacers located on sidewalls of the gate electrode layer and the gate insulating layer. 6. The metal-oxide-semiconductor transistor device as claimed in claim 1, wherein the active region comprises a drain/source region located in the semiconductor substrate and the epitaxial layer on both sides of the gate structure. 7. The metal oxide semiconductor transistor device as claimed in claim 6, wherein the drain/source region comprises a lightly doped region and a doped region. 8. The MOS transistor device of claim 6, further comprising a contact etch stop layer covering the source/drain region. 9. The MOS transistor device as claimed in claim 6, further comprising a salicide layer on the surface of the gate electrode layer and the surface of the source/drain region. 10. The MOS transistor device as claimed in claim 1, wherein the active region comprises a doped well. 11. The MOS transistor device of claim 1, wherein the epitaxial layer includes a low concentration of dopants. 12. The MOS transistor device as claimed in claim 1, wherein the MOS transistor device is a P-type MOS transistor device or an N-type MOS transistor device. 13. The MOS transistor device as claimed in claim 1, wherein the isolation region comprises a shallow trench isolation structure. 14. A method of fabricating a metal oxide semiconductor transistor device, comprising: Provide a semiconductor substrate; forming an isolation region in the semiconductor substrate, thereby defining the isolation region and an active region, wherein the active region is adjacent to the isolation region and electrically insulated by the isolation region; performing a selective epitaxial process to form an epitaxial layer on the surface of the active region, while the epitaxial layer grows laterally to extend to the surface of the peripheral portion of the isolation region; forming doped wells in the semiconductor substrate of the active region; forming a gate structure on the epitaxial layer; and A source/drain region is formed in the doped well and the epitaxial layer on both sides of the gate structure. 15. The method of claim 14, wherein the epitaxial layer comprises Si or SiGe. 16. The method of claim 14, wherein the epitaxial layer comprises Si or SiC. 17. The method of claim 14, further comprising lightly doping the epitaxial layer. 18. The method of claim 14, further comprising annealing the epitaxial layer. 19. The method of claim 14, wherein the gate structure comprises a gate electrode layer and a gate insulating layer interposed between the gate electrode layer and the semiconductor substrate. 20. The method of claim 14, after forming the gate structure, further forming spacers on sidewalls of the gate structure. 21. The method of claim 14, wherein the isolation region comprises a shallow trench isolation structure. 22. The method of claim 14, wherein forming the drain/source region comprises forming a lightly doped region and a doped region. 23. The method of claim 14, further forming a salicide layer on the surface of the source/drain region and the surface of the gate structure. 24. The method of claim 14, further forming a contact etch stop layer on the source/drain region. 25. A method of fabricating a metal oxide semiconductor transistor device comprising: Provide a semiconductor substrate; forming an isolation region and a doped well in the semiconductor substrate, and making the doped well surrounded by the isolation region; performing a selective epitaxial process to form an epitaxial layer on the surface of the doped well, and at the same time, the epitaxial layer grows laterally to extend to the surface of the peripheral portion of the isolation region; forming a gate structure on the epitaxial layer; and A source/drain region is formed in the doped well and the epitaxial layer on both sides of the gate structure. 26. The method of claim 25, wherein the epitaxial layer comprises Si or SiGe. 27. The method of claim 25, wherein the epitaxial layer comprises Si or SiC. 28. The method of claim 25, further comprising lightly doping the epitaxial layer. 29. The method of claim 25, further comprising annealing the epitaxial layer. 30. The method of claim 25, wherein the gate structure comprises a gate electrode layer and a gate insulating layer between the gate electrode layer and the semiconductor substrate. 31. The method of claim 25, after forming the gate structure, further forming spacers on sidewalls of the gate structure. 32. The method of claim 25, wherein the isolation region comprises a shallow trench isolation structure. 33. The method of claim 25, wherein forming the drain/source region comprises forming a lightly doped region and a doped region. 34. The method of claim 25, wherein the doped well is formed after the isolation region is formed. 35. The method of claim 25, wherein the isolation region is formed after forming the doped well. 36. The method of claim 25, further forming a salicide layer on the surface of the source/drain region and the surface of the gate electrode layer. 37. The method of claim 25, further forming a contact etch stop layer on the source/drain region. 38. A method for improving the drain current of a metal oxide semiconductor transistor element, the metal oxide semiconductor transistor element comprising a semiconductor substrate and a gate structure, wherein the semiconductor substrate comprises an isolation region and an active region, and the isolation region surrounds the active region source region to electrically isolate it, the method comprising: After forming the isolation region and before forming the gate structure, a selective epitaxial layer is formed on the active region, and the epitaxial layer is grown laterally to extend to the surface of the peripheral portion of the isolation region, thereby increasing the metal The channel width of an oxide semiconductor transistor element. 39. The method of claim 38, wherein the epitaxial layer comprises Si or SiGe. 40. The method of claim 38, wherein the epitaxial layer comprises Si or SiC. 41. The method of claim 38, further comprising lightly doping the epitaxial layer. 42. The method of claim 38, further comprising annealing the epitaxial layer.

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