CN101118460A - Adaptive storage system including hard disk drive with flash interface - Google Patents

Abstract

A processing system comprises a first processor that has active and inactive states and that processes at least one thread during the active state. A second processor has active and inactive states. The second processor consumes less power when operating in the active state than the first processor operating in the active state. A control module communicates with the first and second processors and selectively transfers the at least one thread from the first processor to the second processor and selects the inactive state of the first processor. The second processor processes the at least one thread.

Description

Has the system that high power and low-power processor and thread shift

Technical field

The present invention relates to data-storage system, relate in particular to the low-power data storage system.

Background technology

Laptop computer uses line power and battery supply power supply.The processor of laptop computer, graphic process unit, storer and display consume a large amount of power during operation.A critical limitation of laptop computer relates to laptop computer can use battery operated time quantum under the situation of not charging.The corresponding usually short battery life of the higher power consumption of laptop computer.

Referring now to Figure 1A, shown exemplary computer architecture 4 comprises storer 6, and storer 6 has the storer 7 such as buffer memory.Processor 6 is communicated by letter with I/O (I/O) interface 8.Volatile memory 9 such as random-access memory (ram) 10 and/or other suitable electronic data storage device structures is also communicated by letter with interface 8.Graphic process unit 11 and the storer such as buffer memory 12 have increased the speed and the performance of graphics process.

Communicate by letter with interface 8 with the one or more I/O equipment the pointing device 14 (for example mouse and/or other suitable device) such as keyboard 13.Such as having one or more diameters greater than 1.8 " the hard disk drive of disc high power disk drive (HPDD) 15 nonvolatile memory, storage data be provided and communicate by letter with interface 8.HPDD15 generally consumes relatively large power during operation.When using when battery operated, the frequent use of HPDD15 will reduce battery life greatly.Computer Architecture 4 also comprises display 16, such as the audio output apparatus 17 of audio tweeter and/or usually be designated other input-output apparatus of 18.

Referring now to Figure 1B, exemplary Computer Architecture 20 comprises process chip group 22 and I/O chipset 24.For example, Computer Architecture can be northbridge/southbridge architecture (the process chip group is corresponding to north bridge chipset, and the I/O chipset is corresponding to the South Bridge chip group) or other similar architecture.Process chip group 22 is communicated by letter with graphic process unit 26 with processor 25 via system bus 27.22 controls of process chip group are mutual with volatile memory 28 (for example outside DRAM or other storeies), periphery component interconnection (PCI) bus 30 and/or level 2 cache memory 32.1 grade of buffer memory 33 and 34 can be associated with processor 25 and/or graphic process unit 26 respectively.In the embodiment that replaces, Accelerated Graphics Port (AGP) (not shown) is communicated by letter with process chip group 22 rather than graphic process unit 26, perhaps except with also communicate by letter graphic process unit 26 is communicated by letter with process chip group 22.Process chip group 22 generally realizes with a plurality of chips, but is not to realize with a plurality of chips.PCI groove 36 is connected with pci bus 30.

The citation form of I/O chipset 24 management I/O (I/O).I/O chipset 24 is communicated by letter with USB (universal serial bus) (USB) 40, audio frequency apparatus 41, keyboard (KBD) and/or pointing device 42 and basic input/output (BIOS) 43 via ISA(Industry Standard Architecture) bus 44.Different with process chip group 22 is, I/O chipset 24 general (but be not must) is with single chip realization, and it is connected to pci bus 30.HPDD50 such as hard disk drive also communicates by letter with I/O chipset 24.Full feature (full-featured) operating system (OS) that the HPDD50 storage is carried out by processor 25, for example Windows XP ^, Windows 2000 ^, Linux and based on MAC ^OS.

Summary of the invention

A kind of SOC (system on a chip) (SOC), comprise first processor of realizing by described SOC and second processor of realizing by described SOC, this first processor has movable and inactive state and first and second groups of threads of processing during active state, this second processor has activity and inactive state, and wherein second processor works in active state consumption power still less than first processor when working in active state.Described SOC also comprises the control module that is realized by described SOC, this control module and first and second processor communications, and optionally second group of thread transferred to second processor and selected the inactive state of first processor from first processor.Second group of thread of second processor processing.

In another feature, described SOC also comprises the register file that is realized by described SOC, and this register file and first processor and second processor communication and storage are used for the thread information of first and second processors.Described thread information comprises register, checkpoint and programmable counter at least a of the thread that is used for first and second processors.

In another feature, described SOC also comprises first register file and second register file, this first register file is communicated by letter with first processor and is stored the first thread information that is used for first processor, and this second register file and second processor communication and storage are used for the second thread information of second processor.The first and second thread information comprise register, checkpoint and programmable counter at least a of the thread that is used for first and second processors respectively.

In another feature, described control module with thread when first processor is transferred to second processor, thread information is transferred to second register file from first register file.

In another feature, described first processor comprises the first transistor, and described second processor comprises transistor seconds, and wherein the first transistor has higher leakage current than transistor seconds.

In another feature, described first processor comprises the first transistor, and described second processor comprises transistor seconds, and wherein transistor seconds has bigger size than the first transistor.

In another feature, described SOC is in high-power mode when first processor is in active state, is in low-power mode when first processor is inactive.

In another feature, described first and second processors comprise first and second Graphics Processing Unit respectively.

In other features, a kind of method that is used for deal with data is included in SOC (system on a chip) (SOC) and goes up realization first and second processors, wherein said first and second processors have activity and inactive state, and second processor works in active state consumption power still less than first processor when working in active state.Described method also comprises uses first processor to handle first and second groups of threads during active state; Optionally second group of thread transferred to second processor from first processor; Select the inactive state of first processor; And use second group of thread of second processor processing.

In another feature, described method comprises that also the thread information stores of using described SOC realization register file and will being used for first and second processors is in register file.Thread information comprises register, checkpoint and programmable counter at least a of the thread that is used for first and second processors.

In another feature, described method also comprise the first thread information stores using described SOC to realize first register file, will be used for first processor in first register file, use described SOC to realize that second register file and storage are used for the second thread information of second processor.The first and second thread information comprise register, checkpoint and programmable counter at least a of the thread that is used for first and second processors respectively.

In another feature, described method also is included in transfers to second register file with thread information from first register file with thread when first processor is transferred to second processor.

In another feature, described first processor comprises the first transistor, and described second processor comprises transistor seconds, and wherein the first transistor has higher leakage current than transistor seconds.

In another feature, described first processor comprises the first transistor, and described second processor comprises transistor seconds, and wherein transistor seconds has bigger size than the first transistor.

In another feature, described method also comprises and working in when first processor is in active state under the high-power mode, works under the low-power mode when first processor is inactive.

In another feature, described first and second processors comprise first and second Graphics Processing Unit respectively.

In other features, a kind of SOC (system on a chip) (SOC) comprises first treating apparatus, and this first treating apparatus is realized by described SOC and had activity and inactive state, is used for handling during active state first and second groups of threads.Described SOC also comprises second treating apparatus that is used to handle, this second treating apparatus is realized by described SOC and has activity and inactive state that wherein second treating apparatus works in active state consumption power still less than first treating apparatus when working in active state.Described SOC also comprises control device, this control device is realized by described SOC, be used for communicating by letter, and be used for optionally second group of thread being transferred to from first treating apparatus inactive state of second treating apparatus and selection first treating apparatus with first and second treating apparatus.Second treating apparatus is handled second group of thread.

In another feature, described SOC also comprises register setting, and this register setting is realized by described SOC and communicated by letter with second treating apparatus with first treating apparatus, is used to store the thread information that is used for first and second treating apparatus.Thread information comprises register, checkpoint and programmable counter at least a of the thread that is used for first and second treating apparatus.

In another feature, described SOC also comprises first register setting and second register setting, this first register setting is communicated by letter with first treating apparatus, be used to store the first thread information that is used for first treating apparatus, this second register setting is communicated by letter with second treating apparatus, is used to store the second thread information that is used for second treating apparatus.The first and second thread information comprise register, checkpoint and programmable counter at least a of the thread that is used for first and second treating apparatus respectively.

In another feature, described control device is being transferred to second register setting with thread information from first register setting with thread when first treating apparatus is transferred to second treating apparatus.

In another feature, described first treating apparatus comprises the first transistor, and described second treating apparatus comprises transistor seconds, and wherein the first transistor has higher leakage current than transistor seconds.

In another feature, described first treating apparatus comprises the first transistor, and described second treating apparatus comprises transistor seconds, and wherein transistor seconds has bigger size than the first transistor.

In another feature, described SOC is in high-power mode when first treating apparatus is in active state, is in low-power mode when first treating apparatus is inactive.

In another feature, described first and second treating apparatus comprise first and second graphic processing facilities that are used for processing graphics respectively.

In other features, a kind of disposal system comprises the first processor and second processor, this first processor has movable and inactive state and at least one thread of processing during active state, this second processor has activity and inactive state, and wherein second processor works in active state consumption power still less than first processor when working in active state.Described disposal system also comprises control module, this control module and first and second processor communications, and optionally described at least one thread is transferred to second processor and selected the inactive state of first processor from first processor.Described at least one thread of second processor processing.

In another feature, described disposal system also comprises the register file that is realized by described SOC, this register file and first processor and second processor communication and storage are used for the thread information of first and second processors, and wherein said thread information comprises register, checkpoint and programmable counter at least a of the thread that is used for first and second processors.

In another feature, a kind of SOC (system on a chip) (SOC) comprises first and second processors and register file.

In another feature, described disposal system also comprises first register file and second register file, this first register file is communicated by letter with first processor and is stored the first thread information that is used for first processor, this second register file and second processor communication and storage are used for the second thread information of second processor, and wherein the first and second thread information comprise register, checkpoint and programmable counter at least a of the thread that is used for first and second processors respectively.

In another feature, a kind of SOC (system on a chip) (SOC) comprises first and second processors and first and second register files.

In another feature, described control module with thread when first processor is transferred to second processor, thread information is transferred to second register file from first register file.

In another feature, described first processor comprises the first transistor, and described second processor comprises transistor seconds, and wherein the first transistor has higher leakage current than transistor seconds.

In another feature, described first processor comprises the first transistor, and described second processor comprises transistor seconds, and wherein transistor seconds has bigger size than the first transistor.

In another feature, described disposal system is in high-power mode when first processor is in active state, is in low-power mode when first processor is inactive.

In another feature, described first and second processors comprise first and second Graphics Processing Unit respectively.

In other features, a kind of method of deal with data comprises provides first and second processors, wherein said first and second processors have activity and inactive state, and second processor works in active state consumption power still less than first processor when working in active state.Described method also comprises uses first processor to handle at least one thread during active state, optionally described at least one thread is transferred to second processor and selected the inactive state of first processor and use described at least one thread of second processor processing from first processor.

In another feature, described method also comprises the thread information stores of using described SOC to realize register file and will being used for first and second processors in register file, and wherein said thread information comprises register, checkpoint and programmable counter at least a of the thread that is used for first and second processors.

In another feature, described method also is included in and realizes register file, first processor and second processor in the SOC (system on a chip).

In another feature, described method also comprise the first thread information stores using described SOC to realize first register file, will be used for first processor in first register file, use described SOC to realize that second register file and storage are used for the second thread information of second processor, the wherein said first and second thread information comprise register, checkpoint and programmable counter at least a of the thread that is used for first and second processors respectively.

In another feature, described method also is included in and realizes first and second register files and first and second processors in the SOC (system on a chip).

In another feature, described method also is included in transfers to second register file with thread information from first register file with thread when first processor is transferred to second processor.

In another feature, described first processor comprises the first transistor, and described second processor comprises transistor seconds, and wherein the first transistor has higher leakage current than transistor seconds.

In another feature, described first processor comprises the first transistor, and described second processor comprises transistor seconds, and wherein transistor seconds has bigger size than the first transistor.

In another feature, described method also comprises and working in when first processor is in active state under the high-power mode, works under the low-power mode when first processor is inactive.

In another feature, described first and second processors comprise first and second Graphics Processing Unit respectively.

In other features, a kind of disposal system comprises first treating apparatus and second treating apparatus that is used to handle, this first treating apparatus has activity and inactive state, be used for during active state, handling at least one thread, this second treating apparatus has activity and inactive state, and wherein said second treating apparatus works in active state consumption power still less than first treating apparatus when working in active state.Described disposal system also comprises control device, this control device is used for communicating by letter with first and second treating apparatus, and be used for optionally described at least one thread being transferred to second treating apparatus and the inactive state of selecting first treating apparatus from first treating apparatus, wherein second treating apparatus is handled described at least one thread.

In another feature, described disposal system also comprises register setting, this register setting is realized by described SOC and is communicated by letter with second treating apparatus with first treating apparatus, be used to store the thread information that is used for first and second treating apparatus, wherein said thread information comprises register, checkpoint and programmable counter at least a of the thread that is used for first and second treating apparatus.

In another feature, described register setting and described first and second treating apparatus are implemented in the SOC (system on a chip).

In another feature, described disposal system also comprises first register setting and second register setting, this first register setting is communicated by letter with first treating apparatus, be used to store the first thread information that is used for first treating apparatus, this second register setting is communicated by letter with second treating apparatus, be used to store the second thread information that is used for second treating apparatus, the wherein said first and second thread information comprise register, checkpoint and programmable counter at least a of the thread that is used for first and second treating apparatus respectively.

In another feature, described first and second register settings and described first and second treating apparatus are implemented in the SOC (system on a chip).

In another feature, described control device is being transferred to second register setting with thread information from first register setting with thread when first treating apparatus is transferred to second treating apparatus.

In another feature, described first treating apparatus comprises the first transistor, and described second treating apparatus comprises transistor seconds, and wherein the first transistor has higher leakage current than transistor seconds.

In another feature, described first treating apparatus comprises the first transistor, and described second treating apparatus comprises transistor seconds, and wherein transistor seconds has bigger size than the first transistor.

In another feature, described disposal system works in when first treating apparatus is in active state under the high-power mode, works under the low-power mode when first treating apparatus is inactive.

In another feature, described first and second treating apparatus comprise first and second graphic processing facilities that are used for processing graphics respectively.

Further adaptability of the present invention field will become clear from the following detailed description that provides.Though should recognize and describe in detail and concrete example indication the preferred embodiments of the present invention, wish it is to be used for illustrative purposes, be not intended to limit the scope of the invention.

Description of drawings

The present invention will be understood from the detailed description and the accompanying drawings more fully, wherein:

Figure 1A and Figure 1B show the exemplary computer architecture according to prior art;

Fig. 2 A shows according to first exemplary computer architecture of the present invention, and this Computer Architecture is included in primary processor, main graphic processor and the main volatile memory of working during the high-power mode and communicates by letter with primary processor, working during the low-power mode and adopt the second processor and the inferior graphic process unit of main volatile memory during low-power mode;

Fig. 2 B shows according to second exemplary computer architecture of the present invention, this Computer Architecture and Fig. 2 category-A like and comprise the inferior volatile memory that is connected to second processor and/or inferior graphic process unit;

Fig. 2 C shows according to the 3rd exemplary computer architecture of the present invention, this Computer Architecture and Fig. 2 category-A like and comprise the embedded volatile memory that is associated with second processor and/or inferior graphic process unit;

Fig. 3 A shows according to the 4th example architecture of the present invention, and this architecture is used to have in the primary processor of working during the high-power mode, main graphic processor and main volatile memory and with the process chip group communication, is working during the low-power mode and adopt the second processor of main volatile memory and the computing machine of inferior graphic process unit during low-power mode;

Fig. 3 B shows according to the 5th exemplary computer architecture of the present invention, this Computer Architecture and Fig. 3 category-A like and comprise the inferior volatile memory that is connected to second processor and/or inferior graphic process unit;

Fig. 3 C shows according to the 6th exemplary computer architecture of the present invention, this Computer Architecture and Fig. 3 category-A like and comprise the embedded volatile memory that is associated with second processor and/or inferior graphic process unit;

Fig. 4 A shows according to the 7th example architecture of the present invention, and this architecture is used to have with the I/O chipset communicates by letter, working during the low-power mode and adopt the second processor of main volatile memory and the computing machine of inferior graphic process unit during low-power mode;

Fig. 4 B shows according to the 8th exemplary computer architecture of the present invention, this Computer Architecture and Fig. 4 category-A like and comprise the inferior volatile memory that is connected to second processor and/or inferior graphic process unit;

Fig. 4 C shows according to the 9th exemplary computer architecture of the present invention, this Computer Architecture and Fig. 4 category-A like and comprise the embedded volatile memory that is associated with second processor and/or inferior graphic process unit;

Fig. 5 shows the buffer memory grade according to the Computer Architecture of the Fig. 2 of being used for A-4C of the present invention;

Fig. 6 is the functional block diagram that comprises the drive control module of data storage between minimum use piece (LUB) module and managing low-power disk drive (LPDD) and the high power disk drive (HPDD) and transfer;

Fig. 7 A shows the process flow diagram by the performed step of the drive control module of Fig. 6;

Fig. 7 B shows the process flow diagram by the performed alternative step of the drive control module of Fig. 6;

Fig. 7 C and Fig. 7 D show the process flow diagram by the performed alternative step of the drive control module of Fig. 6;

Fig. 8 A shows the data storage that comprises between adaptability storage control module and control LPDD and the HPDD and the buffer memory control module of transfer;

Fig. 8 B shows the data storage that comprises between adaptability storage control module and control LPDD and the HPDD and the operating system of transfer;

Fig. 8 C shows the data storage that comprises between adaptability storage control module and control LPDD and the HPDD and the host computer control module of transfer;

Fig. 9 shows by the performed step of the adaptability storage control module of Fig. 8 A-8C;

To be that explanation is a kind of be used for determining program or the file exemplary table with the method for the possibility that is used during low-power mode to Figure 10;

Figure 11 A shows and comprises that the dish driving power reduces the buffer memory control module of module;

Figure 11 B shows and comprises that the dish driving power reduces the operating system of module;

Figure 11 C shows and comprises that the dish driving power reduces the host computer control module of module;

The dish driving power that Figure 12 shows by Figure 11 A-11C reduces the performed step of module;

Figure 13 shows the polydisc drive system that comprises high power disk drive (HPDD) and low-power disk drive (LPDD);

Figure 14-17 shows other exemplary implementations of the polydisc drive system of Figure 13;

Figure 18 shows the use of the low power non-volatile memory such as flash memory or low-power disk drive (LPDD) of the virtual memory that is used to increase computing machine;

Figure 19 and Figure 20 show distribution of being carried out by operating system and the step of using the virtual memory of Figure 18;

Figure 21 is the functional block diagram of redundant array of independent disks (RAID) system according to prior art;

Figure 22 A is that this RAID system has the disk array that comprises X HPDD and comprises the disk array of Y LPDD according to the functional block diagram of exemplary RAID of the present invention system;

Figure 22 B is the functional block diagram of the RAID system of Figure 22 A, and wherein X and Y equal Z;

Figure 23 A is that this RAID system has the disk array that comprises Y LPDD according to the functional block diagram of another exemplary RAID system of the present invention, comprises that the disk array of Y LPDD communicates by letter with the disk array that comprises X HPDD;

Figure 23 B is the functional block diagram of the RAID system of Figure 23 A, and wherein X and Y equal Z;

Figure 24 A is that this RAID system has the disk array that comprises X HPDD according to the functional block diagram of another exemplary RAID system of the present invention, comprises that the disk array of X HPDD communicates by letter with the disk array that comprises Y LPDD;

Figure 24 B is the functional block diagram of the RAID system of Figure 24 A, and wherein X and Y equal Z;

Figure 25 is the functional block diagram of network attached storage (NAS) system according to prior art;

Figure 26 is the functional block diagram according to network attached storage of the present invention (NAS) system, and this network attached storage system comprises the RAID system of Figure 22 A, 22B, 23A, 23B, 24A and/or 24B and/or according to the multi-drive system of Fig. 6-17;

Figure 27 is the functional block diagram that comprises the disc drive controller of flash memory and disc drive interface controller;

Figure 28 is the functional block diagram of the interface controller of Figure 27;

Figure 29 is the functional block diagram with polydisc drive system of flash interface;

Figure 30 shows the process flow diagram by the performed step of the multiple disk file of Figure 30;

Figure 31 A-31C is the functional block diagram that comprises the disposal system of high power and low-power processor, when these processors are changed between high power and low-power mode processing threads is transferred to each other;

Figure 32 A-32C is the functional block diagram that comprises the graphic system of high power and low-power Graphics Processing Unit (GPU), when these Graphics Processing Unit are changed between high power and low-power mode the graphics process thread is transferred to each other;

Figure 33 is the process flow diagram of the disposal system operation of key diagram 31A-32C;

Figure 34 A is the functional block diagram of hard disk drive;

Figure 34 B is the functional block diagram of DVD driver;

Figure 34 C is the functional block diagram of high-definition television;

Figure 34 D is the functional block diagram of vehicle control system;

Figure 34 E is cellular functional block diagram;

Figure 34 F is the functional block diagram of set-top box; And

Figure 34 G is the functional block diagram of media player.

Embodiment

The following description of (one or more) preferred embodiment in fact only is exemplary, never wishes restriction the present invention and application or use.For the sake of clarity, will use identical label to identify similar elements in the accompanying drawings.Here employed term module and/or device refer to processor (shared processing device, application specific processor or processor group) and storer, the combinational logic circuit of special IC (ASIC), electronic circuit, the one or more softwares of execution or firmware program and/or other suitable assemblies of described function are provided.

Here employed term " high-power mode " refers to activity (active) operation of the host-processor and/or the main graphic processor of main process equipment.Term " low-power mode " refers to the low power sleep mode, " shut " mode" of when second processor and time graphic process unit can be operated primary processor and/or main graphic processor and/or response modes not." " shut " mode" " refers to primary processor and the second processor situation when all closing.

Term " low-power disk drive " or LPDD refer to have one or more diameters and is less than or equal to 1.8 " the disk drive and/or the microdrive of disc.Term " high power disk drive " or HPDD refer to has one or more diameters greater than 1.8 " the hard disk drive of disc.LPDD generally has lower memory capacity and consumption power still less than HPDD.LPDD is also with the speed rotation higher than HPDD.For example, LPDD can reach 10,000-20,000RPM or higher rotating speed.

The HDD that term has non-volatile memory interface (IF) refers to the hard disk drive that can be connected to main process equipment via the standard semiconductor memory interface of main frame.For example, the semiconductor memory interface can be a flash interface.

HDD with nonvolatile memory IF uses the non-volatile memory interface agreement via non-volatile memory interface and main-machine communication.Main frame and the employed non-volatile memory interface of HDD with non-volatile memory interface can comprise the semiconductor memory interface of the flash memory with flash interface, the nand flash memory with nand flash memory interface or any other type.HDD with nonvolatile memory IF can be LPDD and/or HPDD.To further describe HDD in conjunction with Figure 27 and Figure 28 below with nonvolatile memory IF.Relate to the U.S. Patent application No.11/322 that the other details of the HDD operation with flash memory IF can be submitted on Dec 29th, 2005, find in 447, by reference the whole of this application are herein incorporated.In described below each implementation, LPDD can realize with the HDD with nonvolatile memory IF (being implemented as HPDD and/or LPDD).Perhaps, the HDD with nonvolatile memory IF can be LPDD and/or the HPDD that is used except disclosed LPDD and/or HPDD.

Computer Architecture according to the present invention is included in primary processor, main graphic processor and the primary memory (as the description in conjunction with Figure 1A and Figure 1B) of working during the high-power mode.Second processor and time graphic process unit are worked during low-power mode.As described below, second processor and time graphic process unit can be connected to the various assemblies of computing machine.Main volatile memory can be used by second processor and time graphic process unit during low-power mode.Perhaps, as described below, can use inferior volatile memory such as DRAM and/or embedded volatile memory such as embedded DRAM.

When working, primary processor and main graphic processor consume higher power under high-power mode.Primary processor and main graphic processor are carried out full feature (full-featured) operating system (OS) that needs relatively large external memory storage.Primary processor and main graphic processor are supported high performance operation, comprise complicated calculations and advanced figure.Full feature OS can be such as Windows XP ^And so on based on Windows ^OS, based on the OS of Linux, based on MAC ^OS etc.Full feature OS is stored in HPDD15 and/or 50.

Second processor consumes less power (comparing with the main graphic processor with primary processor) with time graphic process unit during low-power mode.Second processor and time graphic process unit operation need the limited feature operating system (OS) of a small amount of external volatile memory.Second processor also can use identical OS with primary processor with time graphic process unit.For example, can use the reduction version of full feature OS.Second processor and time graphic process unit are supported the operation of lower-performance, lower computation rate and so not senior figure.For example, limited feature OS can be Windows CE ^Or any other suitable limited feature OS.Limited feature OS preferably is stored in the nonvolatile memory such as flash memory, the HDD with nonvolatile memory IF, HPDD and/or LPDD.In a preferred embodiment, full feature OS and limited feature OS share a shared data form to reduce complicacy.

Primary processor and/or main graphic processor preferably include and use the transistor that manufacturing process realized with less characteristic dimension.In an implementation, these transistors are realized with the advanced CMOS manufacturing process.The transistor of being realized in primary processor and/or main graphic processor has higher standby leakage, short raceway groove and at a high speed and design size.It mainly is dynamic logic that primary processor and main graphic processor preferably adopt.In other words, they can not be closed.Though can use other dutycycle, transistor is with less than about 20% and preferably be switched less than about 10% dutycycle.

On the contrary, second processor and/or inferior graphic process unit preferably include with the transistor that a kind of manufacturing process realized like this, and this manufacturing process has bigger characteristic dimension than the technology that is used for primary processor and/or main graphic processor.In an implementation, these transistors are realized with the CMOS manufacturing process of rule.The transistor of being realized in second processor and/or inferior graphic process unit has lower standby leakage, long raceway groove and at low-power consumption and design size.It mainly is static logic that second processor and time graphic process unit preferably adopt, rather than dynamic logic.Though can use other dutycycle, transistor is with greater than 80% and be preferably more than 90% dutycycle and be switched.

When working, primary processor and main graphic processor consume higher power under high-power mode.Second processor and time graphic process unit consume less power when working under low-power mode.Yet, under low-power mode, can support still less feature and calculating and so not complicated figure when Computer Architecture is worked than under high-power mode.Those skilled in the art can know that Computer Architecture according to the present invention has a variety of implementation methods.Therefore, those skilled in the art will know that below in conjunction with the described architecture of Fig. 2 A-4C in fact only be exemplary, rather than restrictive.

Referring now to Fig. 2 A, show first exemplary computer architecture 60.Primary processor 6, volatile memory 9 and main graphic processor 11 are communicated by letter with interface 8 and support complicated data and graphics process during high-power modes.Second processor 62 is communicated by letter with interface 8 with time graphic process unit 64 and support so not complicated data and graphics process during low-power mode.Optionally nonvolatile memory 65 for example is LPDD66 and/or flash memory and/or the HDD69 with nonvolatile memory IF, and it is communicated by letter with interface 8 and provides the low power non-volatile of data to store during low-power mode and/or high-power mode.HDD with nonvolatile memory IF can be LPDD and/or HPDD.HPDD15 provides high power/capacity nonvolatile memory.Nonvolatile memory 65 and/or HPDD15 are used to store limited feature OS and/or other data and file during low-power mode.

In this embodiment, second processor 62 and time graphic process unit 64 duration of work under low-power mode adopts volatile memory 9 (or primary memory).For this reason, at least a portion of interface 8 is being powered during the low-power mode with the communication between components of communicating by letter and/or low-power mode during being powered of support with primary memory.For example, keyboard 13, pointing device 14 and basic display unit 16 can be powered during low-power mode and use.In described all embodiment in conjunction with Fig. 2 A-4C, inferior display (for example monochrome display) and/or inferior input-output apparatus with ability of reduction also can be provided during low-power mode and use.

Referring now to Fig. 2 B, show second exemplary computer architecture 70 of the architecture that is similar among Fig. 2 A.In this embodiment, second processor 62 is communicated by letter with time volatile memory 74 and/or 76 with time graphic process unit 64.Inferior volatile memory 74 and 76 can be DRAM or other suitable storeies.During low-power mode, second processor 62 and time graphic process unit 64 except utilize shown in Fig. 2 A and described main volatile memory 9 also utilize time volatile memory 74 and/or 76 respectively, perhaps utilize respectively time volatile memory 74 and/or 76 rather than Fig. 2 A shown in and described main volatile memory 9.

Referring now to Fig. 2 C, show the 3rd exemplary computer architecture 80 that is similar to Fig. 2 A.Second processor 62 and/or inferior graphic process unit 64 comprise embedded volatile memory 84 and 86 respectively.During low-power mode, second processor 62 and time graphic process unit 64 are also utilized embedded volatile memory 84 and/or 86 respectively except utilizing main volatile memory, perhaps utilize embedded volatile memory 84 and/or 86 rather than main volatile memory respectively.In one embodiment, though can use the embedded volatile memory of other types, embedded volatile memory 84 and 86 is embedded DRAM (eDRAM).

Referring now to Fig. 3 A, show according to the 4th exemplary computer architecture 100 of the present invention.Primary processor 25, main graphic processor 26 and main volatile memory 28 are communicated by letter with process chip group 22 and support complicated data and graphics process during high-power modes.Second processor 104 and time graphic process unit 108 are in low-power mode support of following time so not complicated data and graphics process at computing machine.Adopt main volatile memory 28 when in this embodiment, second processor 104 and time graphic process unit 108 are worked under low-power mode.For this reason, process chip group 22 can powered entirely during the low-power mode and/or partly powered to assist the communication between them.HPDD50 can be powered during low-power mode so that the high power volatile memory to be provided.Low power non-volatile memory 109 (LPDD110 and/or flash memory and/or have the HDD113 of nonvolatile memory IF) is connected to process chip group 22, I/O chipset 24 or in the another location, and storage is used for the limited feature operating system of low-power mode.HDD with nonvolatile memory IF can be LPDD and/or HPDD.

Process chip group 22 can be powered entirely and/or part is powered to support the operation of HPDD50, LPDD110 and/or other assemblies that will use during low-power mode.For example, during low-power mode, can use keyboard and/or pointing device 42 and basic display unit.

Referring now to Fig. 3 B, show the 5th exemplary computer architecture 150 that is similar to Fig. 3 A.Inferior volatile memory 154 and 158 is connected respectively to second processor 104 and/or inferior graphic process unit 108.During low-power mode, second processor 104 and time graphic process unit 108 are utilized time volatile memory 154 and 158 rather than main volatile memory 28 respectively, perhaps also utilize inferior volatile memory 154 and 158 except utilizing main volatile memory 28 respectively.Process chip group 22 and main volatile memory 28 then can be closed during low-power mode if desired.Inferior volatile memory 154 and 158 can be DRAM or other suitable storeies.

Referring now to Fig. 3 C, show the 6th exemplary computer architecture 170 that is similar to Fig. 3 A.Second processor 104 and/or inferior graphic process unit 108 comprise in- line memory 174 and 176 respectively.During low-power mode, second processor 104 and time graphic process unit 108 are utilized in- line memory 174 and 176 rather than main volatile memory 28 respectively, perhaps also utilize in- line memory 174 and 176 except main volatile memory 28 respectively.In one embodiment, though can use the in-line memory of other types, embedded volatile memory 174 and 176 is embedded DRAM (eDRAM).

Referring now to Fig. 4 A, show according to the 7th exemplary computer architecture 190 of the present invention.Second processor 104 communicate by letter with I/O chipset 24 with time graphic process unit 108 and during low-power mode the main volatile memory of employing 28 as volatile memory.During low-power mode, process chip group 22 keeps being powered entirely and/or part is powered to allow the access to main volatile memory 28.

Referring now to Fig. 4 B, show the 8th exemplary computer architecture 200 that is similar to Fig. 4 A.Inferior volatile memory 154 and 158 is connected respectively to second processor 104 and time graphic process unit 108, during low-power mode, use time volatile memory 154 and 158 rather than main volatile memory 28, perhaps except using main volatile memory 28, also use time volatile memory 154 and 158.Process chip group 22 and main volatile memory 28 can be closed during low-power mode.

Referring now to Fig. 4 C, show the 9th exemplary computer architecture 210 that is similar to Fig. 4 A.Except main volatile memory 28, be respectively second processor 104 and/or inferior graphic process unit 108 embedded volatile memory 174 and 176 are provided, perhaps be respectively second processor 104 and/or inferior graphic process unit 108 embedded volatile memory 174 and 176 rather than main volatile memory 28 are provided.In this embodiment, process chip group 22 and main volatile memory 28 can be closed during low-power mode.

Referring now to Fig. 5, show the buffer memory grade 250 that is used for the Computer Architecture shown in Fig. 2 A-4C.HP nonvolatile memory HPDD50 is positioned at lowermost layer 254 places of buffer memory grade 250.If HPDD50 is disabled, then during low-power mode, can use and also can not use layer 254, and if during low-power mode HPDD50 be enabled, then will use layers 254.Such as LPDD110, flash memory and/or the LP non volatile memory bits of HDD113 with nonvolatile memory IF in last layer 258 places of buffer memory grade 250.Depending on configuration, is the last layer 262 of buffer memory grade 250 such as the external volatile memory of main volatile memory, inferior volatile memory and/or inferior in-line memory.2 grades or inferior buffer memory comprise the last layer 266 of buffer memory grade 250.1 grade of last layer 268 that buffer memory is a buffer memory grade 250.CPU (host CPU and/or inferior CPU) is the final layer 270 of buffer memory grade.Main graphic processor and time graphic process unit are used similar grade.

Computer Architecture according to the present invention provides a kind of low-power mode, processing and figure that this pattern support is so not complicated.Therefore, the power consumption of computing machine can be greatly diminished.For application on knee, battery life is extended.

Referring now to Fig. 6, the drive control module 300 or the host computer control module that are used for the polydisc drive system comprise minimum use piece (LUB) module 304, adaptability memory module 306 and/or LPDD maintenance module 308.Drive control module 300 is based in part on LUB information, the storage of control data and such as the high power disk drive (HPDD) 310 of hard disk drive and such as the transfer between the low-power disk drive (LPDD) 312 of microdrive.Drive control module 300 reduces power consumption in storage and the transfer between HPDD and LPDD by management data during high-power mode and the low-power mode.As shown in Figure 6, the HDD317 with nonvolatile memory IF can be used as LPDD, and/or can also use the HDD317 with nonvolatile memory IF except LPDD.Drive control module 300 is communicated by letter with the HDD317 with nonvolatile memory IF with main frame 313 via main frame nonvolatile memory IF315.Drive control module 300 can be integrated with main frame 313 and/or main frame nonvolatile memory IF315.

The minimum use data block that minimum use piece module 304 is followed the tracks of among the LPDD312.During low-power mode, the minimum use piece of data (for example file and/or program) among the minimum use piece module 304 identification LPDD312 is so that can replace it when needing.Some data block or file can be exempted the monitoring of minimum use piece, for example only relate to limited feature operating system file, manually be set at the piece that is stored among the LPDD312 and/or only operated alternative document and program during low-power mode.As described below, can also use other standards to select the data block that will be written.

During the data storage request of low-power mode, adaptability memory module 306 determines whether write data more may be used before minimum use piece.Adaptability memory module 306 determines also whether read data may only be used once during the data retrieval request of low-power mode.LPDD maintenance module 308 is during the high-power mode and/or under other situations as described below legacy data is transferred to HPDD from LPDD.

Referring now to Fig. 7 A, show by the performed step of drive control module 300.Control starts from step 320.In step 324, drive control module 300 determines whether to exist data storage request.If the judged result of step 324 is true, then drive control module 300 determines whether there are enough free spaces on the LPDD312 in step 328.If there are not enough free spaces, then drive control module 300 is the HPDD310 power supply in step 330.In step 334, drive control module 300 is transferred to HPDD310 with minimum use data block.In step 336, drive control module 300 determines whether there are enough free spaces on the LPDD312.If there are not enough free spaces, then Control Circulation is to step 334.Otherwise drive control module 300 continues step 340 and turns off HPDD310.In step 344, the data that will store (for example from main frame) are transferred to LPDD312.

If the judged result of step 324 is false, then drive control module 300 continues step 350 and determines whether to exist data retrieval request.If there is not data retrieval request, then step 324 is returned in control.Otherwise control continues step 354 and whether specified data is arranged in LPDD312.If the judged result of step 354 is true, then drive control module 300 is fetched data and is continued step 324 from LPDD312 in step 356.Otherwise drive control module 300 is the HPDD310 power supply in step 360.In step 364, drive control module 300 determines whether exist enough free spaces to be used for the data of being asked on the LPDD.If there are not enough free spaces, then drive control module 300 is transferred to minimum use data block HPDD310 and is continued step 364 in step 366.When the judged result of step 364 is a true time, drive control module 300 is transferred to data LPDD312 and is fetched data from LPDD312 in step 368.In step 370, when data when the transfer of LPDD312 is finished, HPDD310 is turned off in control.

Referring now to Fig. 7 B, use method after the modification be similar to Fig. 7 A, this method comprises by the performed one or more adaptability steps of adaptability memory module 306.When determining not have enough free spaces on the LPDD in step 328, then in step 372, control determines whether the data that will store may be used before the data in the one or more minimum use piece of being discerned by minimum use piece module.If the judged result of step 372 is false, then drive control module 300 in step 374 with data storage on HPDD and control continue step 324.By doing like this, saved (one or more) minimum use piece has been transferred to the power that LPDD consumes.If the judged result of step 372 is true, then control continues top with reference to the described step 330 of Fig. 7 A.

When the judged result of step 354 during data retrieval request is fictitious time, control continuation step 376 and specified data and whether may be used once.If the judged result of step 376 is true, then drive control module 300 is fetched data and is continued step 324 from HPDD in step 378.By doing like this, saved data have been transferred to the power that LPDD will consume.If the judged result of step 376 is false, then control continues step 360.Can know,, then will data not move on to LPDD if data may be used once.Yet the power consumption of HPDD can not be avoided.

Referring now to Fig. 7 C, also can during low-power operation, carry out the more control of reduced form.Also can during high-power mode and/or low-power mode, carry out and safeguard step (with LPDD maintenance module 308).In step 328, when having enough free spaces on the LPDD, data are transferred to LPDD in step 344 and step 324 is returned in control.Otherwise when the judged result of step 328 is a fictitious time, data are stored on the HPDD in step 380 and step 324 is returned in control.Can know, but the method shown in Fig. 7 C is used LPDD in the capacity time spent, when the LPDD capacity is unavailable, use HPDD.Those skilled in the art will know and can adopt mixed method with the various combinations of the step of Fig. 7 A-7D.

In Fig. 7 D, after returning high-power mode and/or other times by drive control module 300 carry out safeguard step with deletion be stored on the LPDD need not or the file of usefulness seldom.This safeguards that step also can carry out in low-power mode, periodically carry out during use, carries out after the incident such as the full incident of dish takes place and/or execution in other cases.Control starts from step 390.In step 392, control determines whether using high-power mode.If not using high-power mode, then Control Circulation is returned step 392.If the judged result of step 392 is true, then in step 394, control determines whether a last pattern is low-power mode.If not, then step 392 is returned in control.If the judged result of step 394 is true, then in step 396, control is carried out and is safeguarded, for example with ancient deed or seldom the file of usefulness move on to HPDD from LPDD.For example use as mentioned above and, also can make the adaptability judgement the file that may use in the future below with reference to the described standard of Fig. 8 A-10.

Referring now to Fig. 8 A to Fig. 8 C, show storage control system 400-1,400-2 and 400-3.In Fig. 8 A, storage control system 400-1 comprises the buffer memory control module 410 with adaptability storage control module 414.The use of adaptability storage control module 414 monitoring files and/or program is to determine whether they may use under low-power mode still is high-power mode.Buffer memory control module 410 is communicated by letter with one or more data bus 416, and data bus 416 is communicated by letter with volatile memory 422, and volatile memory 422 for example is L1 buffer memory, L2 buffer memory, such as volatibility RAM and/or other volatibility electronic data storage device structures of DRAM.Bus 416 is also communicated by letter with the high power nonvolatile memory 426 such as HPDD with low power non-volatile memory 424 (for example flash memory, the HDD with nonvolatile memory IF and/or LPDD).In Fig. 8 B, shown full feature and/or limited feature operating system comprise adaptability storage control module 414.Appropriate interface and/or controller (not shown) are between data bus and HPDD and/or LPDD.

In Fig. 8 C, host computer control module 440 comprises adaptability storage control module 414.Host computer control module 440 and LPDD424 ' and hard disk drive 426 ' communicate by letter.Host computer control module 440 can be drive control module, integrated device circuit (IDE), ATA, serial ATA (SATA) or other controllers.As among Fig. 8 C as seen, the HDD431 with nonvolatile memory IF can be used as LPDD, and/or can also use the HDD431 with nonvolatile memory IF except LPDD.Host computer control module 440 is communicated by letter with the HDD431 with nonvolatile memory IF via main frame nonvolatile memory IF429.Host computer control module 440 can be integrated with main frame nonvolatile memory IF429.

Referring now to Fig. 9, show by the performed step of the storage control system among Fig. 8 A-8C.In Fig. 9, control starts from step 460.In step 462, control determines whether to exist with the request of data storage to nonvolatile memory.If should not ask, then Control Circulation is returned step 462.Otherwise whether adaptability storage control module 414 specified data in step 464 may be used under low-power mode.If the judged result of step 464 is false, then in step 468, data are stored among the HPDD.If the judged result of step 464 is true, then in step 474, data are stored in the nonvolatile memory 444.

Referring now to Figure 10, show a kind of method whether the specified data piece may use under low-power mode.Table 490 comprises and buffer descriptor symbol field 492, low power counter field 493, high power counter field 494, size field 495, last time uses field 496 and/or manually overthrow field 497.When specific program or file were used during low-power mode or high-power mode, counter field 493 and/or 494 increased progressively.In the time the data storage of program or file need being arrived nonvolatile memory, table 492 is accessed.Threshold percentage and/or count value can be used for assessment.For example, if the service time of file or program is greater than 80% in low-power mode, then file can be stored in the low power non-volatile memory, and low power non-volatile memory for example is flash memory, have HDD and/or the microdrive of nonvolatile memory IF.If do not reach threshold value, then file or program are stored in the high power nonvolatile memory.

Can know, after the sampling of predetermined number, (in other words, just provide scrolling windows) and/or use any other standard can be periodically with counter reset.In addition, possibility can be by size field 495 weightings, modification and/or replacement.In other words, along with the increase of file size, needed threshold value may be increased because of the limited capacity of LPDD.

Can be to the further modification of the judgement of using possibility on the basis of the time that file used last time, making of using as last time that field 496 write down.The time that can use the threshold value date and/or used since last time in possibility is determined is as a factor.Though figure 10 illustrates a table, employed one or more fields can be stored in other positions and/or other data structures.Can use the algorithm and/or the weight sampling of two or more fields.

Use is manually overthrown field 497 and is allowed users and/or operating system manually to overthrow the possibility of using judgement.For example, manually overthrow field and can allow L state, corresponding to the H state of the default storage among the HPDD, and/or corresponding to the A condition (as mentioned above) of storage judgement automatically corresponding to the default storage among the LPDD.What can define other manually overthrows classification.Except above-mentioned standard, can use the current power level that is operated in computing machine under the LPDD to adjust judgement.Those skilled in the art will know and exist other to be used for determining file or the program method with the possibility that is used under high-power mode or low-power mode that these methods drop in the teachings of the present invention.

Referring now to Figure 11 A to Figure 11 C, show driving power and reduce the 500-1 of system, 500-2 and 500-3 (being called 500 jointly).Driving power reduces sequential access file section outburst (burst) that system 500 will be bigger on cycle or other bases to low power non-volatile memory, and described bigger sequential access file for example is but is not limited to audio frequency and/or video file.In Figure 11 A, driving power reduces the 500-1 of system and comprises having the buffer memory control module 520 that driving power reduces control module 522.Buffer memory control module 520 is communicated by letter with one or more data bus 526, and data bus 526 is communicated by letter with HPDD538 with volatile memory 530, nonvolatile memory 534, volatile memory 530 for example is L1 buffer memory, L2 buffer memory, such as volatibility RAM and/or other volatibility electronic data storage device structures of DRAM, nonvolatile memory 534 for example is flash memory, have HDD and/or the LPDD of nonvolatile memory IF.In Figure 11 B, driving power reduces the 500-2 of system and comprises having full feature and/or the limited feature operating system 542 that driving power reduces control module 522.Appropriate interface and/or controller (not shown) are between data bus and HPDD and/or LPDD.

In Figure 11 C, driving power reduces the 500-3 of system and comprises having the host computer control module 560 that driving power reduces control module 522.Host computer control module 560 is communicated by letter with one or more data bus 564, data bus 564 and LPDD534 ' and hard disk drive 538 ' communicate by letter.Host computer control module 560 can be drive control module, integrated device circuit (IDE), ATA, serial ATA (SATA) and/or other controllers or interface.As among Figure 11 C as seen, the HDD531 with nonvolatile memory IF can be used as LPDD, and/or can also use the HDD531 with nonvolatile memory IF except LPDD.Host computer control module 560 is communicated by letter with the HDD531 with nonvolatile memory IF via main frame nonvolatile memory IF529.Host computer control module 560 can be integrated with main frame nonvolatile memory IF529.

Referring now to Figure 12, show by the driving power among Figure 11 A-11C and reduce the performed step of system 500.Control starts from step 582.In step 584, control determines that system is whether under low-power mode.If not, then Control Circulation is returned step 584.If the judged result of step 584 is true, then control continues step 586, and in step 586, control determines that whether the request of big data block access is generally from HPDD.If not, then Control Circulation is returned step 584.If the judged result of step 586 is true, then whether control continuation step 590 and specified data piece be by sequential access.If not, then Control Circulation is returned step 584.If the judged result of step 590 is true, then control continues step 594 and definite playback length.In step 598, control is identified for outburst cycle and the frequency that the data from the high power nonvolatile memory to low power non-volatile memory shift.

In an implementation, outburst cycle and frequency are optimized to reduce power consumption.Outburst cycle and frequency are preferably based on the starting of capacity, playback rate, HPDD and/or the LPDD of starting (spin up) time of HPDD and/or LPDD, nonvolatile memory and the playback length of steady state power consumption and/or alphabetic data piece.

For example, the high power nonvolatile memory is to consume 1-2W during operation, have the starting time of 4-10 second and generally greater than the HPDD of the capacity of 20Gb.Low power non-volatile memory is to consume 0.3-0.5W during operation, have the starting time of 1-3 second and the microdrive of 1-6Gb capacity.Can know that above-mentioned performance number and/or capacity will change for other implementations.HPDD can have to the data transfer rate of the 1Gb/s of microdrive.Playback rate can be 10Mb/s (for example for a video file).Can know that the transfer rate of HPDD multiply by the capacity that the outburst cycle should not surpass microdrive.Cycle between the outburst should add the outburst cycle greater than the starting time.In these parameters, the power consumption of system can be optimised.Under low-power mode,, then consume a large amount of power consumptions if HPDD is used for playing the complete video such as film.Use said method, by optionally data being transferred to LPDD from HPDD with very high speed (for example 100 of playback rate times) and with a plurality of outburst sections of the fixed intervals of being separated by, can reduce power consumption widely, HPDD can be closed then.Can easily obtain Power Cutback greater than 50%.

Referring now to Figure 13, shownly comprise drive control module 650 and one or more HPDD644 and one or more LPDD648 according to polydisc drive system 640 of the present invention.Drive control module 650 is communicated by letter with main process equipment via host computer control module 651.For main frame, as described below, polydisc drive system 640 is operated HPDD644 and LPDD648 to reduce complicacy, to improve performance and reduce power consumption as single disk drive effectively.Host computer control module 651 can be IDE, ATA, SATA and/or other control modules or interface.

Referring now to Figure 14, in an implementation, drive control module 650 comprises the hard disk controller (HDC) 653 of the one or both that is used for controlling LPDD and/or HPDD.The data that impact damper 656 storages are associated with the control of HPDD and/or LPDD, and/or by optimizing the data block size energetically buffering go to/from the data of HPDD and/or LPDD to increase data transfer rate.Processor 657 is carried out the processing of the operation that relates to HPDD and/or LPDD.

HPDD648 comprises one or more discs 652 with magnetic coating of storage tape.The rotating shaft motor rotation that disc 652 is schematically shown by 654 places.In general, during read/write operation, rotating shaft motor 654 is with fixed speed rotation disc 652.One or more read/write arm 658 move relative to disc 652, with from disc 652 reading of data and/or data are write disc 652.Because HPDD648 has bigger disc than LPDD, so rotating shaft motor 654 needs more power to start HPDD and keeps the HPDD fast rotational.Usually, the starting time of HPDD is also higher.

Read/write device 659 is positioned near the end of read/write arm 658.Read/write device 659 comprises writing component, for example produces the inductor in magnetic field.Read/write device 659 also comprises the reading component (for example magnetic resistance (MR) element) in the magnetic field on the sensation disc 652.Pre-amplification circuit 660 amplifies analog read/write signals.

When reading of data, pre-amplification circuit 660 amplifies from the low level signal of reading component and the signal after will amplifying outputs to read/write channel device.In the write data process, produce the write current of the writing component that flows through read/write device 659, write current is switched the magnetic field that has positive polarity or negative polarity with generation.Positive polarity or negative polarity are by disc 652 storages and be used for representative data.LPDD644 also comprises one or more discs 662, rotating shaft motor 664, one or more read/write arm 668, read/write device 669 and pre-amplification circuit 670.

HDC653 communicates by letter with host computer control module 651, and communicates by letter with first rotating shaft/voice coil motor (VCM) driver 672, first read/write channel circuit 674, second rotating shaft/VCM driver 676, second read/write channel circuit 678.Host computer control module 651 and drive control module 650 can be realized by SOC (system on a chip) (SOC) 684.Can know, rotating shaft/ VCM driver 672 and 676 and/or read/ write channel circuit 674 and 678 can make up.Rotating shaft/ VCM driver 672 and 676 control rotating shaft motors 654 and 664, rotating shaft motor 654 and 664 rotates disc 652 and 662 respectively.Rotating shaft/ VCM driver 672 and 676 also for example uses voice coil actuator, stepper motor or any other suitable actuator to produce the control signal of locating read/ write arm 658 and 668 respectively.

Referring now to Figure 15-17, show other variants of polydisc drive system.In Figure 15, drive control module 650 can comprise the direct interface 680 that the outside that is used to be provided to one or more LPDD682 connects.In an implementation, direct interface is periphery component interconnection (PCI) bus, PCI Express (PCIX) bus and/or any other suitable bus or interface.

In Figure 16, host computer control module 651 is communicated by letter with HPDD648 with LPDD644.Low-power drive control module 650LP directly communicates by letter with host computer control module with high power dish drive control module 650HP.Zero in LP and/or the HP drive control module, one or two may be implemented as SOC.As shown in Figure 16, the HDD695 with nonvolatile memory IF can be used as LPDD, and/or can also use the HDD695 with nonvolatile memory IF except LPDD.Host computer control module 651 is communicated by letter with the HDD695 with nonvolatile memory IF via main frame nonvolatile memory IF693.Host computer control module 651 can be integrated with main frame nonvolatile memory IF693.

In Figure 17, a shown exemplary L PDD682 comprises the interface 690 that support is communicated by letter with direct interface 680.As mentioned above, interface 680 and 690 can be periphery component interconnection (PCI) bus, PCI Express (PCIX) bus and/or any other suitable bus or interface.LPDD682 comprises HDC692, impact damper 694 and/or processor 696.As mentioned above, LPDD682 also comprises rotating shaft/VCM driver 676, read/write channel circuit 678, disc 662, rotating shaft motor 665, read/write arm 668, reading component 669 and prime amplifier 670.Perhaps, HDC653, impact damper 656 and processor 657 can make up and be used for two drivers.Equally, rotating shaft/VCM driver and read channel circuit can make up alternatively.In the embodiment of Figure 13-17, the positive buffering of LPDD is used to improve performance.For example, impact damper is used to optimize the data block size to obtain the optimal velocity on the host data bus.

In traditional computer system, the page (paging) file is the hidden file on HPDD or the HP nonvolatile memory, and operating system uses pagefile to hold to be not suitable for a program in the volatile memory that is stored in computing machine and/or the part in the data file.The virtual memory of pagefile and physical storage or RAM definition computing machine.Operating system is transferred to storer with data from pagefile as required, thereby and data are turned back to pagefile from volatile memory abdicates the space for new data.Pagefile is also referred to as exchange (swap) file.

Referring now to Figure 18-20, LP nonvolatile memories such as utilization of the present invention such as LPDD, the HDD with nonvolatile memory IF and/or flash memory increase the virtual memory of computer system.In Figure 18, operating system 700 allows user definition virtual memory 702.During operation, operating system 700 is via 704 pairs of virtual memory 702 addressing of one or more bus.Virtual memory 702 comprise volatile memory 708 and LP nonvolatile memory 710 both, nonvolatile memory 710 for example is flash memory, have HDD and/or the LPDD of nonvolatile memory IF.

Referring now to Figure 19, operating system allow the user distribute in the LP nonvolatile memory 710 some or all as page storage to increase virtual memory.In step 720, the control beginning.In step 724, operating system determines whether to ask other page storage.If do not ask other page storage, then Control Circulation is returned step 724.Otherwise in step 728, operating system distribution portion LP nonvolatile memory is used for the use of pagefile to increase virtual memory.

In Figure 20, operating system adopts other LP nonvolatile memory as page storage.Control starts from step 740.In step 744, whether request msg write operation of operating system is determined in control.If judged result is true, then control the capacity that continues step 748 and determine whether to surpass volatile memory.If no, then in step 750, volatile memory is used for write operation.If the judged result of step 748 is true, then in step 754, data are stored in the pagefile in the LP nonvolatile memory.If the judged result of step 744 is false, then control continues step 760 and determines whether the request msg read operation.If judged result is false, then Control Circulation is returned step 744.Otherwise in step 764, control determines that whether described address is corresponding to address ram.If the judged result of step 764 is true, then be controlled in the step 766 from volatile memory reading of data and continuation step 744.If the judged result of step 764 is false, then be controlled at pagefile reading of data from the LP nonvolatile memory and control continuation step 744 in the step 770.

Can know, compare that the size of using LP nonvolatile memory such as flash memory, the HDD with nonvolatile memory IF and/or LPDD to increase virtual memory will improve the performance of computing machine with the system that adopts HPDD.In addition, power consumption will be lower than the system of HPDD as pagefile that use.HPDD is owing to its bigger size needs the extra starting time, this compares with flash memory and/or LPDD or HDD with nonvolatile memory IF has increased data time, wherein flash memory does not have start delay, and LPDD or the HDD with nonvolatile memory IF have short starting time and lower power consumption.

Referring now to Figure 21, shown redundant array of independent disks (RAID) system 800 comprises one or more and disk array 808 server in communication and/or client 804.Described one or more server and/or client 804 comprise disk array controller 812 and/or array management module 814.The mapping that disk array controller 812 and/or array management module 814 receive data and the data actuating logic address of arriving disk array 808 arrived physical address.Disk array generally comprises a plurality of HPDD816.

The data access speed that a plurality of HPDD816 provide fault-tolerant (redundancy) and/or improve.RAID system 800 provides the method for a plurality of individual HPDD of a kind of access, just as disk array 808 is big hard disk drivers.Generally speaking, disk array 808 can provide hundreds of Gb to tens data storage to hundreds of Tb.Data are stored in a plurality of HPDD816 in every way and go up to lose the risk of all data under the situation that reduces a drives fail and to improve data time.

The method of data storage on HPDD816 is commonly referred to as the RAID rank.There are various RAID ranks, comprise RAID rank 0 or dish segmentation (disk striping).In RAID rank 0 system, data are written in the piece across a plurality of drivers, and next driver is being searched next piece simultaneously to allow a drive read or write data piece.The advantage of dish segmentation comprises the higher access rate and the full use of array capacity.The shortcoming that exists be do not have fault-tolerant.If a drives fail, then become can not access for the full content of array.

RAID rank 1 or disk mirroring provide redundant by writing twice (each driver once).If a drives fail, then another driver comprises the accurate copy of data, and the RAID system can switch to the accessibility that uses mirrored drive and do not lose the user.The higher cost that shortcoming comprises the improvement that lacks on the data access speed and causes owing to the more driver of needs (2N).Yet RAID rank 1 provides the better preserved of data, because in HPDD one when losing efficacy, array management software will be simply all remaining HPDD of application request guiding.

RAID rank 3 usefulness are exclusively used in the other driver of parity information (parity) with data segmentation on a plurality of drivers, are used for error correcting/recovery.RAID rank 5 provides segmentation and is used for the parity information that mistake is recovered.In RAID rank 5, the parity information piece is distributed among a plurality of drivers of array, and this provides the more access load of balance between driver.Parity information is used for restore data under the situation of a drives fail.Shortcoming is slower write cycle time (writes each piece need read for 2 times and write for 2 times).Array capacity is N-1,3 drivers of minimum needs.

RAID rank 0+1 relates to segmentation and the mirror image that does not have parity information.Advantage is fast data access (being similar to RAID rank 0) and single driver fault-tolerant (being similar to RAID rank 1).RAID rank 0+1 also needs the dish (being similar to RAID rank 1) of twice number.Can know, can exist other to be used for the RAID rank and/or the method for data storage on array 808.

Referring now to Figure 22 A and Figure 22 B, the RAID 834-1 of system according to the present invention comprises disk array 836 and disk array 838, and disk array 836 comprises X HPDD, and disk array 838 comprises Y LPDD.One or more clients and/or server 840 comprise disk array controller 842 and/or array management module 844.Though show the device 842 and 844 of separation, these devices can be integrated under the situation of hope.Can know that X is more than or equal to 2, Y is more than or equal to 1.X can be greater than Y, less than Y and/or equal Y.For example, Figure 22 B shows the wherein 834-1 ' of RAID system of X=Y=Z.

Referring now to Figure 23 A, 23B, 24A and 24B, show 834-2 of RAID system and 834-3.In Figure 23 A, LPDD disk array 838 is communicated by letter with server/customer end 840, and HPDD disk array 836 is communicated by letter with LPDD disk array 838.The 834-2 of RAID system can comprise the management bypass, and LPDD disk array 838 is optionally walked around in this management bypass.Can know that X is more than or equal to 2, Y is more than or equal to 1.X can be greater than Y, less than Y and/or equal Y.For example, Figure 23 B shows the wherein 834-2 ' of RAID system of X=Y=Z.In Figure 24 A, HPDD disk array 836 is communicated by letter with server/customer end 840, and LPDD disk array 838 is communicated by letter with HPDD disk array 836.The 834-2 of RAID system can comprise that by the management bypass shown in the dotted line 846, HPDD disk array 836 is optionally walked around in this management bypass.Can know that X is more than or equal to 2, Y is more than or equal to 1.X can be greater than Y, less than Y and/or equal Y.For example, Figure 24 B shows the wherein 834-3 ' of RAID system of X=Y=Z.The strategy that is adopted can comprise directly writing among Figure 23 A-24B (write through) and/or write-back (write back).

Array management module 844 and/or disk controller 842 utilize LPDD disk array 838 to reduce the power consumption of HPDD disk array 836.In general, the HPDD disk array 808 in the traditional RAID system among Figure 21 keeps full-time unlatching to support needed data time during operation.Can know that HPDD disk array 808 consumes relatively large power.In addition, owing to mass data is stored in the HPDD disk array 808, so the disc of HPDD is generally big as much as possible, and this needs more high performance rotating shaft motor, and because read/write arm moves fartherly on average, has therefore increased data time.

According to the present invention, optionally adopted in the RAID system 834 shown in Figure 22 B in conjunction with the described technology of Fig. 6-17 above, to reduce power consumption and data time.Though not shown in Figure 22 A and Figure 23 A-24B, other RAID systems according to the present invention also can use these technology.In other words, LUB module 304 described in Fig. 6 and Fig. 7 A-7D, adaptability memory module 306 and/or LPDD maintenance module are optionally realized by disk array controller 842 and/or array management controller 844, with optionally with data storage on LPDD disk array 838, thereby reduce power consumption and data time.Adaptability storage control module 414 described in Fig. 8 A-8C, Fig. 9 and Figure 10 also can optionally be realized by disk array controller 842 and/or array management controller 844, to reduce power consumption and data time.Driving power described in Figure 11 A-11C and Figure 12 reduces module 522 also can be realized by disk array controller 842 and/or array management controller 844 ground, to reduce power consumption and data time.In addition, multi-drive system shown in Figure 13-17 and/or direct interface can be realized with the one or more HPDD in the HPDD disk array 836 to improve performance and to reduce power consumption and access time.

Referring now to Figure 25, shown network attached storage according to prior art (NAS) system 850 comprises memory device 854, storage requester 858, file server 862 and communication system 866.Memory device 854 generally comprises disk drive, RAID system, tape drive, tape library, CD-ROM driver, automatic disc machine and any other is with the memory device that is shared.Memory device 854 is preferably OO equipment, but is not to be necessary for OO equipment.Memory device 854 can comprise data storage that is used for requester 858 and the I/O interface of fetching.Requester 858 generally comprises the server and/or the client of shared storage device 854 and/or direct access storage device 854.

File server 862 is carried out management and the security function such as request authentication and resource location.The management orientation of memory device 854 depends on file server 862, and requester 858 is disengaged this responsibility is born in storage administration to file server 862 degree.In mini system, may not wish to use dedicated file server.In this case, requester can be born the responsibility of the operation of supervision NAS system 850.Like this, both comprise administration module 870 and 872 respectively shown file server 862 and requester 858, yet in these two administration modules one or another and/or both also can be provided.Communication system 866 is physical infrastructure, and the assembly of NAS system 850 communicates by it.The character that it preferably has network and channel has the ability that connects all component in the network and has the low delay that generally has in the channel.

When NAS system 850 powers up, memory device 854 or to indicating self each other, perhaps to reference common point indicating self, described common reference point is file server 862, one or more requestor 858 and/or communication system 866 for example.Communication system 866 generally is provided for this network management technology, and these technology can be by being connected to the media that is associated with communication system and be obtained.Memory device 854 and requestor 858 sign in on this media.Any assembly of wanting to determine active configuration can use intermediary service to discern every other assembly.Requestor 858 learns the existence of the memory device 854 that they can be visited from file server 862, and memory device 854 learns where go to when they need be located another equipment or call management service such as backup.Similarly, file server 862 can be learnt the existence of memory device 854 from media services.Depend on the security of specific installation, can refuse the visit of requestor certain device.From addressable set of memory device, the requestor can discern file, database and available free space then.

Simultaneously, each NAS assembly can identify it to file server 862 and wants any special consideration known.Any device level Service Properties can once be passed to file server 862, and every other assembly can be learnt these attributes.For example, the requestor may wish to be apprised of the introducing of the other storage after starting, and the attribute that is provided with when this signs in to file server 862 by the requestor triggers.No matter when new memory device is added in the configuration, and file server 862 can be done automatically like this, comprise transmitting important characteristic, for example its be RAID5, by mirror image etc.

When the requestor must open file, it can directly go to memory device 854, and perhaps it is obliged to go toward file server to secure permission and positional information.File server 862 will be the function of the security requirement of installation to which kind of degree to the access control of memory storage.

Referring now to Figure 26, shownly comprise memory device 904, requestor 908, file server 912 and communication system 916 according to network attached storage of the present invention (NAS) system 900.Memory device 904 comprises RAID system 834 and/or top polydisc drive system 930 described in Fig. 6-19.Memory device 904 generally can also comprise disk drive, RAID system, tape drive, tape library, CD-ROM driver, automatic disc machine and any other memory device that will be shared as described above.Can know, use the RAID system of improvement and/or power consumption and the data time that polydisc drive system 930 will reduce NAS system 900.

Referring now to Figure 27, show the disc drive controller that comprises nonvolatile memory and disc drive interface controller.In other words, the HDD of Figure 27 has non-volatile memory interface (hereinafter referred to as the HDD with non-volatile memory interface (IF)).The equipment of Figure 27 allows HDD to be connected to the existing non-volatile memory interface (IF) of main process equipment so that other non-volatile memories to be provided.

Disc drive controller 1100 is communicated by letter with disk drive 1104 with main frame 1102.HDD with nonvolatile memory IF comprises disc drive controller 1100 and disk drive 1104.Disk drive 1104 generally has ATA, ATA-CE or IDE style interface.Auxiliary non-volatile memories 1106 also is coupled to disc drive controller 1100, and it is a disc drive controller storing firmware code.In this case, though main frame 1102 is illustrated as single, but it generally comprises the industrial standard nonvolatile memory groove (connector) that is used to be connected to the non-volatile memory devices type that can buy as associated component, and this groove is connected to the standard nonvolatile memory controller in the main frame again.One of general conformance with standard type of this groove, for example MMC (multimedia card), SD (secure data), as SD/MMC, the HS-MMC (high speed MMC) of SD and MMC combination, as the SD/HS-MMC and the memory stick (Memory Stick) of SD and HS-MMC combination.This tabulation is not restrictive.

Typical application is a portable computer or such as the consumer-elcetronics devices of MP3 music player or cellular handset, this consumer-elcetronics devices has an application processor that communicates by non-volatile memory interface and embedded non-volatile memory.Non-volatile memory interface can comprise flash interface, nand flash memory interface and/or other suitable nonvolatile semiconductor memory interfaces.According to the disclosure, be not to use nonvolatile semiconductor memory, and the disk drive that provides hard disk drive or other types is replaced nonvolatile semiconductor memory and is used its interface signal.Disclosed method provides the interface that is similar to nonvolatile memory for disk drive, and this makes easier conjoint disk driver in the host computer system of usually only accepting flash memory.Is much bigger memory capacity for special cost with disk drive rather than flash memory as an advantage of memory device.

Only need in main frame nonvolatile memory controller firmware and software, make minimum change to be used in combination the disk drive of disclosed interface controller.And, minimum order expense is provided.Advantageously, with regard to the number of the logical block that between main frame and disk drive, shifts, exist unconfined data to shift for any specific read or write.And main frame needn't provide the sector count of disk drive.

In certain embodiments, disk drive 1104 can be small-shape factor (SFF) hard disk drive, and it generally has the physical size of 650 * 15 * 70mm.The typical data transfer rate of such SFF hard disk drive is per second 25 megabyte.

Further specify the function of the disc drive controller 1100 of Figure 27 below.Disc drive controller 1100 comprises interface controller 1110, and interface controller 1110 is the flash controllers with bus of 14 rows for host computer system 1102.Interface controller 1110 is also carried out the data flow con-trol function between Host Command explanation and main frame 1102 and the buffer-manager 1112.Buffer-manager circuit 1112 is via the actual impact damper (storer) of Memory Controller 1116 control, and actual impact damper can be to be included on the chip identical with interface controller 1100 as a part or SRAM or DRAM impact damper 1118 on individual chips.Buffer-manager provides following further described buffer attribute.

Buffer-manager 1112 is also connected to processor interface/servo and ID-Less/ defect management device (MPIF/SAIL/DM) circuit 1122, and it is carried out track format and produces and defect management function.MPIF/SAIL/DM circuit 1122 is connected to high performance bus (AHB) 1126 again.Line buffer memory (line cache) 1128 and processor 1130 are connected to ahb bus 1126; Tightly-coupled-memory (TCM) 1134 is associated with processor 1130.Processor 1130 can be realized by flush bonding processor or microprocessor.The purpose of line buffer memory 1128 is to reduce code to carry out delay.It can be coupled to external flash 1106.

Other pieces execution functions in the disc drive controller 1100 are with the support disc driver and comprise servo controller 1140, dish formatter and error correction circuit 1142 and read channel circuit 1144, and read channel circuit 1144 is connected to the pre-amplification circuit in the disk drive 1104.8 rows (0-7) in 14 rows' the parallel bus can be carried two-way I/O (I/O) data.Other rows can carry respectively order CLE, ALE ,/CE ,/RE ,/WE and R/B.

Referring now to Figure 28, illustrate in greater detail the interface controller of Figure 27.Interface controller 1110 comprises flash controller (flash_ctl) piece 1150, flash memory register (flash_reg) piece 1152, flash memory FIFO packing (flash_fifo_wrapper) piece 1154 and flash memory system (flash_sys_syn) piece 1156 synchronously.

Flash memory block of registers 1152 is used for register access.The order that its storage is programmed by processor 1130 and main frame 1102.Flash memory state machine (not shown) in the flash controller 1150 is decoded to the order that enters from main frame 1102 and is provided control for disc drive controller 1100.Flash memory FIFO packing 1154 comprises the FIFO that can be realized by 32 * 32 two-way asynchronous FIFO.It produces data and control signal, is used for via buffer-manager interface (BM IF) data being transferred to buffer-manager 1112 and being received data via the buffer-manager interface from buffer-manager 1112.The shift direction of FIFO can be controlled by the order that is stored in the flash memory register 1152.Flash memory system synchronization blocks 1156 is carried out the control signal between interface controller and the buffer-manager interface synchronously.It also produces counter initialization pulse (clk2_clr) for flash memory FIFO packing 1154.

Flash controller 1150 can be realized reading at random of LPDD by the control interface signal wire.Flash controller 1150 can the control interface signal wire be realized the random writing of LPDD.Flash controller 1150 can realize that the order of LPDD reads by the control interface signal wire, and can realize that the order of LPDD writes by the control interface signal wire.Flash controller 1150 can the control interface signal wire realizes that the order between control module and the LPDD shifts.Flash controller 1150 can be with one group of LPDD command mapping to corresponding one group of flash command.

Flash memory register 1152 is via processor bus and interface controller and LPDD processor communication.The order that 1152 storages of flash memory register are programmed by LPDD processor and control module.Flash controller 1150 can be with from data storage that LPDD the read difference with the data transfer rate between compensation control module and the LPDD memory buffer, and can signal ready for data to control module to have data in the indication memory buffer unit.

Flash controller 1150 can be stored the write data from control module in memory buffer, with the difference of data transfer rate between compensation control module and the LPDD.Flash controller 1150 can be led control module by signal ready for data, with indication data is arranged in memory buffer unit.

Referring now to Figure 29, the general functional block diagram that polydisc drive system with flash interface is shown at 1200 places.Though previous discussion relates to a use with disk drive (for example low-power or high power disk drive) of flash interface, a plurality of disk drives can be connected via flash interface.More particularly, the polydisc drive system 1204 with flash interface comprises the main frame flash interface 1206 of communicating by letter with the flash interface of main frame 1202.Main frame flash interface 1206 is worked as mentioned above.Drive control module 1208 is one or two among any one among inoperation HPDD 1220 and the LPDD 1222 or operation HPDD 1220 and the LPDD 1222 optionally.Aforesaid control technology about low-power and high-power mode operation can be carried out by drive control module 1208.In some implementations, the information of the power mode of the power mode of main frame flash interface 1206 sensation main frames and/or reception sign main frame 1202.

Referring now to Figure 30, show the process flow diagram of explanation by the performed step of the polydisc drive system of Figure 29.Control starts from step 1230.In step 1232, control determines whether main frame is opened.If the judged result of step 1232 is true, then is controlled at and determines in the step 1234 that main frame is whether under high-power mode.If the judged result of step 1234 is true, then is controlled in the step 1236 and powers up for LPDD 1222 and/or HPDD 1220 as required.If the judged result of step 1234 is false, then is controlled at and determines in the step 1238 that main frame is whether under low-power mode.If the judged result of step 1238 is true, then is controlled at and cuts off the power supply for HPDD in the step 1240 and as required LPDD is operated with saving power.Control continues step 1232 from step 1238 (if judged result is false) and step 1240.

Can know that aforesaid HDD with flash interface can use aforesaid multiple disk file with flash interface.In addition, aforesaid about any can in the multiple disk file with flash interface shown in Figure 29, the use in the control technology of system with LPDD and HPDD.In in aforesaid embodiment any one, LPDD or HPDD can be replaced by the low power non-volatile memory of any kind.For example, LPDD or HPDD can by such as flash memory but any suitable non-volatile solid state memory that is not limited to flash memory replace.Equally, the low power non-volatile memory in any one among the aforesaid embodiment can be replaced by the low-power disk drive.Though described flash memory among more superincumbent embodiment, can use the nonvolatile semiconductor memory of any kind.

Referring now to Figure 31 A-31C, show the various data handling systems that work in high-power mode and low-power mode.When changing between high-power mode and low-power mode, high power and low-power processor are optionally transferred to one or more program threads each other.Thread can be under the various completion statuses.This allows the bumpless transfer between high-power mode and the low-power mode.

In Figure 31 A, disposal system 1300 comprises high power (HP) processor 1304, low-power (LP) processor 1308 and register file 1312.In high-power mode, high-power processor 1304 is in active state and processing threads.Low-power processor 1308 also can be worked during high-power mode.In other words, low-power processor is in active state in can be during high-power mode all or part of and/or can be in inoperative mode.

In low-power mode, low-power processor 1308 be operated under the active state and high-power processor 1304 inactive.High-power processor 1304 can be used identical or similar instruction group respectively with low-power processor 1308.Low-power can have identical or similar architecture with high- power processor.Processor 1304 and 1308 both when low-power mode is transformed into high-power mode and when high-power mode is transformed into low-power mode, can temporarily be operated in simultaneously under the active state.

High-power processor 1304 and low-power processor 1308 comprise transistor 1306 and 1310 respectively.The transistor 1306 of high-power processor 1304 is tending towards consuming more power than the transistor 1310 of low-power processor 1308 during working in active state.In some implementations, transistor 1306 can have higher leakage current than transistor 1310.Transistor 1310 can have the size bigger than the size of transistor 1306.

High-power processor 1304 can be more complicated more than low-power processor 1308.For example, low-power processor 1308 can have the littler width and/or the degree of depth than high-power processor.In other words, width can be defined by the number of parallel pipeline (pipeline).High-power processor 1304 can comprise P _HPIndividual parallel pipeline 1342, low-power processor 1308 can comprise P _LPIndividual parallel pipeline 1346.In some implementations, P _LPCan be less than P _HPP _LPIt can be integer more than or equal to zero.Work as P _LP=0 o'clock, low-power processor did not comprise any parallel pipeline.The degree of depth can be defined by progression.High-power processor 1304 can comprise S _HPLevel 1344, low-power processor 1308 can comprise S _LPLevel 1348.In some implementations, S _LPCan be less than S _HPS _LPIt can be integer more than or equal to 1.

Register file 1312 can be shared between high-power processor 1304 and low-power processor 1308.Register file 1312 can be used for register, checkpoint and/or programmable counter with predetermined address location.For example, can be stored in the same position of register file 1312 by high-power processor 1304 and/or low-power processor 1308 employed registers, checkpoint and/or programmable counter respectively.Therefore, high-power processor 1304 and low-power processor 1308 can be located specific register, checkpoint and/or programmable counter when new thread has been passed to processor separately.Share the transfer that register file 1312 helps thread.Register file 1312 can be except the register file the register file (not shown) in each of high-power processor 1304 and low-power processor 1308 respectively.Thread can comprise single-threaded and/or multithreading.

Can provide control module 1314 optionally to control the conversion between high-power mode and the low-power mode.Control module 1314 can be from another module or equipment receiving mode request signal.Control module 1314 can monitoring thread transfer and/or relate to the information that thread shifts, for example register, checkpoint and/or programmable counter.In case the transfer of thread is finished, control module 1314 just can be converted to inactive state with one of high-power processor and low-power processor.

High-power processor 1304, low-power processor 1308, register file 1312 and/or control module 1314 may be implemented as SOC (system on a chip) (SOC) 1330.

In Figure 31 B, disposal system 1350 comprises high power (HP) processor 1354 and low-power (LP) processor 1358.High-power processor 1354 comprises register file 1370, and low-power processor 1358 comprises register file 1372.

In high-power mode, high-power processor 1354 is in active state and processing threads.Low-power processor 1358 also can be worked during high-power mode.In other words, low-power processor 1358 is in active state (and can processing threads) in can be during high-power mode all or part of and/or can be in inoperative mode.In low-power mode, low-power processor 1358 be operated under the active state and high-power processor 1354 inactive.High-power processor 1354 can be used identical or similar instruction group respectively with low-power processor 1358.Processor 1354 can have identical or similar architecture with 1358. Processor 1354 and 1358 both when low-power mode is transformed into high-power mode and when high-power mode is transformed into low-power mode, can all be under the active state.

High-power processor 1354 and low-power processor 1358 comprise transistor 1356 and 1360 respectively.Transistor 1356 is tending towards consuming more power than transistor 1360 during working in active state.In some implementations, transistor 1356 can have higher leakage current than transistor 1360.Transistor 1360 can have the size bigger than the size of transistor 1356.

High-power processor 1354 can be more complicated more than low-power processor 1358.For example, low-power processor 1358 can have the littler width and/or the degree of depth than the high-power processor shown in Figure 31 A.In other words, the width of low-power processor 1358 can comprise parallel pipeline still less or not comprise parallel pipeline than high-power processor 1354.The degree of depth of low-power processor 1358 can than high-power processor 1354 comprise still less the level.

Register file 1370 is the thread information of high-power processor 1354 storage such as register, programmable counter and checkpoints.Register file 1372 is the thread information of low-power processor 1358 storage such as register, programmable counter and checkpoints.During thread shifted, high-power processor 1354 and low-power processor 1358 can also shift the register, programmable counter and the checkpoint that are associated with the thread that is shifted respectively to be stored in register file 1370 and/or 1372.

Can provide control module 1364 to control conversion between high-power mode and the low-power mode.Control module 1364 can be from another module receiving mode request signal.Control module 1364 can with or HP processor or LP processor integrated.Control module 1364 can monitoring thread and/or is related to the transfer of the information of register, checkpoint and/or programmable counter.In case the transfer of (one or more) thread is finished, control module 1364 just can be converted to inactive state with one of high-power processor and low-power processor.

In Figure 31 C, two or more in high-power processor 1354, low-power processor 1358 and/or the control module 1364 are integrated in the SOC (system on a chip) (SOC) 1380.Can know that control module 1364 also can be by independent realization.Though register file 1370 and 1372 is illustrated as the part of HP processor and LP processor, they also can be by independent realization.

Referring now to Figure 32 A-32C, show the various graphic systems that work in high-power mode and low-power mode.When changing between high-power mode and low-power mode, high power and low-power Graphics Processing Unit (GPU) are optionally transferred to one or more program threads each other.Thread can be under the various completion statuses.This allows the bumpless transfer between high-power mode and the low-power mode.

In Figure 32 A, graphic system 1400 comprises high power (HP) GPU 1404, low-power (LP) GPU 1408 and register file 1412.In high-power mode, high power GPU1404 is in active state and processing threads.Low-power GPU 1408 also can work during high-power mode.In other words, low-power GPU is in active state in can be during high-power mode all or part of and/or can be in inoperative mode.

In low-power mode, low-power GPU 1408 be operated under the active state and high power GPU 1404 inactive.High power GPU 1404 can use identical or similar instruction group respectively with low-power GPU 1408.Low-power can have identical or similar architecture with high power GPU.GPU 1404 and 1408 both when low-power mode is transformed into high-power mode and when high-power mode is transformed into low-power mode, can temporarily be operated in simultaneously under the active state.

High power GPU 1404 and low-power GPU 1408 comprise transistor 1406 and 1410 respectively.The transistor 1406 of high power GPU 1404 is tending towards consuming more power than the transistor 1410 of low-power GPU 1408 during working in active state.In some implementations, transistor 1406 can have higher leakage current than transistor 1410.Transistor 1410 can have the size bigger than the size of transistor 1406.

High power GPU 1404 can be more complicated more than low-power GPU 1408.For example, low-power GPU 1408 can have the littler width and/or the degree of depth than high power GPU.In other words, width can be defined by the number of parallel pipeline.High power GPU 1404 can comprise P _HPIndividual parallel pipeline 1442, low-power GPU 1408 can comprise P _LPIndividual parallel pipeline 1446.In some implementations, P _LPCan be less than P _HPP _LPIt can be integer more than or equal to zero.Work as P _LP=0 o'clock, low-power GPU did not comprise any parallel pipeline.The degree of depth can be defined by progression.High power GPU 1404 can comprise S _HPLevel 1444, low-power GPU 1408 can comprise S _LPLevel 1448.In some implementations, S _LPCan be less than S _HPS _LPIt can be integer more than or equal to 1.

Register file 1412 can be shared between high power GPU 1404 and low-power GPU 1408.Register file 1412 can be used for register, checkpoint and/or programmable counter with predetermined address location.For example, can be stored in the same position of register file 1412 by high power GPU 1404 and/or low-power GPU 1408 employed registers, checkpoint and/or programmable counter respectively.Therefore, high power GPU 1404 and low-power GPU 1408 can locate specific register, checkpoint and/or programmable counter when new thread has been transferred to GPU separately.Share the transfer that register file 1412 helps thread.Register file 1412 can be except the register file the register file (not shown) in each of high power GPU 1404 and low-power GPU 1408 respectively.Thread can comprise single-threaded and/or multithreading.

Can provide control module 1414 optionally to control the conversion between high-power mode and the low-power mode.Control module 1414 can be from another module or equipment receiving mode request signal.Control module 1414 can monitoring thread transfer and/or relate to the information that thread shifts, for example register, checkpoint and/or programmable counter.In case the transfer of thread is finished, control module 1414 just can be converted to inactive state with one of high power GPU and low-power GPU.

High power GPU 1404, low-power GPU 1408, register file 1412 and/or control module 1414 may be implemented as SOC (system on a chip) (SOC) 1430.

In Figure 32 B, disposal system 1450 comprises high power (HP) GPU 1454 and low-power (LP) GPU 1458.High power GPU 1454 comprises register file 1470, and low-power GPU1458 comprises register file 1472.

In high-power mode, high power GPU 1454 is in active state and processing threads.Low-power GPU 1458 also can work during high-power mode.In other words, low-power GPU1458 is in active state (and can processing threads) in can be during high-power mode all or part of and/or can be in inoperative mode.In low-power mode, low-power GPU1458 be operated under the active state and high power GPU 1454 inactive.High power GPU 1454 can use identical or similar instruction group respectively with low-power GPU 1458.GPU1454 can have identical or similar architecture with 1458. GPU 1454 and 1458 both when low-power mode is transformed into high-power mode and when high-power mode is transformed into low-power mode, can all be under the active state.

High power GPU 1454 and low-power GPU 1458 comprise transistor 1456 and 1460 respectively.Transistor 1456 is tending towards consuming more power than transistor 1460 during working in active state.In some implementations, transistor 1456 can have higher leakage current than transistor 1460.Transistor 1460 can have the size bigger than the size of transistor 1456.

High power GPU 1454 can be more complicated more than low-power GPU 1458.For example, low-power GPU 1458 can have the littler width and/or the degree of depth than the high power GPU shown in Figure 32 A.In other words, the width of low-power GPU 1458 can comprise still less parallel pipeline than high power GPU 1454.The degree of depth of low-power GPU 1458 can than high power GPU 1454 comprise still less the level.

Register file 1470 is the thread information of high power GPU 1454 storage such as register, programmable counter and checkpoints.Register file 1472 is the thread information of low-power GPU 1458 storage such as register, programmable counter and checkpoints.During thread shifted, high power GPU1454 and low-power GPU 1458 can also shift the register, programmable counter and the checkpoint that are associated with the thread that is shifted respectively to be stored in register file 1470 and/or 1472.

Can provide control module 1464 to control conversion between high-power mode and the low-power mode.Control module 1464 can be from another module receiving mode request signal.Control module 1464 can monitoring thread and/or is related to the transfer of the information of register, checkpoint and/or programmable counter.In case the transfer of (one or more) thread is finished, control module 1464 just can be converted to inactive state with one of high power GPU and low-power GPU.

In Figure 32 C, two or more in high power GPU 1454, low-power GPU 1458 and/or the control module 1464 are integrated in the SOC (system on a chip) (SOC) 1480.Can know that control module 1464 also can be by independent realization.

Referring now to Figure 33, show the process flow diagram that explanation is used for the illustrative methods of the data of application drawing 31A-32C and graphic system.Operation starts from step 1500.In step 1504, control determines whether equipment is operated under the high-power mode.In step 1508, control determines whether that request is transformed into low-power mode.When the judged result of step 1508 is a true time, be controlled in the step 1512 data or figure thread are transferred to low-power processor or GPU.In step 1516, be controlled under the situation about needing and arrive low-power processor or GPU such as the information transfer of register, checkpoint and/or programmable counter.When using shared storage, this step can be omitted.In step 1520, control determines whether thread and/or other information have correctly been transferred to low-power processor or GPU.If the judged result of step 1520 is true, then controls high-power processor or GPU are converted to inactive state.

If the judged result of step 1504 is false, then control determines whether equipment is operated under the low-power mode.If the judged result of step 1528 is true, then control determines whether that request is transformed into high-power mode.If the judged result of step 1532 is true, then is controlled in the step 1536 data or figure thread are transferred to high-power processor or GPU.In step 1540, control will be such as the information transfer of register, checkpoint and/or programmable counter to high-power processor or GPU.When using shared storage, this step can be omitted.In step 1544, control determines whether thread and/or other information have been transferred to high-power processor or GPU.When the judged result of step 1544 is a true time, control is with low-power processor or GPU is converted to inactive state and step 1504 is returned in control.

Referring now to Figure 34 A-34G, show the various exemplary implementation that comprises instruction of the present invention.

Referring now to Figure 34 A, instruction of the present invention can realize in the control system of hard disk drive (HDD) 1600.HDD 1600 comprises Hard disc module (HDA) 1601 and HDD PCB1602.HDA 1601 can comprise magnetic medium 1603 and read/write device 1604, and magnetic medium 1603 for example is one or more discs of storage data.Read/write device 1604 can be disposed on the actuator arm 1605 and can be on magnetic medium 1603 the read and write data.In addition, HDA 1601 comprises rotating shaft motor 1606 that makes magnetic medium 1603 rotations and the voice coil motor (VCM) 1607 that actuator arm 1605 is activated.Prime amplifier device 1608 amplifies and signal is offered read/write device 1604 during write operation at the signal that during the read operation read/write device 1604 is produced.

HDD PCB 1602 comprises read/write channel module (hereinafter referred to as " read channel ") 1609, hard disk controller (HDC) module 1610, impact damper 1611, nonvolatile memory 1612, processor 1613 and rotating shaft/VCM Drive Module 1614.Read channel 1609 is handled the data that receive and send to prime amplifier device 1608 from prime amplifier device 1608.HDC module 1610 is controlled the assembly of HDA 1601 and is communicated by letter with the external unit (not shown) via I/O interface 1615.External unit can comprise computing machine, multimedia equipment, mobile computing device etc.I/O interface 1615 can comprise wired and/or wireless communication link.

HDC module 1610 can receive data from HDA 1601, read channel 1609, impact damper 1611, nonvolatile memory 1612, processor 1613, rotating shaft/VCM Drive Module 1614 and/or I/O interface 1615.Processor 1613 can deal with data, comprises coding, decoding, filters and/or format.Treated data can be output to HDA 1601, read channel 1609, impact damper 1611, nonvolatile memory 1612, processor 1613, rotating shaft/VCM Drive Module 1614 and/or I/O interface 1615.

The control that HDC module 1610 can be used impact damper 1611 and/or nonvolatile memory 1612 to store to relate to HDD 1600 and the data of operation.Impact damper 1611 can comprise DRAM, SDRAM etc.Nonvolatile memory 1612 can comprise flash memory (comprising NAND and NOR flash memory), phase transition storage, magnetic RAM or multi-state memory, and in multi-state memory, each memory cell has the state more than two.Rotating shaft/VCM Drive Module 1614 control rotating shaft motors 1606 and VCM 1607.The assembly that HDD PCB 1602 is included as HDD 1600 provides the power supply 1616 of power.

Referring now to Figure 34 B, instruction of the present invention can realize in the control system of DVD driver 1618 or CD driver (not shown).DVD driver 1618 comprises DVD PCB 1619 and DVD assembly (DVDA) 1620.DVD PCB 1619 comprises DVD control module 1621, impact damper 1622, nonvolatile memory 1623, processor 1624, rotating shaft/FM (feed motor (feed motor)) Drive Module 1625, analog front-end module 1626, writes policy module 1627 and DSP module 1628.

DVD control module 1621 is controlled the assembly of DVDA 1620 and is communicated by letter with the external unit (not shown) via I/O interface 1629.External unit can comprise computing machine, multimedia equipment, mobile computing device etc.I/O interface 1629 can comprise wired and/or wireless communication link.

DVD control module 1621 can be from impact damper 1622, nonvolatile memory 1623, processor 1624, rotating shaft/FM Drive Module 1625, analog front-end module 1626, write policy module 1627, DSP module 1628 and/or I/O interface 1629 receives data.Processor 1624 can deal with data, comprises coding, decoding, filters and/or format.DSP module 1628 is carried out signal Processing, for example video and/or audio coding/decoding.Treated data can be output to impact damper 1622, nonvolatile memory 1623, processor 1624, rotating shaft/FM Drive Module 1625, analog front-end module 1626, write policy module 1627, DSP module 1628 and/or I/O interface 1629.

The control that DVD control module 1621 can be used impact damper 1622 and/or nonvolatile memory 1623 to store to relate to DVD driver 1618 and the data of operation.Impact damper 1622 can comprise DRAM, SDRAM etc.Nonvolatile memory 1623 can comprise flash memory (comprising NAND and NOR flash memory), phase transition storage, magnetic RAM or multi-state memory, and in multi-state memory, each memory cell has the state more than two.The assembly that DVD PCB 1619 is included as DVD driver 1618 provides the power supply 1630 of power.

DVDA 1620 can comprise prime amplifier device 1631, laser driver 1632 and optical device 1633, and optical device 1633 can be optical read/write (ORW) device or light read-only (OR) device.Rotating shaft motor 1634 makes optical storage media 1635 rotations, and feed motor 1636 sun adjuster spares 1633 activate with respect to optical storage media 1635.

When from optical storage media 1635 reading of data, laser driver offers optical device 1633 with readout power.Optical device 1633 detects and sends to prime amplifier device 1631 from the data of optical storage media 1635 and with data.Analog front-end module 1626 receives data and carries out function such as filtering and A/D conversion from prime amplifier 1631.In order to write optical storage media 1635, write policy module 1627 power level and timing information are sent to laser driver 1632.Thereby laser driver 1632 control optical devices 1633 are write optical storage media 1635 with data.

Referring now to Figure 34 C, instruction of the present invention can realize in the control system of high-definition television (HDTV) 1637.HDTV 1637 comprises HDTV control module 1638, display 1639, power supply 1640, storer 1641, memory device 1642, WLAN interface 1643 and associated antenna 1644 and external interface 1645.

HDTV 1637 can be from WLAN interface 1643 and/or external interface 1645 receiving inputted signals, and external interface 1645 sends and receives information via cable, broadband the Internet and/or artificial satellite.HDTV control module 1638 can be handled input signal, comprises coding, decoding, filters and/or format, and produce output signal.Output signal can be sent to one or more in display 1639, storer 1641, memory device 1642, WLAN interface 1643 and the external interface 1645.

Storer 1641 can comprise random-access memory (ram) and/or the nonvolatile memory such as flash memory, phase transition storage or multi-state memory, and in multi-state memory, each memory cell has the state more than two.Memory device 1642 can comprise optical storage drive and/or hard disk drive (HDD), and optical storage drive for example is the DVD driver.HDTV control module 1638 is via WLAN interface 1643 and/or external interface 1645 and and PERCOM peripheral communication.Power supply 1640 provides power for the assembly of HDTV 1637.

Referring now to Figure 34 D, instruction of the present invention can realize in the control system of vehicle 1646.Vehicle 1646 can comprise vehicle control system 1647, power supply 1648, storer 1649, memory device 1650 and WLAN interface 1652 and associated antenna 1653.Vehicle control system 1647 can be power transmission (powertrain) control system, body control system, amusement control system, anti-lock braking system (ABS), navigational system, information communication system, deviation system, adaptability cruise control system etc.

Vehicle control system 1647 can be communicated by letter with one or more sensors 1654 and be produced one or more output signals 1656.Sensor 1654 can comprise temperature sensor, acceleration transducer, pressure transducer, rotation sensor, pneumatic sensor etc.Output signal 1656 can be controlled engine operation parameters, transmission operating parameter, suspension parameter etc.

Power supply 1648 provides power for the assembly of vehicle 1646.Vehicle control system 1647 can be with data storage in storer 1649 and/or memory device 1650.Storer 1649 can comprise random-access memory (ram) and/or the nonvolatile memory such as flash memory, phase transition storage or multi-state memory, and in multi-state memory, each memory cell has the state more than two.Memory device 1650 can comprise optical storage drive and/or hard disk drive (HDD), and optical storage drive for example is the DVD driver.Vehicle control system 1647 can be used WLAN interface 1652 and PERCOM peripheral communication.

Referring now to Figure 34 E, instruction of the present invention can realize in the control system of cell phone 1658.Cell phone 1658 comprises telephone control module 1660, power supply 1662, storer 1664, memory device 1666 and cellular network interface 1667.Cell phone 1658 can comprise WLAN interface 1668 and associated antenna 1669, microphone 1670, the output of the audio frequency such as loudspeaker and/or output socket 1672, display 1674 and the user input device such as keyboard and/or pointing device 1676.

Telephone control module 1660 can be from cellular network interface 1667, WLAN interface 1668, microphone 1670 and/or user input device 1676 receiving inputted signals.Telephone control module 1660 can processing signals, comprises coding, decoding, filtering and/or format, and produces output signal.Output signal can be sent to one or more in storer 1664, memory device 1666, cellular network interface 1667, WLAN interface 1668 and the audio frequency output 1672.

Storer 1664 can comprise random-access memory (ram) and/or the nonvolatile memory such as flash memory, phase transition storage or multi-state memory, and in multi-state memory, each memory cell has the state more than two.Memory device 1666 can comprise optical storage drive and/or hard disk drive (HDD), and optical storage drive for example is the DVD driver.Power supply 1662 provides power for the assembly of cell phone 1658.

Referring now to Figure 34 F, instruction of the present invention can realize in the control system of set-top box 1678.Set-top box 1678 comprises machine top control module 1680, display 1681, power supply 1682, storer 1683, memory device 1684 and WLAN interface 1685 and associated antenna 1686.

Machine top control module 1680 can be from WLAN interface 1685 and external interface 1687 receiving inputted signals, and external interface 1687 can send and receive information via cable, broadband the Internet and/or artificial satellite.Machine top control module 1680 can processing signals, comprises coding, decoding, filtering and/or format, and produces output signal.Output signal can comprise the audio frequency and/or the vision signal of standard and/or HD.Output signal can be sent to WLAN interface 1685 and/or display 1681.Display 1681 can comprise televisor, projector and/or monitor.

Power supply 1682 provides power for the assembly of set-top box 1678.Storer 1683 can comprise random-access memory (ram) and/or the nonvolatile memory such as flash memory, phase transition storage or multi-state memory, and in multi-state memory, each memory cell has the state more than two.Memory device 1684 can comprise optical storage drive and/or hard disk drive (HDD), and optical storage drive for example is the DVD driver.

Referring now to Figure 34 G, instruction of the present invention can realize in the control system of media player 1689.Media player 1689 can comprise media player control module 1690, power supply 1691, storer 1692, memory device 1693, WLAN interface 1694 and associated antenna 1695 and external interface 1699.

Media player control module 1690 can be from WLAN interface 1694 and/or external interface 1699 receiving inputted signals.External interface 1699 can comprise USB, infrared and/or Ethernet.Input signal can comprise compressed audio frequency and/or video, and can defer to MP3 format.In addition, media player control module 1690 can be imported 1696 from the user such as keyboard, touch dish (touchpad) or separate button and receive input.Media player control module 1690 can be handled input signal, comprises coding, decoding, filtering and/or format, and produces output signal.

Media player control module 1690 can output to display 1698 with vision signal with audio signal output to audio frequency output 1697.Audio frequency output 1697 can comprise loudspeaker and/or output socket.Display 1698 can be the graphic user interface that comprises menu, icon etc.Power supply 1691 provides power for the assembly of media player 1689.Storer 1692 can comprise random-access memory (ram) and/or the nonvolatile memory such as flash memory, phase transition storage or multi-state memory, and in multi-state memory, each memory cell has the state more than two.Memory device 1693 can comprise optical storage drive and/or hard disk drive (HDD), and optical storage drive for example is the DVD driver.

Those skilled in the art can know from top description that now extensive instruction of the present invention can realize with various forms.Therefore, though described the present invention together with specific example of the present invention, but true scope of the present invention should be so unlimited, because after having learnt accompanying drawing, instructions and claims, other modifications will become clear to those skilled in the art.

The application requires the provisional application No.60/825 of submission on September 12nd, 2006,368, the provisional application No.60/823 that on August 24th, 2006 submitted to, the provisional application No.60/822 that on August 10th, 453 and 2006 submitted to, 015 right, and be the U.S. Patent application No.11/503 that submitted on August 11st, 2006,016 part continuity, U.S. Patent application No.11/503,016 requires the provisional application No.60/820 of submission on July 31st, 2006, the provisional application No.60/799 that on May 10th, 867 and 2006 submitted to, 151 right, provisional application No.60/799,151 is the U.S. Patent application No.10/865 that submitted on June 10th, 2004,368 part continues and is U.S. Patent application No.11/322,447 part continuity, U.S. Patent application No.11/322, the 447th, submit on Dec 29th, 2005 and its require the provisional application No.60/678 that submitted on May 5th, 2005,249 right.

The U.S. Patent application No.10/779 that the application relates on February 13rd, 2004 and submits to, 544, and the U.S. Patent application No.10/865 that relates on June 10th, 2004 and submit to, 732.The open of these applications all is herein incorporated by reference.

Claims (20)

1. SOC (system on a chip) comprises:

By the first processor that described SOC (system on a chip) realizes, this first processor has movable and inactive state and first and second groups of threads of processing during described active state;

By second processor that described SOC (system on a chip) realizes, this second processor has activity and inactive state, and wherein said second processor works in described active state consumption power still less than described first processor when working in described active state; And

Control module by described SOC (system on a chip) realization, this control module and described first and second processor communications, and optionally described second group of thread transferred to described second processor and selected the described inactive state of described first processor, the described second group of thread of wherein said second processor processing from described first processor.

2. SOC (system on a chip) as claimed in claim 1 also comprises the register file that is realized by described SOC (system on a chip), and this register file and described first processor and described second processor communication and storage are used for the thread information of described first and second processors.

3. SOC (system on a chip) as claimed in claim 2, wherein said thread information comprise register, checkpoint and programmable counter at least a of the described thread that is used for described first and second processors.

4. SOC (system on a chip) as claimed in claim 1 also comprises:

First register file, this first register file are communicated by letter with described first processor and are stored the first thread information that is used for described first processor; And

Second register file, this second register file and described second processor communication and storage are used for the second thread information of described second processor.

5. SOC (system on a chip) as claimed in claim 4, the wherein said first and second thread information comprise register, checkpoint and programmable counter at least a of the described thread that is used for described first and second processors respectively.

6. SOC (system on a chip) as claimed in claim 4, wherein said control module with described thread when described first processor is transferred to described second processor, described thread information is transferred to described second register file from described first register file.

7. SOC (system on a chip) as claimed in claim 1, wherein said first processor comprises the first transistor, described second processor comprises transistor seconds, and described the first transistor has higher leakage current than described transistor seconds.

8. SOC (system on a chip) as claimed in claim 1, wherein said first processor comprises the first transistor, described second processor comprises transistor seconds, and described transistor seconds has bigger size than described the first transistor.

9. SOC (system on a chip) as claimed in claim 1, wherein said SOC (system on a chip) are in high-power mode when described first processor is in active state, be in low-power mode when described first processor is inactive.

10. SOC (system on a chip) as claimed in claim 1, wherein said first and second processors comprise first and second Graphics Processing Unit respectively.

11. a disposal system comprises:

First processor, this first processor have movable and inactive state and at least one thread of processing during described active state;

Second processor, this second processor has activity and inactive state, and wherein said second processor works in described active state consumption power still less than described first processor when working in described active state; And

Control module, this control module and described first and second processor communications, and optionally described at least one thread is transferred to described second processor and selected the described inactive state of described first processor, described at least one thread of wherein said second processor processing from described first processor.

12. disposal system as claimed in claim 11, also comprise the register file that realizes by SOC (system on a chip), this register file and described first processor and described second processor communication and storage are used for the thread information of described first and second processors, and wherein said thread information comprises register, checkpoint and programmable counter at least a of the described thread that is used for described first and second processors.

13. SOC (system on a chip) that comprises described first and second processors of claim 12 and described register file.

14. disposal system as claimed in claim 11 also comprises:

First register file, this first register file are communicated by letter with described first processor and are stored the first thread information that is used for described first processor; And

Second register file, this second register file and described second processor communication and storage are used for the second thread information of described second processor, and the wherein said first and second thread information comprise register, checkpoint and programmable counter at least a of the described thread that is used for described first and second processors respectively.

15. SOC (system on a chip) that comprises described first and second processors of claim 14 and described first and second register files.

16. disposal system as claimed in claim 14, wherein said control module with described thread when described first processor is transferred to described second processor, described thread information is transferred to described second register file from described first register file.

17. disposal system as claimed in claim 11, wherein said first processor comprises the first transistor, and described second processor comprises transistor seconds, and described the first transistor has higher leakage current than described transistor seconds.

18. disposal system as claimed in claim 11, wherein said first processor comprises the first transistor, and described second processor comprises transistor seconds, and described transistor seconds has bigger size than described the first transistor.

19. disposal system as claimed in claim 11, wherein said disposal system are in high-power mode when described first processor is in active state, be in low-power mode when described first processor is inactive.

20. disposal system as claimed in claim 11, wherein said first and second processors comprise first and second Graphics Processing Unit respectively.

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