CN101110260A - Memory Selective Precharge Circuit with Charge Compensation Structure - Google Patents

Abstract

The invention discloses a memory selective precharging circuit with charging compensation structure, its selective precharging unit includes a precharging transistor M _p1 and two or more bit line selection transistors M _pi , the charging compensation unit includes The charge compensation tube M _p2 and the second inverter inv ₂ , the source terminal of the precharge tube M _p1 is connected to the power supply, and the drain terminal is connected to the internal circuit, the precharge tube M _p1 is controlled by the precharge signal F _pre , and each bit line selection tube One end of M _ni is connected to the bit line in the storage array, and the other end is connected to the drain end of the precharge transistor M _p1 and the charge compensation transistor M _p2 , the second inverter inv ₂ of the charge compensation unit, and the first inverter of the output drive unit. The input terminal of the phase device inv ₁ , the source terminal of the charging compensation tube M _p2 is connected to the power supply, and the drain terminal is connected to the internal circuit. The M _p2 tube is controlled by the output terminal of the second inverter inv ₂ , and the input terminal of the second inverter inv ₂ The end is connected to the drain end of the pre-charging tube M _p1 and the charging compensation tube M _p2 . The invention has a simple structure, can shorten the time cost of the charging stage of the bit line, and improve the data reading speed of the memory.

Description

Memory Selective Precharge Circuit with Charge Compensation Structure

technical field

The invention mainly relates to the design field of low-power memory, in particular to a memory selective precharging circuit with a charging compensation structure.

Background technique

As the density and operating frequency of integrated circuits continue to increase as described by Moore's Law, the design of low-power systems has become the focus of designers. In a microprocessor, especially a SoC (System on a Chip), since the memory occupies a large part of the power consumption of the chip, the design technology of the low-power memory is of great significance to the development of the integrated circuit. With the extensive use of embedded memories in high-performance processors, there are high requirements for the performance of the memory in terms of speed, area and power consumption. However, due to the mutual constraints among these three parameters, memory low-power consumption techniques often cause speed and area overhead. Therefore, it is a difficult point in the design of memory low power consumption technology to exchange low overhead for low power consumption performance.

For memory chips, the sources of power consumption can be divided into three aspects: memory cell arrays, decoders and peripheral circuits. The power consumption of the memory cell array is the main source of memory power consumption. For a memory with n rows and m columns, its structure is shown in Figure 1, and the power consumption can be approximated by the following formula:

P＝V _DD I _DD

＝(mi _act +m(n-1)i _hld )+((n+m)C _DE V _int f)+(C _PT V _int f)

Where i _act is the equivalent effective current of the selected cell, which is the ratio of the total charge flowing through the memory cell in a read or write operation to the read/write cycle, i _hld is the data maintenance current of the non-working cell, V _int is the internal power supply voltage , C _DE is the equivalent output load of each decoder, C _PT is the total load of the peripheral circuit, f is the operating frequency.

In today's on-chip embedded memory, in order to achieve high speed and low power consumption, the memory cell array mostly adopts a dynamic precharge structure. Therefore, the power consumption of the memory cell array is mainly the power consumption of charging and discharging the bit line capacitance in the memory cell array. The estimation formula of its power consumption is as follows;

P _array ＝m×i _act ×V _DD ＝m×C _eff ×V _DD ² ×f

Wherein, m is the number of bit lines that need to be charged and discharged in one read operation, C _eff is the equivalent effective capacitance of each bit line, V _DD ² is the power supply voltage, and f is the operating frequency. It can be seen from the formula that, for a memory whose manufacturing process, capacity and performance requirements are determined, in order to reduce the power consumption of the memory array, it can only be achieved by reducing the number m of bit lines participating in the charging and discharging process.

The selective precharge structure is shown in FIG. 2 , in which circuit 10 is a memory cell array, circuit 20 is a selective bit line precharge unit, and circuit 30 is an output drive circuit. In the selective bit line precharge unit, the PMOS transistor M _p1 is a traditional precharge transistor. The source of M _p1 is connected to the power supply, and the drain is connected to the internal circuit. M _p1 is controlled by the precharge signal F _pre . When F _pre When F _pre is at a high level, the pre-charging tube is turned off, and the path from the power supply to the internal circuit is cut off. The NMOS transistors _Mn1 to _Mn16 are bit line selection transistors, and the number of bit line selection transistors varies according to the organizational form of the memory array, and may be two or more. One end of each bit line selection transistor is connected to the bit line in the memory array, and the other end is connected to the drain end of the precharge transistor M _p1 and the input end of the inverter in the output driving circuit. The bit line selection transistors are controlled by the decoding result signals s ₁ to s ₁₆ of the column decoder. When the memory enters the pre-charging stage, F _pre is low level, and the column decoder performs decoding work at the same time. When the column decoder completes decoding, one of the corresponding signals s ₁ to s ₁₆ will jump from low level At this time, the corresponding bit line selection tube is turned on, and the bit line connected to it is connected with the pre-charging tube M _p1 , and the pre-charging tube M _p1 starts to charge the bit line. When the memory completes the pre-charging process and enters the data-reading phase, F _pre jumps to a high level to turn off the pre-charging transistor M _p1 , and at the same time, the bit line selection transistor opened during the pre-charging phase remains on, and the The bit line is discharged or not discharged according to the content stored in the memory cell. If the bit line is discharged, the bit line is low, so the input terminal of the inverter in the output drive circuit is low, thereby outputting a high level "1" signal at the output; if the bit line is not discharged, it remains It is a high-level state in the pre-charging stage, so the input terminal of the inverter in the output drive circuit is high-level, so that a low-level "0" signal is output at the output terminal. The working sequence of the circuit is shown in Figure 3.

In the circuit structure of Figure 2, the number of bit lines involved in charging and discharging can be reduced to 1/16 of the common structure through the bit line selection unit of 16 to 1, thereby reducing the working power consumption of the memory cell array to only 1 /16 or so. It can be seen that the selective precharging structure has a very obvious power consumption optimization effect. However, it can be seen from the working timing diagram that in order to ensure that the bit line can be precharged correctly, this structure will bring nearly double the overhead of data reading time (t ₂ ≈t ₁ ), which is obvious for high-speed memories is unacceptable.

Contents of the invention

The problem to be solved by the present invention is that: aiming at the technical problems existing in the prior art, the present invention provides a charging compensation structure with a simple structure, which can greatly shorten the time overhead of the bit line charging stage, thereby improving the memory data reading speed memory selective precharge circuit.

In order to solve the above-mentioned technical problems, the solution proposed by the present invention is: a memory selective pre-charging circuit with a charging compensation structure, characterized in that it includes a selective pre-charging unit, a charging compensation unit and an output drive unit, the The selective pre-charging unit includes a pre-charging tube M _p1 and two or more bit line selection tubes M _ni , the charging compensation unit includes a charging compensation tube M _p2 and a second inverter inv ₂ , and the charging compensation tube M _p1 The source end is connected to the power supply, the drain end is connected to the internal circuit, the charge compensation transistor M _p1 is controlled by the precharge signal F _pre , one end of each bit line selection transistor M _ni is connected to the bit line in the memory array, and the other end is connected to the precharge The drain terminals of the tube M _p1 and the charging compensation tube M _p2 , the second inverter inv ₂ of the charging compensation unit, the input terminal of the first inverter inv ₁ of the output drive unit, and the source terminal of the charging compensation tube M _p2 are connected to Power supply, the drain end is connected to the internal circuit, the M _p2 tube is controlled by the output end of the second inverter inv ₂ , the input end of the second inverter inv ₂ is connected to the drain end of the pre-charging tube M _p1 and the charging compensation tube M _p2 connect.

The charging compensation unit is connected with an equivalent capacitor C _d .

Compared with the prior art, the present invention has the advantages of:

1. Since the present invention adopts a charging compensation structure circuit, compared with the common selective precharging structure, the time cost t ₂ of the bit line charging stage can be greatly shortened, thereby improving the data reading speed of the memory.

2. The charging process of the bit line is controlled by the bit line selection tube, and the bit line capacitance that does not participate in data reading is not charged and discharged, thereby avoiding the waste of power consumption when reading data.

3. Introduce a charging compensation circuit, which not only ensures the correctness of pre-charging but also shortens the time spent in the charging phase.

Description of drawings

Figure 1 is a memory structure block diagram and a schematic diagram of power consumption sources;

FIG. 2 is a schematic circuit diagram of an existing selective precharging structure;

FIG. 3 is a schematic diagram of a working sequence of an existing selective precharging circuit;

Fig. 4 is a structural framework schematic diagram of the present invention;

Fig. 5 is the specific circuit diagram of the present invention;

Fig. 6 is a schematic diagram of the workflow of the present invention

Fig. 7 is a schematic diagram of the working sequence of the circuit of the present invention.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

As shown in Fig. 4 and Fig. 5, the memory selective precharge circuit with charge compensation structure of the present invention adds a charge compensation unit on the basis of traditional selective precharge structure, and it comprises selective precharge unit, charging A compensation unit and an output drive unit, the selective pre-charging unit includes a pre-charging transistor M _p1 and two or more bit line selection transistors M _ni , and the charging compensation unit includes a charging compensation transistor M _p2 and a second inverter inv ₂ , the source end of the precharge tube M _p1 is connected to the power supply, the drain end is connected to the internal circuit, the precharge tube M _p1 is controlled by the precharge signal F _pre , and one end of each bit line selection transistor M _ni is connected to the memory array The other end of the bit line is connected to the drain end of the pre-charging transistor M _p1 and the charging compensation transistor M _p2 , the second inverter inv ₂ of the charging compensation unit, and the input end of the first inverter inv ₁ of the output driving unit to charge The source end of the compensation tube M _p2 is connected to the power supply, and the drain end is connected to the internal circuit. The M _p2 tube is controlled by the output end of the second inverter inv ₂ , and the input end of the second inverter inv ₂ is connected to the precharge tube M _p1 It is connected to the drain end of the charging compensation tube M _p2 .

As shown in Fig. 5, it is an application example of the present invention in a 16-to-1 bit line selection structure, wherein circuit 10 is a memory cell array, w ₁ to w ₆₄ are memory array word lines, and capacitors C _BL1 to C _BL16 represent The equivalent capacitance of each memory array bit line. Circuit 20 is a selective pre-charging circuit with a charging compensation structure proposed by the present invention. Among them, the NMOS transistors _Mn1 to _Mn16 adopt traditional bit line selection transistors, and select corresponding bit lines according to the result of the column decoder, and the capacitance C _d is the circuit equivalent capacitance of this structure. The circuit 30 is a circuit of an output drive unit.

In the circuit, the PMOS transistor M _p1 is a traditional pre-charging tube. The source of M _p1 is connected to the power supply, and the drain is connected to the internal circuit. M _p1 is controlled by the pre-charging signal F _pre . When F _pre is low, the pre-charging The charging tube is turned on to start charging the circuit. When F _pre is high level, the pre-charging tube is turned off, cutting off the path from the power supply to the internal circuit. The NMOS transistors _Mn1 to _Mn16 are bit line selection transistors, and the number of bit line selection transistors varies according to the organizational form of the memory array, and may be two or more. One end of each bit line selection transistor is connected to the bit line in the storage array, and the other end is connected to the drain end of the precharge transistor M _p1 and the charging compensation transistor M _p2 , the inverter inv ₂ of the charging compensation circuit, and the inverter in the output drive circuit. The input terminal of the phase device inv ₁ . The bit line selection transistors are controlled by the decoding result signals s ₁ to s ₁₆ of the column decoder. The charging compensation tube M _p2 and its driving inverter inv ₂ are innovative structures proposed by the present invention. The connection mode of M _p2 is roughly the same as that of M _p1 . The source end is connected to the power supply, and the drain end is connected to the internal circuit _. Controlled by the output terminal of the inverter inv ₂ , the input terminal of the inverter inv ₂ is connected to the drain terminals of the pre-charging transistor M _p1 and the charging compensation transistor M _p2 . Therefore, in the memory pre-charging stage, the input terminal of the inverter _inv2 is charged to a high level, and the low level of its output can turn on the charging compensation transistor M _p2 , so that after the pre-charging transistor M _p1 is turned off The charging compensation tube M _p2 can still charge the internal circuit.

The operation flowchart of the present invention is shown in Figure 6, and the timing relationship of each signal in the circuit is shown in Figure 7, wherein _sn and _wm are word lines and bit lines selected after column decoder and row decoder decoding respectively Select signal, C _BLn is the equivalent capacitance of the selected bit line. As shown in Figure 6, the operation flow of this circuit can be divided into three stages:

1. Pre-charging tube (M _p1 ) turn-on phase (t ₁ in the timing diagram): When the pre-charging operation starts, the pre-charging signal (F _pre ) jumps to a low level to turn on the pre-charging tube (M _p1 ) for The circuit equivalent capacitance (C _d ) is precharged. At this time, the row decoder and the column decoder of the memory decode the address, and the word line (w _m ) and bit line selection signals (s _n ) in the memory array are kept at low level. Since (s _n ) is at low level, the bit line selection transistor is turned off, and the bit line is not precharged at this stage.

2. Bit line precharging phase (t ₂ in the timing diagram): the column decoder produces a result t ₂ before the row decoder. At this time, according to the result of the column decoder, the corresponding bit line selection signal (s _i ) jumps up, and its jump edge turns on the corresponding bit line selection transistor (M _ni ), so that the precharge circuit and the selected bit line connect. At the same time, the precharge signal (F _pre ) remains low, and the precharge transistor (M _p1 ) continues to conduct and charge the equivalent capacitance of the bit line together with the charge compensation transistor (M _p2 ). The bit lines not selected by the bit line selection signal are not charged.

3. The pre-charge tube (M _p1 ) off stage (t ₃ in the timing diagram): the row decoder completes the decoding operation, and the corresponding word line (w _i ) jumps up to select the memory cell. At the same time, the precharge signal (F _pre ) jumps to a high level to turn off the precharge tube (M _p1 ). At this time, if the memory cell stores a "1" signal, the NMOS transistor of the memory cell connects the bit line to the ground line, and starts to discharge the bit line equivalent capacitance (C _BLj ). Since the drive capability of the NMOS tube of the storage unit is greater than that of the charging compensation tube (M _p2 ), the bit line will be discharged to a low level, and the output drive inverter (inv ₁ ) outputs a "1"signal; if the storage unit stores " 0” signal, then there is no connection path between the bit line and the ground line, the charging compensation tube (M _p2 ) continues to charge the bit line to the power supply voltage, and the output drives the inverter (inv ₁ ) to keep outputting a “0” signal.

Claims (2)

1. A memory selective precharge circuit with charge compensation structure is characterized in that: it comprises selective precharge unit, charge compensation unit and output drive unit, and said selective precharge unit comprises precharge tube M _p1 and Two or more bit line selection transistors M _ni , the charging compensation unit includes a charging compensation transistor M _p2 and a second inverter inv ₂ , the source terminal of the charging compensation transistor M _p1 is connected to the power supply, and the drain terminal is connected to the internal circuit , the charge compensation transistor M _p1 is controlled by the precharge signal F _pre , one end of each bit line selection transistor M _ni is connected to the bit line in the memory array, and the other end is connected to the drain terminals of the precharge transistor M _p1 and the charge compensation transistor M _p2 And the input end of the second inverter inv ₂ of the charge compensation unit and the first inverter inv ₁ of the output drive unit, the source end of the charge compensation tube M _p2 is connected to the power supply, the drain end is connected to the internal circuit, and the M _p2 tube Controlled by the output terminal of the second inverter inv ₂ , the input terminal of the second inverter inv ₂ is connected to the drain terminals of the pre-charging transistor M _p1 and the charging compensation transistor M _p2 . 2. The memory selective precharging circuit with a charge compensation structure according to claim 1, wherein the charge compensation unit is connected to an equivalent capacitor _Cd .

Images