CN101097559A - A system and method for realizing interface and interconnection between main processor and coprocessor - Google Patents

Abstract

The invention discloses a system for realizing the interface and interconnection of a main processor and a coprocessor, including a main processor, at least one coprocessor, a dual-port data memory, a main processor data bus, a coprocessor data bus, at least A command word register and at least one status word register. The invention also discloses a method for realizing the interface and interconnection between the main processor and the coprocessor, comprising: A. the main processor writes the data to be transmitted to the coprocessor into a designated storage area in the dual-port data memory, And send the coprocessor startup instruction to the coprocessor; B. After the coprocessor receives the startup instruction, return the command reception status word to the main processor, and access the designated storage area in the dual-port data memory to obtain the data written by the main processor , execute the operation defined in the start instruction; C. After the coprocessor completes the operation defined in the instruction, it returns the command completion status word to the main processor, and the main processor obtains the execution result of the coprocessor.

Description

A system and method for realizing interface and interconnection between main processor and coprocessor

technical field

The invention relates to the technical field of computer architecture and VLSI design, in particular to a system and method for realizing the interface and interconnection of a main processor and a coprocessor.

Background technique

A coprocessor is a processor that extends the main processor and assists the main processor in completing special application processing for different applications and requirements. Such as floating-point arithmetic coprocessor, multimedia coprocessor, etc.

Coprocessors are programmable. The coprocessor has a coprocessor instruction set expanded on the basis of the main processor instruction set, and the coprocessor contains application-specific functional units that can be used to accelerate the processing of a specific application.

Traditionally, the interface between the main processor and the coprocessor adopts a relatively complex and tightly coupled method. For example, Advanced RISC Machines (ARM) and its coprocessor interface are interconnected and communicated through a dedicated coprocessor interface. The interface of the coprocessor includes the following four types of signals: clock signal, clock control signal, pipeline follow signal and handshake signal. ARM coprocessors use the same clock signal as the ARM processor. The coprocessor has its own pipeline. The coprocessor uses a pipeline follower through the coprocessor interface connected to the ARM processor to track the instructions executed in the ARM core pipeline and keep the two pipelines in sync.

However, the existing main processor and coprocessor interface and interconnection structure have some unavoidable inherent defects. For example, the compatibility is not strong, and it can only support specific main processors and coprocessors; the granularity of data processing by coprocessors is relatively fine, and it can only effectively process a single data word, and cannot support coarser granularity data processing ; The coprocessor and the main processor share a pipeline, and the two cannot run in parallel at the same time; it does not support flexible coprocessor instruction set design, etc.

Contents of the invention

(1) Technical problems to be solved

Aiming at the deficiencies in the above-mentioned prior art, a main purpose of the present invention is to provide a system for realizing the interface and interconnection between the main processor and the coprocessor, so as to improve the compatibility between the main processor and the coprocessor, so that The coprocessor can support data processing of various granularities, and enables the coprocessor and the processor to run in parallel, and supports flexible coprocessor instruction set design.

Another main purpose of the present invention is to provide a method for realizing the interface and interconnection between the main processor and the coprocessor, so as to improve the compatibility between the main processor and the coprocessor, so that the coprocessor can support various granularities data processing, and enables coprocessors and processors to run in parallel, supporting flexible coprocessor instruction set design.

(2) Technical solution

In order to achieve the above object, technical solution of the present invention is achieved in that way:

A system for interfacing and interconnecting a main processor and a coprocessor, comprising a main processor and at least one coprocessor, the system further comprising:

a dual-port data memory for realizing data communication between the main processor and at least one coprocessor;

a main processor data bus for connecting the main processor and a dual-port data memory;

a coprocessor data bus for connecting the dual-port data memory with the at least one coprocessor;

At least one command word register for sending instructions received from the main processor to a coprocessor connected to itself;

At least one status word register for sending status information received from the coprocessor to the main processor.

The dual-port data memory includes: a data access port connected to the main processor through the main processor data bus; a data access port connected to at least one coprocessor through the coprocessor data bus; The address decoding logic circuits corresponding to the two data access ports.

The two data access ports of the dual-port data memory respectively at least include: a clock signal, a control signal, an address signal and a data signal.

The main processor simultaneously reads or writes to different storage areas of the dual-port data memory through the data access port connected to itself and the coprocessor through the data access port connected to itself.

Described main processor is the main processor of Harvard structure; Described main processor data bus is the data bus of Harvard structure main processor, is used to connect the main processor of described Harvard structure and a data access of dual-port data memory port; the coprocessor data bus is used to connect the at least one coprocessor with another data access port of the dual-port data memory.

There is a one-to-one correspondence between the command word registers and the coprocessors; the main processor accesses all the command word registers by performing a write operation, and the coprocessor accesses the command word registers corresponding to itself by performing a read operation.

There is a one-to-one correspondence between the status word registers and the coprocessors; the main processor accesses all the status word registers by performing a read operation, and the coprocessor accesses the status word registers corresponding to itself by performing a write operation.

A method for interfacing and interconnecting a host processor and a coprocessor, the method comprising:

A. The main processor writes the data to be delivered to the coprocessor into the designated storage area in the dual-port data memory, and sends the coprocessor start command to the coprocessor;

B. After the coprocessor receives the startup instruction, it returns the command reception status word to the main processor, accesses the designated storage area in the dual-port data memory to obtain the data written by the main processor, and executes the operation defined in the startup instruction;

C. After the coprocessor completes the operation defined in the instruction, it returns the command completion status word to the main processor, and the main processor obtains the execution result of the coprocessor.

The main processor described in the step A writes the data that needs to be delivered to the coprocessor into the designated storage area in the dual-port data memory, and accesses the dual-port data through a data access port of the main processor data bus and the dual-port data memory implemented in a specified memory area in memory.

In step A, the main processor sending the coprocessor startup instruction to the coprocessor includes: the main processor sends the coprocessor startup instruction to the coprocessor through the command word register, which at least carries the information of executing the defined operation and accessing the designated storage area .

In step B, the coprocessor returns the command receiving status word to the main processor through the status word register.

In step B, after the coprocessor returns the command receiving status word to the main processor, it further includes: the main processor executes a normal program flow according to the received command receiving status word.

After the coprocessor described in the step C completes the operation defined in the instruction, the execution result is further carried in the command completion status word, the coprocessor described in the step C returns the command completion status word to the main processor, and the main processor obtains the coprocessor The processor's execution results include:

C1. The coprocessor sends the command completion status word carrying the execution result to the main processor through the status word register;

C2. The main processor receives the command completion status word sent by the coprocessor, and obtains the execution result returned by the coprocessor from the command completion status word.

After the coprocessor described in the step C completes the operation defined in the instruction, the execution result data is further written into the specified storage area in the dual-port data memory, and the coprocessor described in the step C returns the command completion status word to the main processor, The execution results obtained by the main processor from the coprocessor include:

C1', the coprocessor sends a command to the main processor through the status word register to complete the status word;

C2'. The main processor receives the command completion status word, accesses the specified storage area in the dual-port data memory, and obtains the execution result data written by the coprocessor.

(3) Beneficial effects

As can be seen from the foregoing technical solutions, the present invention has the following beneficial effects:

1. Utilize the present invention, because main processor and coprocessor utilize respective data bus and pipeline respectively, so main processor can be interconnected and cooperate with various types of coprocessors, greatly improve main processor and coprocessor. Compatibility between processors.

2. Utilizing the present invention, since the coprocessor can both perform fine-grained data processing of a single data word and coarse-grained data processing of multiple data words when performing data processing, the coprocessor can support various granularity data processing.

3. Utilize the present invention, because main processor and coprocessor adopt the mechanism of time-sharing access to the specific area of dual-port data memory, coprocessor can not affect the process of the access operation of data memory and the execution operation of main processor to data memory. The access operation of the data memory and the process of executing the operation, the timing of the two accessing the data memory will not affect each other, and the main processor can also execute the program flow normally while the coprocessor is performing the operation, so the main processor and the coprocessor Can run in parallel.

4. Using the present invention, the main processor and the coprocessor can also obtain high data access bandwidth through the dual-port data memory, and the coprocessor can also support flexible coprocessor instruction set design.

5. With the present invention, the main processor only sends a coprocessor instruction at a time, that is, only one coprocessor operates and may access the coprocessor data bus, and at any moment there is only one coprocessor to the coprocessor The data bus is accessed, so there is no problem of coprocessor data bus access conflicts.

6. With the present invention, the main processor will not start other coprocessors until the coprocessor completes the specific operation defined by the coprocessor instruction and returns the status. In this way, at a certain moment, only the main processor and one coprocessor work at the same time, and there is no situation that multiple coprocessors work at the same time, so there is no problem of operation conflict between coprocessors.

Description of drawings

Fig. 1 is the schematic diagram of the system that realizes main processor and N coprocessor interfaces and interconnection provided by the present invention;

Fig. 2 is the schematic diagram of the system that realizes main processor and a coprocessor interface and interconnection provided by the present invention;

Fig. 3 is the realization flow chart of realizing main processor and coprocessor interface and interconnection overall technical scheme provided by the present invention;

4 is a flow chart of a method for realizing the interface and interconnection between the main processor and the coprocessor according to the first embodiment of the present invention;

FIG. 5 is a flowchart of a method for implementing the interface and interconnection between the main processor and the coprocessor according to the second embodiment of the present invention.

Detailed ways

In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

As shown in Figure 1, Figure 1 is a schematic diagram of a system for realizing the interface and interconnection between the main processor and N coprocessors provided by the present invention, the system includes a main processor and at least one coprocessor, and the system also includes :

a dual-port data memory for realizing data communication between the main processor and at least one coprocessor;

a main processor data bus for connecting the main processor and a dual-port data memory;

a coprocessor data bus for connecting the dual-port data memory with the at least one coprocessor;

At least one command word register for sending instructions received from the main processor to a coprocessor connected to itself;

At least one status word register for sending status information received from the coprocessor to the main processor.

The above-mentioned main processor is a main processor of Harvard structure, has independent data memory and program memory, and is respectively connected with the data bus and the program bus, fetches instructions and executes in parallel and independently.

Wherein, in order to distinguish the data bus of the main processor from the data bus of the coprocessor, it is identified as the main processor data bus, and the data bus of the coprocessor is identified as the coprocessor data bus.

The dual-port data memory is extended from the original single-port memory of the main processor, and the main processor and the coprocessor perform data communication through the dual-port data memory. The dual-port data memory includes: a data access port connected to the main processor through the main processor data bus, i.e. data access port A; a data access port connected to at least one coprocessor through the coprocessor data bus port, that is, data access port B; and an address decoding logic circuit corresponding to the two data access ports.

The dual-port data memory has two sets of completely independent data access ports and corresponding address decoding logic circuits. The data access port A and the data access port B of the dual-port data memory are independent of each other. The data access port A and the data access port B respectively at least include: a clock signal, a control signal, an address signal, a data signal, and the like.

The main processor data bus is connected to the data access port A of the dual-port data memory, and the main processor accesses the dual-port data memory through the main processor data bus and the data access port A. Data access port A of the dual-port data memory remains connected to the main processor data bus.

The coprocessor data bus is connected to the data access port B of the dual-port data memory, and the coprocessor accesses the dual-port data memory through the coprocessor data bus and the data access port B. The data access port B of the dual-port data memory is connected to the coprocessor data bus, and multiple coprocessors are connected in parallel through the coprocessor data bus.

Since the main processor only issues one coprocessor instruction at a time, that is, only one coprocessor operates and may access the coprocessor data bus, so at most one coprocessor can access the coprocessor data bus at any time , so there will be no access conflicts on the coprocessor data bus.

Since the main processor can only start one coprocessor at most at a time, there will not be multiple coprocessors working at the same time on the coprocessor data bus, competing for bus resources, and the coprocessors have their own address decoding logic.

The two sets of data access ports of the dual-port data memory can work independently at different clock frequencies, and can simultaneously access the dual-port data memory. However, if a specific storage area of the dual-port data memory is read and written at the same time, the access may fail. In order to ensure correct and effective data communication, in the present invention, the access of the main processor and the coprocessor to the dual-port memory is carried out in time division.

The main processor accesses port A through data, and the coprocessor accesses port B through data, and simultaneously performs read or write operations on different storage areas of the dual-port data memory. However, the main processor accesses port A through data, and the coprocessor accesses port B through data, so they cannot read and write the same storage unit of the dual-port data memory at the same time.

When the main processor issues a coprocessor command to start the coprocessor, the coprocessor command specifies the memory area that the coprocessor can access. When the coprocessor accesses this memory area, the operation of the coprocessor does not affect the normal execution of the program flow of the main processor, but the main processor can only access other memory areas except the designated coprocessor access area. When the coprocessor completes the access to the designated memory area and executes the corresponding operation, it will return the command completion status word to the main processor. The main processor can only access the memory area accessed by the designated coprocessor after receiving the command completion status word.

When performing data communication between the main processor and the coprocessor, the main processor first writes the data to be transmitted to the coprocessor into a specific memory area of the dual-port data memory, and starts the main processor. After the main processor sends the coprocessor instruction and starts the coprocessor to work, the coprocessor can access the specific memory area of the dual-port data memory through the coprocessor data bus and port B of the dual-port memory to read in the operation data and operate Write data when done. At this time, the main processor cannot access this memory area. Only when the coprocessor completes the access to the data memory and returns the command completion status word, and the main processor receives the command completion status word, the main processor can access the dual A specific memory area of the port data memory is accessed. The main processor obtains the data written by the coprocessor by accessing a specific memory area of the dual-port data memory, and completes the data communication between the main processor and the coprocessor.

The command word registers are in one-to-one correspondence with the coprocessors, the main processor accesses all the command word registers by performing a write operation, and the coprocessor accesses the command word registers corresponding to itself by performing a read operation.

The status word registers are in one-to-one correspondence with the coprocessors, the main processor accesses all the status word registers by performing a read operation, and the coprocessor accesses the status word registers corresponding to itself by performing a write operation.

The main processor transmits coprocessor instructions to the coprocessor through the command word register, and the coprocessor returns the status to the main processor through the status word register combined with the interrupt request signal. The command word register transmits the coprocessor instruction issued from the main processor to the coprocessor, and the status word register transmits the status returned from the coprocessor to the main processor. At the same time, the status return of the coprocessor is combined with the external interrupt of the main processor.

The N command word registers and N status word registers in Fig. 1 are all addressable and accessible by the main processor. But the coprocessor can only address and access a command word register and a status word register to which it belongs. For example, coprocessor N can only access command word register N and status word register N.

At the same time, the main processor can only read the status word register, and the coprocessor can only write to the status word register; the main processor can only write to the command word register, and the coprocessor can only write to the command word register. to perform a read operation.

There is also a one-to-one correspondence between the interrupt request signal and the interrupt response signal. For example, the interrupt request signal N in FIG. 1 corresponds to the interrupt response signal N. The interrupt request signal and the interrupt response signal belong to the main processor and correspond to N external interrupts respectively, for example, the interrupt request signal N and the interrupt response signal N correspond to the external interrupt N of the main processor. Each coprocessor is allocated an external interrupt resource, and is connected with an interrupt request signal and an interrupt response signal respectively. For example, coprocessor N is connected to interrupt request signal N and interrupt response signal N. The coprocessor N is connected to the main processor through the interrupt application signal N and the interrupt response signal N and can apply for the external interrupt N of the main processor. When the coprocessor sends an external interrupt request, the main processor enters the corresponding interrupt of the external interrupt N. Interrupt service routine execution.

The process of the main processor sending a command to the coprocessor is: the main processor is in the process of executing the normal program flow, if it needs to start the coprocessor N to perform a certain operation, write the command word R into the command word register . Among them, the command word R defines the operation type of the coprocessor and the accessible memory area specified by the main processor. The N coprocessors connected with the main processor are all in the command query state when they do not receive the command, and constantly query the command word register. If a coprocessor N in the coprocessor finds that the value in the command word register N is a coprocessor instruction R that it can recognize and execute, it will return the command receiving status word and start the corresponding coprocessor operation . The main processor will not start other coprocessors until coprocessor N completes the specific operation defined by coprocessor instruction R and returns status. In this way, at a certain moment, only the processor and one coprocessor work at the same time, and there will be no situation that multiple coprocessors work at the same time, so there will be no problem of operation conflict between coprocessors.

The process for the coprocessor to return the state to the main processor is: when the coprocessor N initiates the state return to the main processor, the coprocessor N sends the interrupt request signal after writing the status word S into the status word register N. N is asserted so that processor N can respond and process immediately. The state word S defines the state returned by the coprocessor N to the main processor.

After the main processor receives the interrupt request N, the interrupt controller judges whether to receive the interrupt according to conditions such as the interrupt mask bit and the interrupt priority. If an interrupt request N is received, the host processor will assert the interrupt response signal N. After the coprocessor N in the waiting state for interrupt application detects that the interrupt response N signal is valid, it cancels the interrupt application signal N.

Based on the schematic diagram of the present invention shown in Fig. 1 realizing the main processor and N coprocessor interfaces and the interconnection system, Fig. 2 shows the implementation of the main processor and a coprocessor interface and interconnection provided by the present invention Schematic diagram of the system.

The interface and interconnection structure of the main processor and a coprocessor is a special case of the connection structure between the main processor and N coprocessors in FIG. 1 when N=1. In the structure where the main processor and N coprocessors are interfaced and interconnected, multiple coprocessors will not work at the same time. At a certain moment, only the main processor and one coprocessor are working in parallel at the same time. There is no data communication between coprocessors and coprocessors, and resource access conflicts do not occur between coprocessors. Therefore, in the interface and interconnection structure of the main processor and a coprocessor, the communication mode between the main processor and the coprocessor is completely consistent with that in the interface and interconnection structure of the main processor and N coprocessors.

A schematic diagram of a system for realizing the interface and interconnection between the main processor and N coprocessors based on the present invention shown in Figure 1, and the system for realizing the interface and interconnection between the main processor and a coprocessor shown in Figure 2 Fig. 3 shows the implementation flowchart of the overall technical solution for the interface and interconnection between the main processor and the coprocessor provided by the present invention, and the method includes the following steps:

Step 301: the main processor writes the data to be delivered to the coprocessor into a specified storage area in the dual-port data memory, and sends a coprocessor start instruction to the coprocessor;

Step 302: After the coprocessor receives the startup instruction, it returns the command reception status word to the main processor, accesses the designated storage area in the dual-port data memory to obtain the data written by the main processor, and executes the operations defined in the startup instruction;

Step 303: After the coprocessor completes the operation defined in the instruction, it returns the command completion status word to the main processor, and the main processor obtains the execution result of the coprocessor.

The main processor described in the above step 301 writes the data that needs to be delivered to the coprocessor into the designated storage area in the dual-port data memory, and accesses the dual-port through a data access port of the main processor data bus and the dual-port data memory. implemented in a specified memory area in data memory.

The main processor sending the coprocessor startup instruction to the coprocessor in the above step 301 includes: the main processor sends the coprocessor startup command to the coprocessor through the command word register, which carries at least the information of executing the defined operation and accessing the designated storage area. instruction.

The command receiving status word returned by the coprocessor to the main processor in the above step 302 is returned through the status word register.

After the coprocessor in step 302 returns the command receiving status word to the main processor, it further includes: the main processor executes a normal program flow according to the received command receiving status word.

After the coprocessor in step 303 above completes the operations defined in the instruction, the main processor can obtain the execution result in the following two ways:

Mode 1: After the coprocessor completes the operation defined in the instruction, it further carries the execution result in the command completion status word, the coprocessor returns the command completion status word to the main processor, and the main processor obtains the execution result of the coprocessor include:

Step 3031: the coprocessor sends the command completion status word carrying the execution result to the main processor through the status word register;

Step 3032: The main processor receives the command completion status word sent by the coprocessor, and obtains the execution result returned by the coprocessor from the command completion status word.

Mode 2: After the coprocessor completes the operation defined in the instruction, it further writes the execution result data into the designated storage area in the dual-port data memory, and the coprocessor returns the command completion status word to the main processor, and the main processor obtains the coprocessor The processor's execution results include:

Step 3031': the coprocessor sends the command completion status word to the main processor through the status word register;

Step 3032': The main processor receives the command completion status word, accesses the specified storage area in the dual-port data memory, and obtains the execution result data written by the coprocessor.

Below, based on the implementation flow diagram of the overall technical solution for realizing the main processor and coprocessor interface and interconnection provided by the present invention shown in Figure 3, the main processor and a coprocessor interface and interconnection shown in Figure 2 Taking the system as an example, the interface and interconnection method of the processor and coprocessor in the present invention will be described in detail.

As shown in FIG. 4, FIG. 4 is a flowchart of a method for realizing the interface and interconnection between the main processor and the coprocessor according to the first embodiment of the present invention. The specific implementation steps of the method are as follows:

Step 401: start.

Step 402: Send a coprocessor start command. That is, the main processor sends a coprocessor start command R to the coprocessor through the command word register. The coprocessor start command R defines the specific operations that the coprocessor needs to perform and specifies the data memory area that the coprocessor can access.

Step 403: Return the command receiving status word. That is, the coprocessor sends a command to the main processor through the status word register to receive the status word S, and at the same time sets the interrupt request signal to be valid, indicating that the coprocessor has received the coprocessor start command, and starts the operation process defined by the coprocessor command R .

Step 404: cancel the coprocessor activation instruction. That is, the main processor receives the interrupt request signal valid, enters the interrupt service program corresponding to the external interrupt, receives the status word in the status word register, if the status word is the command receiving status word S, cancels the coprocessor start instruction, and the main processor Normal program flow begins, but no accesses can be made to the data memory region being accessed by the coprocessor.

Step 405: Return the command completion status word. That is, after the coprocessor completes the operation defined by the coprocessor instruction R, it carries the execution result in the command completion status word U, sends the command completion status word U to the main processor through the status word register, and simultaneously sets the interrupt request signal to be valid. Indicates that the coprocessor has completed the operation defined by the coprocessor instruction R, and returns the execution result information that needs to be returned after the operation is completed through the command completion status word U.

Step 406: Receive the command completion status word. That is, the main processor receives the interrupt request signal and enters the interrupt service program corresponding to the interrupt, receives the command completion status word U in the status word register, and the main processor extracts the required coprocessor return from the command completion status word U Execution result information.

In this step, the main processor can only access the specific storage area in the dual-port data memory after receiving the command completion status word U.

Step 407: end. A cycle of coprocessor execution ends.

In step 405 of the embodiment of the present invention, after the coprocessor completes the operation defined by the coprocessor instruction R, the execution result is carried in the command completion status word U, and the command completion status word is sent to the main processor through the status word register U, and at the same time set the interrupt request signal to be valid, indicating that the coprocessor has completed the operation defined by the coprocessor instruction R, and the execution result information that needs to be returned after the operation is completed is returned by the command completion status word U. In practical applications, the coprocessor can also further write the execution result data into a specified storage area in the dual-port data memory after completing the operations defined in the instruction. At this time, after receiving the command completion status word returned by the coprocessor, the main processor can obtain the execution result information of the coprocessor by accessing a designated storage area in the dual-port data memory.

The above-mentioned process can be referred to FIG. 5 for details. FIG. 5 is a flow chart of a method for realizing the interface and interconnection between the main processor and the co-processor according to the second embodiment of the present invention. The specific implementation steps of the method are as follows:

Step 501: start.

Step 502: Send a coprocessor start instruction. That is, the main processor sends a coprocessor start command R to the coprocessor through the command word register. The coprocessor start command R defines the specific operations that the coprocessor needs to perform and specifies the data memory area that the coprocessor can access.

Step 503: Return the command receiving status word. That is, the coprocessor sends a command to the main processor through the status word register to receive the status word S, and at the same time sets the interrupt request signal to be valid, indicating that the coprocessor has received the coprocessor startup command, and begins to perform the operation defined by the coprocessor command R buried.

Step 504: cancel the coprocessor activation instruction. That is, the main processor receives the interrupt request signal valid, enters the interrupt service program corresponding to the external interrupt, receives the status word in the status word register, if the status word is the command receiving status word S, cancels the coprocessor start instruction, and the main processor Normal program flow begins, but no accesses can be made to the data memory region being accessed by the coprocessor.

Step 505: Return the command completion status word. That is, after the coprocessor completes the operation defined by the coprocessor instruction R, it writes the execution result data into the specified storage area in the dual-port data memory, and sends a command to the main processor through the status word register to complete the status word U, and simultaneously sets The interrupt request signal is valid, indicating that the coprocessor has completed the operation defined by the coprocessor instruction R.

Step 506: Receive the command completion status word. That is, the main processor receives the interrupt request signal and enters the interrupt service program corresponding to the interrupt, receives the command completion status word U in the status word register, and accesses the designated storage area in the dual-port data memory according to the received command completion status word U, Get the execution result data written by the coprocessor.

Step 507: end. A cycle of coprocessor execution ends.

The specific embodiments described above have further described the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above descriptions are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present invention shall be included within the protection scope of the present invention.

Claims (14)

1, a kind of system that realizes primary processor and coprocessor interface and interconnection comprises a primary processor and at least one coprocessor, it is characterized in that this system also comprises:

Dual port data memory is used to realize the data communication between described primary processor and at least one coprocessor;

The primary processor data bus is used to connect described primary processor and dual port data memory;

The coprocessor data bus is used to connect dual port data memory and described at least one coprocessor;

At least one command word register, the instruction that is used for being received from described primary processor sends to the coprocessor that is connected with self;

At least one status word register, the status information that is used for being received from coprocessor sends to described primary processor.

2, the system of realization primary processor according to claim 1 and coprocessor interface and interconnection is characterized in that, described dual port data memory comprises:

The data access port that is connected with primary processor by described primary processor data bus;

The data access port that is connected with at least one coprocessor by described coprocessor data bus; With

With described two data access port corresponding address decoding logic circuits.

3, the system of realization primary processor according to claim 2 and coprocessor interface and interconnection, it is characterized in that two data access ports of described dual port data memory comprise respectively at least: clock signal, control signal, address signal and data-signal.

4, the system of realization primary processor according to claim 2 and coprocessor interface and interconnection is characterized in that,

The data access port of described primary processor by being connected with self, and the data access port of coprocessor by being connected with self are carried out read operation or write operation to the different storage zone of dual port data memory simultaneously.

5, the system of realization primary processor according to claim 1 and coprocessor interface and interconnection is characterized in that, described primary processor is the primary processor of Harvard structure;

Described primary processor data bus is the data bus of Harvard structure primary processor, is used to connect the primary processor of described Harvard structure and a data access port of dual port data memory;

Described coprocessor data bus is used to connect another data access port of described at least one coprocessor and dual port data memory.

6, the system of realization primary processor according to claim 1 and coprocessor interface and interconnection is characterized in that, described command word register is corresponding one by one with coprocessor;

Described primary processor conducts interviews to the complete order word register by carrying out write operation, and described coprocessor conducts interviews by carrying out the read operation pair command word register corresponding with self.

7, the system of realization primary processor according to claim 1 and coprocessor interface and interconnection is characterized in that, described status word register is corresponding one by one with coprocessor;

Described primary processor conducts interviews to whole status word registers by carrying out read operation, and described coprocessor conducts interviews by carrying out the write operation pair status word register corresponding with self.

8, a kind of method that realizes primary processor and coprocessor interface and interconnection is characterized in that this method comprises:

The data that A, primary processor pass to coprocessor with need write the designated storage area in the dual port data memory, and send the coprocessor enabled instruction to coprocessor;

B, coprocessor receive after the enabled instruction to primary processor return command accepting state word, and the designated storage area in the visit dual port data memory is obtained the data that primary processor writes, and carries out the operation that defines in the enabled instruction;

C, coprocessor are finished after the operation that defines in the instruction to primary processor return command completion status word, and primary processor obtains the execution result of coprocessor.

9, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection, it is characterized in that, the data that primary processor described in the steps A passes to coprocessor with need write the designated storage area in the dual port data memory, are to realize by the designated storage area in the data access port visit dual port data memory of primary processor data bus and dual port data memory.

10, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection is characterized in that, primary processor described in the steps A sends the coprocessor enabled instruction to coprocessor and comprises:

Primary processor sends to coprocessor by command word register and carries the coprocessor enabled instruction of carrying out defining operation and visit designated storage area domain information at least.

11, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection is characterized in that, coprocessor described in the step B returns by status word register to primary processor return command accepting state word.

12, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection is characterized in that, coprocessor described in the step B further comprises behind primary processor return command accepting state word:

Primary processor is carried out normal program flow according to the order accepting state word that receives.

13, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection is characterized in that, coprocessor described in the step C further is carried at execution result in the order completion status word after finishing the operation that defines in the instruction,

Coprocessor described in the step C is to primary processor return command completion status word, and the execution result that primary processor obtains coprocessor comprises:

C1, coprocessor send the order completion status word that carries execution result by status word register to primary processor;

C2, primary processor receive the order completion status word that coprocessor sends, and obtain the execution result that coprocessor returns from order completion status word.

14, the method for realization primary processor according to claim 8 and coprocessor interface and interconnection, it is characterized in that, coprocessor described in the step C is finished the designated storage area that further the execution result data is write after the operation that defines in the instruction in the dual port data memory

Coprocessor described in the step C is to primary processor return command completion status word, and the execution result that primary processor obtains coprocessor comprises:

C1 ', coprocessor send order completion status word by status word register to primary processor;

C2 ', primary processor receive order completion status word, and the designated storage area in the visit dual port data memory is obtained the execution result data that coprocessor writes.

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