CN101095232A - Input stage resistant against negative voltage swings - Google Patents

Abstract

A device (10) comprising a level shifter (15) connectable to a signal input (1) for receiving an input signal (s(t)) having a negative signal swing. The level shifter (15) provides a DC offset to the input signal (s(t)), thereby providing a positive signal swing to the output signal (r(t)). The level shifter (15) includes an amplifier (17) having a first input (11), a second input (12) and an output (13). The first capacitor (C1), the second capacitor (C2), the reference voltage source (16) and the transistor (14; 74) acting as a switch form a network in which the first capacitor (C1) is arranged at the signal input (1 ) and the first input terminal (11), the second capacitor (C2) is set in the feedback loop (18) between the output terminal (13) and the first input terminal (11), the reference voltage source (16) Connect to the second input (12). The transistor (14) is arranged in a branch (19) bridging the second capacitor (C2), so that a control signal (CNTRL) can be applied to the gate (14.1) of the transistor (14) so that the level shifter (15) RESET.

Description

Prevent the input stage of negative voltage swings

The present invention relates to have the input stage of the negative voltage swings of preventing protection.Especially, the present invention relates to CMOS input stage and their protection.

Present CMOS IC (complementary mos integrated circuit) manufacturing technology reduces aspect critical geometry, and swing of the maximum permissible voltage at each transistor two ends and the corresponding maximum supply voltage that allows are also in quick reduction.On the other hand, the swinging of signal at the input port place of cmos device may surpass these voltage limits.Even more debatable be to occur having the input signal of negative voltage swings in some applications.

Typical C MOS device comprises certain level shifter 5, as shown in Figure 1, so that will import variation on the pad 1 to the V of the core 6 of cmos device _DDVoltage domain than low level.Yet such level shifter 5 is not suitable for handling the input signal with negative voltage swings.

Must protect to prevent Electrostatic Discharge COMS IC, this is not damaged by voltage peak in order to ensure circuit.Usually, at input pad 1, the voltage source terminal V of circuit _DDAnd ESD (ESD) protection component is set between the earth terminal GND, such as diode 2 and 3, describe as Fig. 1.Use esd protection destroyed when being discharged incident to prevent highstrung level shifter 5.This situation may occur in for example when someone induces voltage peak by the pin of contact chip in circuit.This esd protection scheme is also inoperative when negative voltage is applied to input pad 1, and this is because diode 3 will enter conducting state, and this will cause the slicing of input signal.

Handle the esd protection of input signal and the more details of level deviation propose about cmos device in the common pending application application of " INPUT STAGE RESISTANT AGAINST HIGH VOLTAGESWINGS (preventing the input stage of high voltage swing) " by name with positive voltage swing; this application was submitted on February 6th, 2002, and the application number of this common pending application is EP02002681.1.

An object of the present invention is to provide the input stage that to handle negative voltage swings, and provide based on above equipment.

Another object of the present invention provides the input stage that can handle negative voltage swings and can stand esd event, and provides based on above equipment.

These and other objects are finished by the circuitry according to claim 1.Other favourable implementation is stated in claim 2-9.

The invention enables the manufacturing technology cost with reduction and the circuit of more uncomplicated system design to be achieved.

For to the present invention and further purpose and advantage be described in more detail, carry out following description in conjunction with the accompanying drawings, wherein:

Fig. 1 is the representative schematic diagram with conventional cmos device of esd protection and level shifter;

Fig. 2 is the representative schematic diagram of the first embodiment of the present invention;

Fig. 3 is the chart that illustrates according to the unlike signal in the equipment of the present invention;

Fig. 4 is the representative schematic diagram of the second embodiment of the present invention;

Fig. 5 is the representative schematic diagram of the third embodiment of the present invention;

Fig. 6 is a chart of representing unlike signal in the device in accordance with the invention;

Fig. 7 is the representative schematic diagram of the fourth embodiment of the present invention;

Fig. 8 is the representative schematic diagram of the fifth embodiment of the present invention;

Fig. 9 is the representative schematic diagram according to esd protection scheme of the present invention.

The first embodiment of the present invention as shown in Figure 2.In this figure, show according to the input utmost point 10 of the present invention.It comprises the level shifter 15 that is connected with signal input part 1.The input utmost point 10 receives the input signal with negative signal swing.Owing to can not handle negative signal fully at this subsequent conditioning circuit that is called " core ", for the output signal that provides only to have the positive signal swing, level shifter 15 provides the DC skew to described input signal.As shown in Figure 2, level shifter 15 comprises an amplifier 17 with first input end 11, second input 12 and output 13.Amplifier 17 is parts of a network, and this network comprises the first capacitor C1, the second capacitor C2 and as the transistor 14 of switch.Transistor 14 is the n channel MOS transistor preferably.The first capacitor C1 is set between signal input part 1 and the amplifier first input end 11.The second capacitor C2 is set on the feedback loop 18 between output 13 and the first input end 11.A reference voltage source 16 is arranged, and it is with reference voltage V _RefBe applied on second input 12 of amplifier.

Transistor 14 is set in the branch road 19 of the bridge joint second capacitor C2.When applying high-level control signal CNTRL to the grid 14.1 of transistor 14, level shifter 15 is initialised or is reset.Generally speaking, execution resets at every turn before input signal s (t) being applied to input 1.

When switch 14.1 cut out, amplifier 17 all served as the unit gain voltage follower of reference voltage 16, so output 13 and input 11 are set near V _RefTherefore capacitor C1 is charged to V _Ref-s (t), and realization is to the DC level deviation of input.In case switch 14.1 is opened, amplifier 17 just has the inverting amplifier of gain-C1/C2 with C1 and C2 conduct.

For example can be set to height and, promptly apply input signal s (t) before just by control signal CNTRL in moment t0 release.After t0, output signal r (t) is provided by following formula:

$r\left(t\right)=-\frac{C1}{C2}\·(s\left(t\right)-s\left(t\right){|}_{t=t0})+V_{\mathrm{ref}}---\left(1\right)$

The DC skew that equation (1) expression is provided by input stage 10 can be by reference voltage V _RefDetermine with the ratio of C1 and C2.This has provided any freedom that adapts to any input voltage swing.Control signal CNTRL is activated often or is activated when needs, with the potential discharge of compensation condenser C1.Discharge is owing to inevitable leakage current takes place.

For the device that uses deep submicron process to make, the importantly transistor of neither one device wrecking property voltage between its terminal.According to the present invention, high voltage only is applied on the capacitor C1, and it should be built into outside the available layers, and such as metal interconnected sandwich structure or edge capacitance device, it can bear high voltage.

Fig. 3 shows has constant reference voltage V _Ref=1V and have 0V and-example of the sinusoidal wave s (t) at input 1 place of swing between the 4V.Amplifier 17 has 0.5 gain.At moment t=t0, release control signal CNTRL.Before input 1, discharge this signal soon applying signal s (t).Sinusoidal wave s (t) beginning 0V and-vibrate between the 4V.According to the present invention, output signal r (t) is offset by DC.In this example, output signal r (t) is vibration around+1V, and has the amplitude of 1V.Output signal r (t) does not enter negative voltage range.

According to current needs, can come device 10 is made amendment by adding building-out condenser and switch, to allow to regulate the DC skew.To be described in more detail in conjunction with another embodiment.

Fig. 4 shows according to another embodiment of the present invention.Fig. 4 shows equipment 20, and it comprises a level shifter 10 (or according to other level shifter of the present invention) and bias current sources 21.Current source 21 comprises a network with a plurality of PMOS transistor P1, P2, P3, resistor R 1 and R2 and reference current source 22.Current source 21 is by a current mirror configuration that comprises the transistor P1 that is connected to supply voltage node 23 and P2.Supply voltage Vsupply is applied to this node 23.As mentioned above, in deep submicron fabrication process, the voltage between each transistorized terminal must can not surpass maximum prescribed voltage Vmax, and it is usually near Vsupply.This will mean that the biasing of transistor P2 will be above the working range that allows when the source electrode of transistor P2 is directly connected to input node IN.For preventing that transistor P2 from damaging, add a special cobasis-grounded-emitter transistor P3, if the input signal s (t) at node IN place is lower than 0V, then this transistor P3 just absorbs the voltage of any Vsupply of exceeding.Two resistor R 1 and R2 serve as resitstance voltage divider, and it is controlled the canopy utmost point of cobasis-grounded-emitter transistor P3 according to input voltage s (t).If necessary, additional cobasis-grounded-emitter transistor and cobasis-grounded-emitter transistor P3 can be connected in series, to allow higher protection range.Like this, the voltage between node 23 and the node 24 just is held and is lower than Vsupply.

Current source 21 is designed such that itself is protected, thereby does not suffer negative input voltage.

If Vtp is that threshold voltage and the s (INmin) of transistor P3 is the minimum voltage at input node IN place, then the specification of described resitstance voltage divider is:

$-s\left(\mathrm{IN}\min \right)=\frac{R1+R2}{R2}\·\mathrm{Vtp}---\left(2\right)$

Many application need bias current sources, it preferably is arranged on the chip.Typical example is the transducer that is used to measure the power that the RF of similar antenna connects.Respective embodiments is shown in Figure 5.Equipment 30 has been shown in this accompanying drawing.It comprises the bias current sources 21 shown in a level shifter 10 or 15 (perhaps according to other level shifter of the present invention) and similar Fig. 4.Equipment 30 serves as the peak detector of radiofrequency signal RF.At input side, there is a network that comprises two capacitor C3 and C4, resistor R and diode D.A RF signal is applied to RF node 31.Current source 21 is designed such that diode D is suitably setovered.

Fig. 6 show constant reference voltage and have 2V at input 31 places and-example of the RF voltage of swing between the 2V.At moment t=t0, release control signal CNTRL.Before being applied to input 31, the RF signal discharges this control signal CNTRL soon.The RF signal begin 2V and-vibrate between the 2V.Fig. 6 shows the biasing of the diode D when about t=t0, and negative voltage s (t) is to the conversion of positive voltage r (t).The voltage x (t) of node 24 (between transistor P2 and the P3) has been shown among Fig. 6.Voltage s (t) become be lower than 0V in, the voltage x (t) at node 24 places maintains in the safe range.That is to say that transistor P3 is activated, and is as desired.

According to the present invention, output signal r (t) is offset by DC.In this example, output signal r (t) does not enter negative voltage range.

Fig. 7 shows according to another embodiment of the present invention.Figure 7 illustrates equipment 70, wherein can change reference voltage V _RefWith ratio C1/C2.An input stage has been shown in this accompanying drawing.It comprises a level shifter 75 that can be connected to signal input part 71.This input stage receives the input signal s (t) with negative signal swing.Because late-class circuit (not shown among Fig. 7) can not handled negative signal, provide DC skew so level shifter 75 just is described input signal s (t), thereby provide the output signal r (t) that only has the positive signal swing at output 73 places.As shown in Figure 7, level shifter 75 comprises the amplifier 77 with first input end 61, second input 62 and output 73.Amplifier 77 is parts of a network, array and a transistor 74 that serves as switch (nsw) that this network comprises the first capacitor C1, is made of to C2n n the second capacitor C2A, C2B.Preferably, transistor 74 is n channel MOS transistors.The first capacitor C1 is set between the first input end 61 of signal input part 71 and amplifier.During the second capacitor C2A, C2B are set at feedback loop between output 73 and the first input end 61 to C2n.Reference voltage V _RefProvide by controller 78 and number-Mo (DAC) transducer 79 that is connected to second input 62 of amplifier.The output voltage r (t) at output 73 places is measured by analog-digital converter (ADC) 80, and is fed to controller 78 as numerical data (Adata).Controller 78 is digitial controllers, and it is provided with the reference voltage V at input 62 places by number-Mo (DAC) transducer 79 _RefIn addition, controller 78 is by switching the capacitor C2B in parallel with capacitor C2A comes tuned amplifier 77 to C2n gain.For example, if apply switching signal sb, then second capacitor C 2 is just decided by parallel C2A and the C2B that is provided with.That is to say C2=C2A+C2B.In this case, output signal r (t) is provided by following equation (3):

$r\left(t\right)=-\frac{C1}{C2A+C2B}\·(s\left(t\right)-s\left(t\right){|}_{t=t0})+V_{\mathrm{ref}}---\left(3\right)$

Gain is depended on:

$\mathrm{gain}=\frac{C1}{C2A+\underset{i=B}{\overset{n}{\mathrm{\Σ}}}(C2i\·\mathrm{ai})}---\left(4\right)$

Ai=1 when switch s is closed, and when switch s opens ai=0.With the equipment class of describing before seemingly because capacitor C1 and C2A discharge because of leakage current to C2n, so need reset often.

Also can adopt the programmable array of capacitor to substitute the single first capacitor C1.

Fig. 8 has provided the block diagram with similar equipment 90 shown in Figure 7.Equipment 90 comprises an input pad 91 that is used for applying the signal s (t) with negative signal swing.Provide esd protection 92 for making core avoid all possible ESD overstress situation.One and similar bias current sources 93 shown in Figure 4 are provided.Level shifter 95 provides the DC skew to signal s (t) at its input 91 places.In order to make circuit reset often, timing circuit 94 provides control signal CNTRL.Provide reference voltage V by reference voltage source 97 _RefWith shown in Figure 7 similar, can be by the Amplifier Gain and the reference voltage V of controller 96 controls and adjusting level shifter 95 inside _Ref Output 91 is connected to circuit core, and this core is not shown in Fig. 8.

Schematically shown general esd protection scheme of the present invention among Fig. 9.Two diode DP1 and DP2 that are used to protect level shifter and core 103 are arranged.Diode DP2 is between input node 91 and power supply node 101, and diode DP1 is between power supply node 101 and substrate 102.Clamping diode DCL1 is between power supply node 101 and substrate 102.Used diode must be enough to bear required ESD level.Preferably, diode DP1 comprises a Nwell (N trap) who is arranged on P epitaxial loayer or P trap layer inside.For example, Nwell preferably is higher than 20V to the puncture voltage of substrate 102.Diode DP2 comprises a p+ active region in Nwell inside, and it also constitutes diode DP1.The puncture voltage of diode DP2 preferably is higher than 12V.Voltage on the power protection clamping diode DCL1 restriction power supply node 101.For example, this limit can be set to 11V.Therefore, the voltage range of resulting input node 91 is that 12V is to V _Supply+ Vf (diode drop), restrictive condition is V _Supply＜V _Br(puncture voltage of diode DCL1).Preferably, protective resistor Rp is positioned at the input end of level shifter and core 103, as shown in Figure 9.

For multiple-power-domain, each territory must have P type diode D1 and the such combination of power clamping diode DCL1.

Except that protection scheme shown in Figure 9, advantageously adopt so-called secondary protection scheme, so that the element of protection level shifter and core.Processing to two kinds of different situations is as follows:

1., then must protect this drain electrode to prevent electrical overstress if core is the drain electrode of PMOS.This can realize by protective resistor.Resistor is calculated, cause any damage in the PMOS of core drain electrode place to prevent maximum current.

2. if core is a grid, then recommending will be by protective resistor Rp with towards V _SupplyThe RC low pass filter that constitutes of diode p as protection.Because gate breakdown voltage is very low in present semiconductor technology, so this is necessary.For example, the time constant of this RC low pass filter should be about 50ps.As a rule, protective resistor should be big as far as possible, and restrictive condition is by the switching frequency and the decision of input driving force of the circuit that input signal s (t) is provided to equipment according to the present invention.

Because strict voltage limit, so recommend to make as far as possible the VDD protection near power supply node.Otherwise interconnection line can cause the voltage drop that adds, thereby causes junction breakdown or gate oxide breakdown in the core.

For example, this programme can be used for protecting CMOS (complementary metal oxide semiconductors (CMOS)) and BiCMOS circuit (with the bipolar device of CMOS electronic circuit combination on the single chip).

The present invention can be used for mobile phone and wherein measures other device of the RF power of antenna often.The present invention also can be used for electric timer, interface circuit (such as RS232) or the like.

Set forth the preferred embodiments of the present invention in drawing and description, though adopted specific term, the explanation that provides is so just used term on general meaning and describing significance, but not for determinate purpose.

Claims (9)

1, comprises that can be connected to a signal input part (1; 31; 71; 91) level shifter (15; 75; 95; 103) equipment (10; 20; 70; 90; 100), be used to receive input signal (s (t)), described level shifter (15 with negative signal swing; 75; 95; 103) provide DC skew to have the output signal (r (t)) that positive signal is swung, described level shifter (15 so that provide to described input signal (s (t)); 75; 95; 103) comprising: one has first input end (11; 61), second input (12; 62) and output (13; 73) amplifier (17; 77), first capacitor (C1), the second capacitor (C2; C2A, C2B is to C2n), reference voltage source (16; 79) and serve as the transistor (14 of switch; 74), wherein said first capacitor (C1) is set at described signal input part (1; 71; 91) and described first input end (11; 61) between, the described second capacitor (C2; C2A, C2B is to C2n) be set at output (13; 73) and described first input end (11; 61) in the feedback loop between (18), described reference voltage source (16; 79) can be connected to described second input (12; 62), and wherein said transistor (14; 74) be set at a bridge joint second capacitor (C2; C2A, C2B is to C2n) branch road (19; 69) in, like this, control signal (CNTRL) can be applied to described transistor (14; 74) grid (14.1; 74.1) so that allow to reset often this level shifter (15; 75; 95; 103).

2, the equipment of claim 1 is wherein by changing described capacitor (C2; C2A, C2B is to C2n) effective capacitance can regulate described amplifier (17; 77) gain.

3, the equipment of claim 2, wherein provide the branch road of bridge joint second capacitor, described branch road comprise one with switch (sb, sn) capacitor connected in series (C2B, C2n), thereby by open or closed this switch (sb sn) can change effective capacitance.

4, claim 2 or 3 equipment, comprise one can be connected to output (73) with the analog-digital converter (80) of the voltage level that is used for determining that output (73) is located and one be used for receiving from or go to the controller (78 of the digital information of this mould one number converter (80); 96), described digital information is represented described voltage level, described controller (78; 96) provide a signal to regulate described effective capacitance.

5, claim 1,2 or 3 equipment comprise a digital-analog converter (79) that serves as reference voltage source, and described digital-analog converter (79) preferably receives and comes self-controller (78; 96) digital signal.

6, claim 1,2 or 3 equipment comprise a bias current sources (21; 93) and a network, this network have a plurality of transistors (P1, P2, P3), resistor (R1, R2) and a reference current source (22).

7, the equipment of claim 6, one of them transistor is the cobasis-grounded-emitter transistor (P3) that is provided with respect to one of them other transistor (P2), if thereby input signal s (t) drops to below the 0V, then this transistor absorbs any voltage that exceeds supply voltage (Vsupply).

8,, also comprise the esd protection device (92) that is suitable for the negative voltage swings that processing signals input (91) locates according to the equipment of aforementioned arbitrary claim.

9, the equipment of claim 8; wherein said esd protection device (92) comprises first diode (DP2), second diode (DP1) and the 3rd diode (DCL1); described first diode (DP2) is positioned between signal input part (91) and the power supply node (101); described second diode (DP1) is positioned between power supply node (101) and the substrate (102), and described the 3rd diode (DCL1) is positioned between power supply node (101) and the substrate (102).

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