CN101090075B - Method for manufacturing vertical embedded capacitor substrate and structure thereof - Google Patents

Abstract

A vertical embedded capacitor substrate manufacturing method and structure, mainly include providing several conducting layers, these conducting layers are made up of a wire layer and a first dielectric layer, the wire layer is formed on the first dielectric layer; providing a plurality of composite layers, wherein the composite layers are composed of a patterned electrode layer and a second dielectric layer, and the patterned electrode layer is formed on the second dielectric layer; pressing the conducting layers and the composite layers to form a block body, wherein the patterned electrode layer is contacted with the first dielectric layer, and the block body is defined with a plurality of vertical embedded capacitor substrates and a plurality of cutting channels among the vertical embedded capacitor substrates; and cutting the block along the cutting lines to separate the vertical embedded capacitor substrates in a single body.

Description

Fabrication method and structure of vertical embedded capacitor substrate

technical field

The present invention relates to an embedded capacitor substrate, in particular to a method for manufacturing a vertical embedded capacitor substrate and its structure.

Background technique

As shown in FIG. 1, the existing embedded capacitor substrate 10 includes an upper surface 11, a lower surface 12, several embedded capacitors 13 and several wires 14, and these embedded capacitors 13 are electrically connected to these wires. 14. The embedded capacitors 13 have a first electrode 131, a dielectric layer 132 and a second electrode 133, and the first electrodes 131 and the second electrodes 133 are respectively arranged on the upper surface 11 in parallel With the lower surface 12, a chip 50 can be electrically connected to the embedded capacitors 11 through the wires 14, but the layout of the first electrodes 131 and the second electrodes 133 of the embedded capacitors 11 It is a horizontal type, that is, parallel to the upper surface 11 and the lower surface 12 respectively, which will take up a considerable amount of layout space on the substrate, so that the number of layouts of these embedded capacitors 11 will be limited by the size of the substrate, and cannot be used in large quantities. application, and when the number of capacitors is insufficient, it is still necessary to rely on an external capacitor c to compensate, which will not only increase the additional SMT process, but also increase the volume of the package and the production cost.

Contents of the invention

The main purpose of the present invention is to provide a manufacturing method and structure of a vertical embedded capacitor substrate, which mainly uses a vertical embedded capacitor composed of several patterned electrode layers and several dielectric layers to increase the number of substrates. The circuit layout space and design flexibility, in addition to not needing to use additional SMT process to increase the external capacitor, but also can reduce the size of the package using the vertical embedded capacitor substrate and reduce the production cost.

A method for manufacturing a vertical embedded capacitor substrate according to the present invention includes providing several conduction layers, the conduction layers are composed of a wire layer and a first dielectric layer, and the wire layer is formed On the first dielectric layer; providing a plurality of composite layers, the composite layers are composed of a patterned electrode layer and two dielectric layers, the patterned electrode layer is formed on the second dielectric layer; Pressing the conduction layers and the composite layers to form a body, the patterned electrode layer is in contact with the first dielectric layer, the body is defined with several vertical embedded capacitance substrates and the vertical a plurality of cutting lines between the embedded capacitor substrates; and cutting the block along the cutting lines to singulate and separate the vertical embedded capacitor substrates.

Another method for manufacturing a vertical embedded capacitor substrate according to the present invention includes providing several conduction layers, the conduction layers are composed of a wire layer and a first dielectric layer, and the wire layer is Formed on the first dielectric layer; providing a plurality of first composite layers, the first composite layers are composed of a patterned electrode layer and a second dielectric layer, the patterned electrode layer is formed on the On the second dielectric layer; several second composite layers are provided, the second composite layers are composed of a flat electrode layer and a third dielectric layer, the flat electrode layer is formed on the third dielectric layer on; press the conductive layers, the first composite layers and the second composite layers to form a body, the patterned electrode layer is in contact with the first dielectric layer, and the flat electrode layer is in contact with the first dielectric layer Layer contact, the block is defined with a number of vertical embedded capacitor substrates and a number of dicing lines between the vertical embedded capacitor substrates; and cutting the block along the dicing lines to singulate The vertical embedded capacitor substrates are separated.

According to a vertical embedded capacitor substrate of the present invention, it comprises several conductive layers and several first composite layers, and these conductive layers have a wire layer and a first dielectric layer, and the wire layer is Formed on the first dielectric layer, the first composite layers are formed between the conducting layers, and have a patterned electrode layer and a second dielectric layer, and the patterned electrode layers have Several electrodes, the patterned electrode layer is in contact with the first dielectric layer.

Compared with the prior art, the present invention mainly utilizes the vertical embedded capacitance formed by several patterned electrode layers and several dielectric layers to increase the circuit layout space and design flexibility of the substrate, except that no additional SMT In addition to increasing the external capacitance through the manufacturing process, the volume of the package using the vertical embedded capacitance substrate can be reduced and the production cost can be reduced.

Description of drawings

FIG. 1 is a schematic perspective view of a conventional embedded capacitor substrate.

2A to 2D are flowcharts of a method for manufacturing a vertical embedded capacitor substrate according to a first preferred embodiment of the present invention.

3 is a schematic cross-sectional view of the process of forming at least one circuit layer on the vertical embedded capacitor substrate according to the first preferred embodiment of the present invention.

FIG. 4 is a schematic cross-sectional view of the process of forming several bumps on the circuit layer according to the first preferred embodiment of the present invention.

5A to 5E are flowcharts of a method for manufacturing a vertical embedded capacitor substrate according to a second preferred embodiment of the present invention.

6 is a schematic cross-sectional view of the process of forming at least one circuit layer on the vertical embedded capacitor substrate according to the second preferred embodiment of the present invention.

FIG. 7 is a schematic cross-sectional view of the process of forming several bumps on the circuit layer according to the second preferred embodiment of the present invention.

Detailed ways

Please refer to FIG. 2A to FIG. 2C , which are the first preferred embodiment of the present invention, a method for manufacturing a vertical embedded capacitor substrate 20 . First, referring to FIG. 2A, several conducting layers 21 are provided. These conducting layers 21 are composed of a wiring layer 211 and a first dielectric layer 212. The wiring layer 211 is formed on the first dielectric layer. On the layer 212, in this embodiment, the wiring layers 211 are made by a flat metal layer with a lithographic etching process (not shown in the figure), and the wiring layers 211 have several wirings 211a. 211a is used to replace the via holes of the existing substrate; then, please refer to FIG. 2B , providing several composite layers 22, which are composed of a patterned electrode layer 221 and a second dielectric layer 222 , wherein the patterned electrode layer 221 is formed on the second dielectric layer 222. In this embodiment, the patterned electrode layers 221 are made of a flat metal layer by a lithographic etching process (not shown in the figure) 2), these patterned electrode layers 221 have several electrodes 221a to form several capacitive structures C (as shown in FIG. 2C ), and these capacitive structures C can be connected in series according to different electrical requirements in applications. Parallel design, preferably, the electrodes 221a are distributed in an array, and the second dielectric layers 222 and the first dielectric layers 212 can be epoxy resin (epoxyresin), FR4, BT resin, Polymer material or ceramic material; Next, referring to FIG. 2C, the conductive layers 21 and the composite layers 22 are laminated to form a body B, the patterned electrode layer 221 is in contact with the first dielectric layer 212, and the The block B is defined with a number of vertical embedded capacitor substrates 20 and a number of cutting lines B1 between these vertical embedded capacitor substrates 20. In this embodiment, the vertical embedded capacitor substrates 20 The size can be determined according to the application requirements; finally, referring to FIG. 2D , the block B is cut along the cutting lines B1 to singulate and separate the vertical embedded capacitor substrates 20 . The vertical embedded capacitor substrates 20 have a first surface 201 and a second surface 202, the first surfaces 201 and the second surfaces 202 expose the wires 211a and the electrodes 221a, the The wire 211a and the electrodes 221a can be used to electrically connect at least one chip or at least one circuit component (not shown).

Please refer to FIG. 3 , in this embodiment, at least one circuit layer 23 may be formed on the first surfaces 201 and the second surfaces 202 of the vertical embedded capacitor substrates 20, the circuit layer 23 It is to electrically connect the wires 211a of the wire layers 211 and the electrodes 221a of the patterned electrode layers 221, so that the chip or the circuit component can pass through the wire layer 23 and the vertical embedded capacitor substrate 20 electrical connection. Or, please refer to FIG. 4 , further comprising forming a plurality of bumps 24 on the circuit layer 23 so that the chip can be electrically connected to the vertical embedded capacitor substrate 20 through the bumps 24 .

Please refer to FIG. 5A and FIG. 5E , which are the second preferred embodiment of the present invention, a method for manufacturing a vertical embedded capacitor substrate 30 . First, referring to FIG. 5A, several conducting layers 31 are provided. These conducting layers 31 are composed of a wiring layer 311 and a first dielectric layer 312. The wiring layer 311 is formed on the first dielectric layer. On the layer 312, in this embodiment, the wire layers 311 have several wires 311a; then, referring to FIG. 5B, several first composite layers 32 are provided, and these first composite layers 32 are formed by a The electrode layer 321 and a second dielectric layer 322 are formed. The patterned electrode layer 321 is formed on the second dielectric layer 322. In this embodiment, the patterned electrode layers 321 have several electrodes. 321a, these electrodes 321a are distributed in an array; then, referring to FIG. 5C, several second composite layers 33 are provided. Composed, the plate electrode layer 331 is formed on the third dielectric layer 332, in this embodiment, the third dielectric layers 332, the second dielectric layers 322 and the first dielectric layers The layer 312 can be the same material or different materials; then, please refer to FIG. 5D, press the conductive layers 31, the first composite layers 32 and the second composite layers 33 to form a body B, the pattern The electrode layer 321 is in contact with the first dielectric layer 312, and the flat electrode layer 331 is in contact with the first dielectric layer 312. The block B is defined with a number of vertical embedded capacitor substrates 30 and in these vertical Several cutting lines B1 between the embedded capacitor substrates 30; finally, please refer to FIG. The vertical embedded capacitor substrates 30 separated by bulking have a first surface 301 and a second surface 302, the first surfaces 301 and the second surfaces 302 expose the wires 311a, the electrodes 321a and the flat electrode layers 331, the wires 311a, the electrodes 321a and the flat electrode layers 331 can be used to electrically connect at least one chip or at least one circuit component (not shown).

Please refer to FIG. 6 , in this embodiment, at least one circuit layer 34 may be formed on the first surfaces 301 and the second surfaces 302 of the vertical embedded capacitor substrates 30 , the circuit layer 34 It is to electrically connect the wires 311a of the wire layers 311, the electrodes 321a of the patterned electrode layers 321 and the flat electrode layers 331, so that the chip or the circuit component can pass through the wire layer 34 and the The vertical embedded capacitor substrate 30 is electrically connected. Or, referring to FIG. 7 , it further includes forming a plurality of bumps 35 on the circuit layer 34 so that the chip or the circuit component can be electrically connected to the vertical embedded capacitor substrate 30 through the bumps 35 .

Please refer to FIG. 5E and FIG. 6, which are vertical embedded capacitor substrate structures according to the present invention. A vertical embedded capacitor substrate 30 includes a plurality of conducting layers 31 and a plurality of first composite layers 32. The conductive layers 31 have a wire layer 311 and a first dielectric layer 312, the wire layer 311 is formed on the first dielectric layer 312, the wire layers 311 have a plurality of wires 311a, the wire layers 311 The first composite layer 32 is formed between the conducting layers 31 and has a patterned electrode layer 321 and a second dielectric layer 322. The patterned electrode layer 321 has a plurality of electrodes 321a, patterned The electrode layer 321 is in contact with the first dielectric layer 312. Preferably, the electrodes 321a are distributed in an array. In this embodiment, the vertical embedded capacitor substrate 30 further includes a plurality of second composite layers 33, and the second composite layers 33 have a flat electrode layer 331 and a third dielectric layer 332. The second composite layers 33 are formed between the conduction layers 31, and the flat electrode layer 331 is in contact with the first dielectric layer 312, or, in another embodiment, the second composite layers 33 can be Formed between the first composite layers 32 , the flat electrode layer 331 is in contact with the second dielectric layer 322 . The present invention greatly increases the circuit of the substrate through the vertical embedded capacitance formed by the patterned electrode layers 321 and the second dielectric layers 322 or the flat electrode layers 331 and the third dielectric layers 332. The layout space and design flexibility, in addition to not needing to use additional SMT process to increase the external capacitor, can also reduce the size of the package using the vertical embedded capacitor substrate 30 and reduce the manufacturing cost.

Claims (10)

1. the manufacture method of a vertical built-in capacity substrate, it is characterized in that: it comprises:

Several conductting layers are provided, and those conductting layers are made up of a conductor layer and one first dielectric layer, and this conductor layer is to be formed on this first dielectric layer;

Several composite beds are provided, and those composite beds are made up of a patterned electrode layer and one second dielectric layer, and this patterned electrode layer is to be formed on this second dielectric layer;

Those conductting layers of pressing and those composite beds are to form a block, and the patterned electrode layer and first dielectric layer contact, and this block is that definition has several vertical built-in capacity substrates and several Cutting Roads between those vertical built-in capacity substrates; And

Cut this block along those Cutting Roads, separate those vertical built-in capacity substrates, and those vertical built-in capacity substrates are to have a first surface and a second surface with singulation.

2. the manufacture method of vertical built-in capacity substrate as claimed in claim 1, it is characterized in that: it comprises at least one line layer of formation in addition on those first surfaces and those second surfaces of those vertical built-in capacity substrates, and this line layer is to electrically connect those conductor layers and those patterned electrode layer.

3. the manufacture method of vertical built-in capacity substrate as claimed in claim 2 is characterized in that: it comprises in addition and forms several projections on this line layer.

4. the manufacture method of a vertical built-in capacity substrate, it is characterized in that: it comprises:

Several conductting layers are provided, and those conductting layers are made up of a conductor layer and one first dielectric layer, and this conductor layer is to be formed on this first dielectric layer;

Several first composite beds are provided, and those first composite beds are made up of a patterned electrode layer and one second dielectric layer, and this patterned electrode layer is to be formed on this second dielectric layer;

Several second composite beds are provided, and those second composite beds are made up of a plate electrode layer and one the 3rd dielectric layer, and this plate electrode layer is to be formed on the 3rd dielectric layer;

Those conductting layers of pressing, those first composite beds and those second composite beds are to form a block, the patterned electrode layer and first dielectric layer contact, the plate electrode layer contacts with first dielectric layer simultaneously, and this block is that definition has several vertical built-in capacity substrates and several Cutting Roads between those vertical built-in capacity substrates; And

Cut this block along those Cutting Roads, separate those vertical built-in capacity substrates, and those vertical built-in capacity substrates have a first surface and a second surface with singulation.

5. the manufacture method of vertical built-in capacity substrate as claimed in claim 4 is characterized in that: its comprise in addition form those conductor layers of at least one electric connection, patterned electrode layer and plate electrode layer line layer on those first surfaces and those second surfaces of those vertical built-in capacity substrates.

6. the manufacture method of vertical built-in capacity substrate as claimed in claim 5 is characterized in that: it comprises in addition and forms several projections on this line layer.

7. vertical built-in capacity substrate, it is characterized in that: it comprises: several conductting layers, it has a conductor layer and one first dielectric layer, and this conductor layer is to be formed on this first dielectric layer; And several first composite beds, it is formed between those conductting layers, and it has a patterned electrode layer and one second dielectric layer, and those patterned electrode layer have several electrodes, and the patterned electrode layer and first dielectric layer contact.

8. vertical built-in capacity substrate as claimed in claim 7, it is characterized in that: it includes several second composite beds in addition, those second composite beds are to be formed between those conductting layers, those second composite beds have a plate electrode layer and one the 3rd dielectric layer, and the plate electrode layer contacts with first dielectric layer.

9. vertical built-in capacity substrate as claimed in claim 7, it is characterized in that: it includes several second composite beds in addition, those second composite beds are to be formed between those first composite beds, those second composite beds have a plate electrode layer and one the 3rd dielectric layer, and the plate electrode layer contacts with second dielectric layer.

10. vertical built-in capacity substrate as claimed in claim 7 is characterized in that: those conductor layers have several leads.

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