CN101089715B - LCD panel and electronic equipment - Google Patents

Abstract

The present invention provides an electrooptical panel and electronic appliances provided with the electrooptical panel, wherein production yield and a pixel aperture ratio are not decreased even when pixels are made fine in the electrooptical panel using an active matrix addressing method by TFT addressing.The foregoing problems can be solved by putting a plurality of communication lines into electrical contact with the TFT array substrate via contact holes, wherein a plurality of pixel electrodes addressed using a TFT by the data line and scanning line are provided. A lift-up film is formed under the contact holes formed through an interlayer insulation film to put the drain region of the TFT in electrical contact with the pixel electrode.

Description

LCD panel and electronic equipment

This application is a divisional application of the parent application with application number 99102164.9 and application date of February 9, 1999.

technical field

The present invention relates to a liquid crystal panel of an active matrix driving method such as a thin film transistor (hereinafter referred to as TFT) drive, and an electronic device using the liquid crystal panel.

Background technique

Conventionally, in an active matrix drive liquid crystal panel in which a plurality of pixel electrodes arranged in a matrix are controlled by TFTs serving as switching elements, as shown in FIG. Scanning lines 3a and data lines 6a, and a plurality of TFTs 30' corresponding to their intersections, and pixel electrodes 9a electrically connected to the TFTs through contact holes 8. The structure of each TFT 30' is that the channel region 1a' of the semiconductor layer 1a is controlled by the gate electrode 3a' extending from the scanning line 3a (the portion marked with an oblique line toward the upper left in FIG. 16), and will supply an image. The signal data line 6a is electrically connected to the source region of the semiconductor layer 1a through the contact hole 5, and connects the pixel electrode 9a to the drain region of the semiconductor layer 1a. In particular, since the pixel electrode 9a is provided on various layers constituting wiring such as the TFT 30', the data line 6a, and the scanning line 3a, or on an interlayer insulating film for insulating the pixel electrode 9a from each other, , the pixel electrode 9a can be connected to the drain region of the TFT 30' through the contact hole 8 opened in the interlayer insulating film or the like.

However, in the technical field of liquid crystal panels, in order to obtain high-resolution image quality, the demand for high-definition pixels is increasing, and the progress of the miniaturization of the pixel pitch is accelerating. In this way, when the pixel pitch L is shortened and miniaturized as shown in FIG. The distance between such wirings is also bound to be narrowed. In addition, brightness, which is an important element of a liquid crystal panel, can be realized by increasing the ratio of the aperture area of pixels corresponding to the image display area, that is, the pixel aperture ratio. Wiring lines such as scanning lines or areas of TFTs serving as switching elements are non-aperture areas, so there is a certain limit in improving the pixel aperture ratio. Therefore, even if the pixel is miniaturized, the gap between the contact hole for connecting the pixel electrode and the TFT and the data line and scanning line will be narrowed by increasing the pixel aperture ratio. Therefore, there is a possibility that the pixel electrode is short-circuited with various wirings and fatal pixel defects are generated.

In addition, it is important not only to make the wiring widths such as data lines and scanning lines thinner, but also to make the TFT 30' as a switching element miniaturized, so the source region of the semiconductor layer 1a must be connected to the contact hole 5 of the data line 6a. The sizes of the contact holes 8 of the drain region and the pixel electrode 9a are miniaturized respectively. 17 shows a cross-sectional view along the line D-D' in FIG. 16, that is, a cross-sectional view of the TFT 30', indicating the process of opening the contact hole 8. As shown in FIG. In FIG. 17(a), the gate insulating film 2 and the interlayer insulating films 4 and 7 are formed on the drain region 1e, and then, as shown in FIG. In the case of a positive-type resist exposed to light at 302, the resist 302 at the irradiated portion is exposed to light, and the resist 302 is removed. However, there is a problem here with the difference in level of the steps on the interlayer insulating films 4 and 7 caused by the gate electrode 3a'. When the contact hole 8 is opened at a position close to the gate electrode 3a' in order to make the size of the TFT 30' miniaturized, irregular reflection of light will occur due to the difference in step height during the mask exposure, resulting in a resistance The abnormal situation that the etchant shrinks back in the direction of the arrow in the figure. Therefore, the diameter of the pattern from which the resist 302 is removed is larger than the portion of the photomask 303 where the light-shielding chromium film 304 is not provided, that is, the diameter of the pattern for opening a contact hole. When etching is performed, the diameter of the hole becomes larger than the diameter of the pattern for opening the contact hole formed on the photomask 303 , so there is a problem that it is difficult to miniaturize the contact hole 8 .

In addition, in the field of liquid crystal panel technology, under the requirements of high-quality display images and energy saving, it is necessary to improve the light utilization efficiency after using a macro lens. The transmission area is defined by the light-shielding film 22 formed on the counter substrate and transmits light inside the dotted line. When the light transmission area is not line-symmetric with respect to the center of the pixel aperture as in the above-mentioned conventional example, the effect of the macro lens cannot be utilized to the fullest, and thus sufficient incident light utilization efficiency cannot be obtained.

Contents of the invention

The present invention has been developed in view of the above-mentioned problems, and its object is to provide a liquid crystal panel and a liquid crystal panel equipped with such a liquid crystal panel that does not reduce the processing yield and the pixel opening ratio even if the pixels are miniaturized by adopting a relatively simple structure. board of electronic devices.

The liquid crystal panel described in item 1 is a liquid crystal panel in which liquid crystal is sealed between a pair of first and second substrates, and on the first substrate, there are a plurality of data lines and a plurality of data lines intersecting the plurality of data lines. Scanning lines, a plurality of thin film transistors arranged correspondingly to intersections of the above-mentioned data lines and the above-mentioned scanning lines, and a plurality of pixel electrodes corresponding to the plurality of thin-film transistors and arranged in a matrix, the thin-film transistors are formed on a semiconductor A gate electrode is arranged on the layer through a gate insulating film, an interlayer insulating film is arranged on the above-mentioned semiconductor layer and the above-mentioned gate electrode, and the drain region of the above-mentioned thin film transistor is electrically connected to the pixel electrode through a contact hole formed on the above-mentioned interlayer insulating film. The connection is characterized in that under the drain region of the above-mentioned semiconductor layer corresponding to the above-mentioned contact hole, an elevated film is formed by any one of polysilicon, high-melting-point metal film, and high-melting-point metal alloy.

According to the liquid crystal panel described in item 1, since the heightening film is formed under the contact hole, the step height difference between at least one of the scanning line and the data line and the contact hole can be reduced, thereby making the surface of the interlayer insulating film become flat. Therefore, it is possible to prevent the rotational displacement of the liquid crystal due to the step difference. In addition, in order to open a hole in a predetermined region of the interlayer insulating film, a resist mask is formed in a region where the interlayer insulating film is not removed. The reflection of the light can prevent the shrinkage of the resist, so the contact hole can basically be formed according to the size of the mask. Therefore, the opening size of the contact hole is not enlarged, so that the yield is not lowered due to pixel defects. In addition, since the size of the contact hole can be miniaturized, the pixel can be miniaturized, and the high-definition and miniaturization of the liquid crystal panel can be realized.

The liquid crystal panel according to item 2 is characterized in that in the liquid crystal panel described in item 1, at least one of the scanning line and the data line and the heightening film have substantially the same film thickness.

According to the liquid crystal panel described in item 2, since at least one of the scanning line and the data line has substantially the same film thickness as the raising film, the step difference can be further reduced. Therefore, it is more effective for miniaturization of contact holes and reduction of rotational displacement.

The liquid crystal panel described in item 3, liquid crystals are sealed between a pair of first and second substrates, on the above-mentioned first substrate, there are a plurality of data lines, a plurality of scanning lines crossing the plurality of data lines, and The thin film transistors connected to the data lines and the scanning lines, a plurality of pixel electrodes and storage capacitors connected to the plurality of thin film transistors and arranged in a matrix, and the gate electrodes of the thin film transistors are arranged on the semiconductor layer through a gate insulating film An interlayer insulating film is arranged on the above-mentioned semiconductor layer and the above-mentioned gate electrode, and the drain region of the above-mentioned thin film transistor is connected to the above-mentioned pixel electrode through a contact hole formed on the above-mentioned interlayer insulating layer, and is used as an electrode of the above-mentioned storage capacitor The capacitor lines are arranged approximately parallel to the scanning lines, and the liquid crystal panel is characterized in that the contact holes are arranged between the scanning lines and the capacitor lines, and a heightening film is formed under the contact holes.

According to the liquid crystal panel described in item 3, the contact hole is formed between the scanning line and the capacitor line, and the heightening film is formed under the contact hole. Therefore, the step height difference of the scanning line and the capacitance line and the contact hole can be reduced, so that the surface of the interlayer insulating film can be flattened. Since the contact hole is formed between the scanning line and the capacitance line, the contact hole can be effectively arranged by making it be located in the same area as the conventional rotational displacement caused by the lateral electric field generated between adjacent pixel electrodes. In areas that previously had to be shaded. Therefore, the rotational displacement of the liquid crystal can be prevented, and at the same time, when the resist mask is exposed to light in the photolithography process, the enlargement of the opening size of the contact hole can be suppressed.

The liquid crystal panel described in item 4 is characterized in that: in the liquid crystal panel described in item 3, the above-mentioned scanning lines and the above-mentioned capacitor lines are formed at the same time using the same material, and the above-mentioned gate insulating film and the dielectric film of the above-mentioned storage capacitor are made of the same material. materials are formed at the same time, and the same material is used to form the above-mentioned semiconductor layer and the other electrode of the above-mentioned storage capacitor at the same time.

According to the liquid crystal panel described in Item 4, the heights of the scanning lines and the capacitance lines are basically the same. Therefore, the step height difference between the scanning line and the capacitance line can be made gentle, and since the heightening film can be formed according to its height, the step height difference between the scanning line, the capacitance line and the contact hole formation area is easy to adjust, so it can be further flattened. change. Therefore, it is more effective for miniaturization of contact holes and reduction of rotational displacement.

The liquid crystal panel described in item 5 is characterized in that: in the liquid crystal panel described in item 3 or 4, at least a part of the raised film is formed around the contact hole, and at least one of the scanning line and the capacitance line is One side is concave along the above-mentioned elevated film.

According to the liquid crystal panel described in item 5, at least a part of the heightening film is formed along the formation region of the contact hole, and at least one of the scanning line and the capacitance line is recessed along the heightening film. Therefore, even if the scanning line and the capacitance line are arranged close to each other, a contact hole having a large opening area can be formed between the scanning line and the capacitance line without reducing the aperture ratio.

The liquid crystal panel described in Item 6 is characterized in that: in the liquid crystal panel described in any one of Items 3 to 5, the above-mentioned heightening film does not overlap with the above-mentioned scanning lines and the above-mentioned capacitance lines way to form.

According to the liquid crystal panel described in item 6, since the heightening film is formed so as not to overlap the above-mentioned scanning lines and the above-mentioned capacitance lines, there will be no step height difference due to overlapping of the scanning lines or capacitance lines with the heightening film, So it can become flat. Therefore, it is possible to prevent the rotational displacement of the liquid crystal and the enlargement of the opening size of the contact hole due to the level difference.

The liquid crystal panel described in Item 7 is characterized in that: in the liquid crystal panel described in any one of Items 3 to 6, the above-mentioned heightening film is formed by at least one of the above-mentioned scanning line and the above-mentioned capacitance line Almost the same film thickness configuration.

According to the liquid crystal panel described in item 7, since the heightening film is composed of substantially the same film thickness as at least one of the scanning line and the capacitance line, the thickness of the heightening film and at least one of the scanning line and the capacitance line can be further reduced. height difference between steps.

The liquid crystal panel described in item 8 is characterized in that in the liquid crystal panel described in any one of items 1 to 7, the raised film is a conductive film electrically connected to the drain region.

According to the liquid crystal panel described in item 8, the raised film is a conductive film electrically connected to the drain region. Therefore, if the raised film is formed on the drain region, the raised film can function as an etching barrier when the contact hole is opened. In addition, if the raised film is formed under the drain region, even if the drain region is penetrated when the contact hole is opened, electrical conduction with the conductive film can be maintained, so that pixel defects can be prevented.

The liquid crystal panel described in item 9 is characterized in that in the liquid crystal panel described in item 8, the raised film is a conductive film formed on the drain region at the same time as the data line using the same material.

According to the liquid crystal panel described in item 9, since the heightening film and the data lines are formed simultaneously using the same material, the heightening film can be formed without additional steps.

The liquid crystal panel described in item 10 is characterized in that in the liquid crystal panel described in item 8, the raised film is a conductive film formed under the drain region.

According to the liquid crystal panel described in item 10, even if the drain region is penetrated when the contact hole is opened, electrical continuity can be maintained, so that pixel defects can be prevented. Therefore, it is possible to reduce the thickness of the semiconductor layer constituting the source/drain and to obtain high-speed writing characteristics, so that a high-contrast liquid crystal panel can be realized.

The liquid crystal panel described in item 11, in order to solve the above-mentioned problems, is characterized in that: the liquid crystal is sealed between a pair of first and second substrates, and on the above-mentioned first substrate, a plurality of data lines and the plurality of data lines are arranged. A plurality of scanning lines intersecting each other, switching elements arranged corresponding to intersections of the above-mentioned data lines and the above-mentioned scanning lines, and a plurality of pixel electrodes connected to the plurality of switching elements and arranged in a matrix, the pixel electrodes The switching element is connected to the switching element through a contact hole opened at a substantially central position between a data line for supplying an image signal to the pixel electrode and a data line adjacent to the data line.

According to the liquid crystal panel described in item 11, by making the formation position of the contact hole for connecting the TFT as the switching element and the pixel electrode opened in the interlayer insulating film to the position for supplying the image signal to the above-mentioned The roughly central position between the data line of the pixel electrode and the scanning line adjacent to the data line can prevent the short circuit between the data line and the pixel electrode, so even if the pixel is miniaturized, it will not cause processing yield and image loss. Decrease in porosity.

The liquid crystal panel described in item 12 is characterized in that: in the liquid crystal panel described in item 11, on the first substrate, capacitance lines of predetermined storage capacitors are respectively added to the pixel electrodes, and the scanning lines are connected to each other. Arranged approximately in parallel, the above-mentioned contact holes are formed between adjacent capacitor lines and scan lines.

According to the liquid crystal panel described in item 12, the contact hole used to connect the TFT as the switching element to the pixel electrode causes the rotational displacement of the liquid crystal because of its stepped shape, but since the contact hole is arranged on the scanning line and the capacitance line Between, so it can be located in the area of rotational displacement generated by the transverse electric field between adjacent pixel electrodes. Therefore, it is possible to minimize the non-aperture region that had to be shielded from light due to the rotational displacement of the liquid crystal in the past. In addition, by disposing the capacitor line for forming the additional storage capacitor for holding the writing charge of the pixel in the region where the rotational displacement occurs, it is possible to realize a liquid crystal panel with high display quality without reducing the pixel aperture ratio. In addition, the contact hole is opened in the interval area between the adjacent capacitance line and the scanning line that does not sandwich the opening area, so the width along the direction of the data line can be enlarged in each pixel arranged in a matrix. A line-symmetric opening area defined by capacitor lines and scan lines. Therefore, compared with the conventional case where contact holes are formed at the corners of each pixel, light utilization efficiency is improved.

The liquid crystal panel according to item 13 is characterized in that in the liquid crystal panel described in item 11 or 12, a heightening film is provided at least under the switching element and directly under the contact hole.

According to the liquid crystal panel described in the thirteenth item, on the predetermined opening position of the contact hole for connecting the TFT as the switching element to the pixel electrode, since the raising film is laid under the semiconductor layer of the TFT, the etching process When the contact hole is opened in the process, even if the semiconductor layer of the TFT is penetrated, it can be protected from generating pixel defects. Therefore, the thickness of the semiconductor layer can be reduced, and high-speed writing characteristics can be obtained, so that a high-contrast liquid crystal panel can be realized.

The liquid crystal panel described in Item 14 is characterized in that: in the liquid crystal panel described in any one of Items 11 to 13, the above-mentioned switching element is composed of a thin film transistor, and the source region of the thin film transistor is connected to the data line. Electrically connected, the drain region of the thin film transistor is connected to the pixel electrode, and the raised film is electrically connected to the drain region and is a conductive film.

According to the liquid crystal panel described in item 14, the heightening film is electrically connected to the drain region of the thin film transistor as the switching element. In addition, as the material of the heightening film, a polysilicon film or a conductive film such as a high-melting point metal film such as W (tungsten), Ti (titanium), Cr (chromium), Mo (molybdenum), Ta (tantalum), or an alloy film thereof is used. Therefore, when the contact hole is opened in the etching process, even if the semiconductor layer is penetrated, the electrical connection with the conductive film can be maintained, so pixel defects will not occur.

The liquid crystal panel described in Item 15 is characterized in that: in the liquid crystal panel described in any one of Items 11 to 14, the above-mentioned heightening film is arranged so that it does not overlap with the above-mentioned scanning lines and capacitance lines. s position.

According to the liquid crystal panel described in item 15, the laying of the raising film provided under the drain region of the TFT semiconductor layer does not overlap with the scanning lines and capacitance lines provided above the semiconductor layer through the gate insulating film. This means that the surface of the interlayer insulating film above the drain region of the semiconductor layer can be substantially flattened. Therefore, in order to open a contact hole in a predetermined region of the above-mentioned interlayer insulating film, a resist mask is formed in a region where the interlayer insulating film is not removed, and when the resist mask is exposed in a photolithography process, if the interlayer The planarization of the insulating film suppresses the reflection of light on the film surface and prevents the resist from receding. Therefore, the contact hole can basically be formed in accordance with the size of the mask. Therefore, the opening size of the contact hole is not enlarged, and thus the yield is not lowered due to pixel defects. In addition, since the size of the contact hole can be miniaturized, the pixel can be miniaturized, and the high-definition and miniaturization of the liquid crystal panel can be realized.

The liquid crystal panel described in item 16 is characterized in that: in the liquid crystal panel described in any one of items 11 to 15, the film thickness of the above-mentioned raised film is different from that of the film of the above-mentioned scanning line and capacitance line. roughly the same thickness.

According to the liquid crystal panel described in item 16, the film thickness of the raised film is formed to be substantially the same as the film thickness of the scanning line and the capacitance line, so the surface of the interlayer insulating film above the drain region of the TFT can be made more compact. flat. Therefore, the shrinkage of the resist can be further prevented, and the size of the contact hole can be further miniaturized, so that the pixel can be further miniaturized, which contributes to the high-definition and miniaturization of the liquid crystal panel.

The liquid crystal panel described in Item 17 is characterized in that: in the liquid crystal panel described in any one of Items 11 to 16, the opening region has a planar shape that is line-symmetrical with respect to the upper contact hole .

According to the liquid crystal panel described in item 17, the contact hole used to connect the drain region of the TFT to the pixel electrode is opened at a line-symmetrical position with respect to the center line of the opened area, so the area located in the matrix can be enlarged. Arranged in a square shape and having a line-symmetrical hole area near the center in each pixel in a square planar shape. In addition, the step height difference of the pixel electrode around the contact hole is line-symmetric with respect to the opening area. Therefore, regardless of whether a right-handed liquid crystal or a left-handed liquid crystal is used, it is almost the same in terms of tendency to cause poor alignment of liquid crystals such as reverse tilt. That is, when liquid crystals in any of the rotation modes are used, it is possible to prevent occurrence of conspicuous misalignment, and liquid crystals in any of the rotation modes can be used in the same way, which is practically convenient. In addition, compared with the conventional example shown in FIG. 16, when a contact hole is formed at the corner of each pixel and thus a light irradiation region such as a circular shape is formed in an opening region that is not line-symmetrical, the utilization efficiency of light is improved. .

The liquid crystal panel described in item 18 is characterized in that: in the liquid crystal panel described in any one of items 11 to 17, the macro lens is arranged at a position opposite to each pixel electrode, and the The center of the lens is located at the center point of the above-mentioned opening area.

According to the liquid crystal panel described in item 18, by making the center point of the light irradiation area such as the circle formed by the macro lens coincide with the center point of the aperture area of the pixel, the ratio of the light irradiation area to the aperture area can be improved. The proportion, and can improve the light utilization efficiency. Therefore, a bright liquid crystal panel can be realized even if pixels are miniaturized.

The electronic device described in item 19 is characterized by comprising the liquid crystal panel described in any one of items 11 to 18.

According to the electronic equipment of item 19, the electronic equipment has the above-mentioned liquid crystal panel of the present invention, and can perform bright high-quality display by using a liquid crystal panel with a wide light irradiation area corresponding to the opening area and improved light utilization efficiency. .

Description of drawings:

FIG. 1 is an equivalent circuit diagram of a pixel portion constituting an image display region of a liquid crystal panel.

2 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate of the first embodiment of the liquid crystal panel of the present invention viewed from the counter substrate side.

Fig. 3 is an A-A' sectional view of Fig. 2 including the counter substrate.

Fig. 4 is a process diagram (part 1) showing the manufacturing process of the embodiment of the liquid crystal panel sequentially for the parts shown in Fig. 3 .

FIG. 5 is a process diagram (part 2 ) showing the manufacturing process of the embodiment of the liquid crystal panel sequentially for the parts shown in FIG. 3 .

Fig. 6 is a process diagram (part 3) showing the manufacturing process of the embodiment of the liquid crystal panel sequentially for the parts shown in Fig. 3 .

Fig. 7 is a process diagram showing the manufacturing process of the embodiment of the liquid crystal panel in more detail in order of the steps shown in (17) to (20) in Fig. 6 along the B-B' sectional view of Fig. 2 .

8 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate of the second embodiment of the liquid crystal panel of the present invention viewed from the counter substrate side.

Fig. 9 is a cross-sectional view taken along line C-C' of Fig. 8 including the counter substrate.

10 is a plan view of a plurality of adjacent pixel groups on the TFT array substrate of the third embodiment of the liquid crystal panel of the present invention viewed from the counter substrate side.

Fig. 11 is a graph showing the defect rate of image defect of the liquid crystal panel according to the embodiment of the liquid crystal panel of the present invention and the conventional liquid crystal panel at different pixel pitches.

Fig. 12 is a plan view showing the general structure of the liquid crystal panel of the present invention.

Fig. 13 is a sectional view taken along line H-H' of Fig. 12 .

Fig. 14 is an enlarged cross-sectional view of a counter substrate on which a pixel portion of an example of a macro lens is formed.

15 is an enlarged cross-sectional view of a counter substrate on which a pixel portion of another example of a macro lens is formed.

16 is a plan view of a plurality of adjacent pixel groups on a TFT array substrate of a conventional liquid crystal panel viewed from the counter substrate side.

FIG. 17 is a step diagram showing the steps of (17) to (20) shown in FIG. 6 in more detail along the D-D' sectional view of FIG.

Fig. 18 is a block diagram showing a schematic configuration of an embodiment of the electronic device of the present invention.

FIG. 19 is a cross-sectional view showing a liquid crystal projector as an example of electronic equipment.

Fig. 20 is a front view showing a personal computer as an example of electronic equipment.

Fig. 21 is a perspective view showing a liquid crystal device using TCP as an example of electronic equipment.

Detailed ways

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First Embodiment of Liquid Crystal Panel)

The structure of the first embodiment of the liquid crystal panel will be described with reference to FIGS. 1 to 3 . FIG. 1 is an equivalent circuit diagram showing a plurality of pixels formed in a matrix forming an image display area of a liquid crystal panel. 2 is a plan view showing a plurality of adjacent pixel groups on a TFT array substrate constituting a liquid crystal panel, and FIG. 3 is a cross-sectional view along line A-A' in FIG. 2, showing the structure of a TFT as a switching element of a pixel. In Fig. 3, in order to make the size of each layer and each component reach the degree that can be recognized on the figure, each layer and each component are represented by different reduced scales.

First, a plurality of pixels formed in a matrix form in the image display area of the liquid crystal panel of the present embodiment are formed in a matrix form a plurality of TFTs 30 for controlling the pixel electrodes 9a as shown in FIG. A data line 6a for supplying an image signal is electrically connected to the source of the TFT 30. The image signal written in the data line 6a may be sequentially supplied to each line in the order of S1, S2, ..., Sn, or may be simultaneously supplied to each group of a plurality of adjacent data lines 6a. In addition, structurally, the scanning line 3a is electrically connected to the gate of the TFT 30, and the scanning signal is sequentially applied to the scanning line 3a in the form of pulses in the order of G1, G2, ..., Gn at the specified time. . The pixel electrode 9a is electrically connected to the drain of the TFT 30, and causes the TFT 30 as a switching element to close its switch for a certain period of time, thereby writing the image signal supplied by the data line at a specified time. An image signal of a predetermined level written into the liquid crystal through the pixel electrode 9a is maintained for a certain period of time between opposing electrodes (described later) formed on an opposing substrate (described later). Liquid crystal modulates light by virtue of the orientation and sequence of its molecular clusters changing with the applied voltage level, so that it can display different gray levels. If it is a normal white mode, the incident light cannot pass through the liquid crystal part according to the applied voltage, and if it is a normal black mode, the incident light can pass through the liquid crystal part according to the applied voltage, so that it is emitted from the liquid crystal panel as a whole. The light of the contrast corresponding to the image signal. Here, in order to prevent the retained image signal from leaking, a storage capacitor 70 is added in parallel with the liquid crystal capacitor formed between the pixel electrode 9a and the opposite electrode. Therefore, a liquid crystal panel with further improved retention characteristics and high contrast can be realized. In addition, as a method of forming the storage capacitor 70, a capacitor line 3b which is a wiring for forming a capacitor may be provided, and of course, a capacitor may be formed between the previous-stage scanning line 3a.

Next, the structure of the first embodiment of the liquid crystal panel will be described.

According to the first embodiment, the planar arrangement of pixels constituting the image display area of the liquid crystal panel is as shown in FIG. 2 . That is, there are a plurality of pixel electrodes 9a arranged in matrix, a plurality of data lines 6a arranged in the X direction and extending in the Y direction, and a plurality of scanning lines 3a arranged in the Y direction and extending in the X direction. Wherein, the channel region 1a' of the semiconductor layer 1a constituting the TFT 30 is formed at the intersection of the sixth data line 6a and the scanning line 3a (the portion marked with an upward oblique line in FIG. 2 ), the TFT The source area of 30 is electrically connected through the contact hole 5 under the data line. The drain region of the semiconductor layer 1a extends to the vicinity of the adjacent SX+1th data line 6a, and forms a first storage capacitor electrode 1f for adding capacitance to the pixel. A storage capacitor is formed between the first storage capacitor electrode 1f and the capacitor line 3b using a gate insulating film as a dielectric. The capacitance line 3b extends to the outside of the image display area in the X direction along the scanning line 3a. Further, if the first storage capacitor electrode 1f is formed by extending from the drain region of the semiconductor layer 1a in the same manner under the data line 6a of the current stage, then on the non-light-transmitting region of the liquid crystal panel such as the wiring forming part, it is possible to Since the storage capacitor is effectively added, the ability to hold the charges written in the pixels can be improved, and a high-contrast liquid crystal panel can be realized. In addition, in FIG. 2, if the order of the SXth and SX+1th data lines 6a is reversed, there is no problem.

Here, a contact hole 8 for connecting the drain region of the semiconductor layer 1a to the pixel electrode 9a is provided between the wiring of the scanning line 3a and the capacitance line 3b. By making the area where the rotational displacement of the liquid crystal occurs due to the step shape of the contact hole 8 and the rotational displacement caused by the transverse electric field generated between adjacent pixel electrodes 9a be located in the same area, this will effectively dispose the contact hole 8. In areas that previously had to be shaded. In addition, directly below the contact hole 8, in the portion surrounded by a thick line in FIG. (molybdenum), Ta (tantalum) and other refractory metal films or alloy films to increase the conductivity of the film 13a. This is to prevent fatal pixel defects from being produced even if the semiconductor layer 1a is penetrated when the contact hole 8 for connecting the drain region of the semiconductor layer 1a to the pixel electrode 9a is opened in the etching process. Thinning of the semiconductor layer can be achieved, and there is an advantage of being able to form a semiconductor layer with improved transistor characteristics due to the photoelectric effect and less influence of light. In this case, at least a part of the raised film 13a is formed around the contact hole 8 so that the raised film 13a does not overlap the scanning line 3a and the capacitor line 3b. When the margin interval between the contact hole 8 and the scanning line 3a and the capacitance line 3b is very small, as shown in FIG. The (planar) form is recessed so that the scanning line 3a and the capacitance line 3b do not overlap with the elevation film 13a. In addition, by disposing the contact hole 8 at the approximate center between the adjacent SX data line 6a and the SX+1 data line 6a, even if the pixel is miniaturized, it is possible to prevent the data line 6a from contacting the pixel electrode. 9a short circuit, and can greatly reduce fatal defects such as point defects or line defects caused by defects in the TFT 30.

In addition, in the liquid crystal panel of the first embodiment, at least the channel region 1a' of the TFT 30 and the junction between the channel region 1a' and the source/drain region are formed below the data line 6a so that incident light cannot The channel region 1a' and the junction between the channel region 1a' and the source/drain regions are directly irradiated. Further, a refractory metal film such as W (tungsten), Ti (titanium), Cr (chromium), Mo (molybdenum), Ta (tantalum) or its alloy film is also provided through an interlayer insulating film under the TFT 30. The light-shielding film 11a formed by the polysilicon film (in FIG. 2, the portion marked with an oblique line facing upwards to the right), so that the incident light cannot directly irradiate at least the channel region 1a' of the TFT 30 and the channel region 1a' and the source and drain regions. of the junction. With such a structure, it is possible to prevent leakage current caused by light passing through the pixel opening being reflected by a polarizing plate or the like and then irradiating the TFT. This means that leakage current due to the photoelectric effect of semiconductors can be prevented even when strong light is injected to improve light utilization efficiency, which is particularly effective for liquid crystal panels used in projectors. In addition, in order to prevent deterioration of the transistor characteristics of the TFT 30, a fixed potential such as a ground potential may be supplied to the light shielding film 11a. At this time, if it is connected to a fixed potential line such as a power supply that supplies power to the peripheral drive circuit provided outside the image display area, dedicated external input terminals and connection wiring are not required, so the space on the TFT array substrate can be effectively used.

FIG. 3 is a cross section along line A-A' of FIG. 2, showing the three-dimensional structure of the TFT 30 and the storage capacitor 70. The TFT 30 has an LDD (Lightly Doped Drain) structure, and is equipped with a scanning line 3a (gate electrode), a channel region 1a' of the semiconductor layer 1a formed by an electric field from the scanning line 3a, and the scanning line 3a and the semiconductor layer 1a. Layer 1a insulating gate insulating film 2, low-concentration source region (source-side LDD region) 1b and low-concentration drain region (drain-side LDD region) 1c of semiconductor layer 1a, high-concentration source region 1d and high-concentration drain region of semiconductor layer 1a District 1e. The data line 6a is connected to the high-concentration source region 1d, and a corresponding one of the plurality of pixel electrodes 9a is connected to the high-concentration drain region 1e. As will be described later, the semiconductor layer 1a is doped with a dopant for n-type or p-type at a predetermined concentration depending on whether to form an n-type or p-type channel, thereby forming source regions 1b and 1d and drain regions 1c and 1e. An n-channel TFT has the advantage of fast operation, and is often used as the TFT 30 which is a switching element of a pixel. In particular, in this embodiment, the data line 6a (source electrode) is formed of a light-shielding thin film such as a metal film such as Al or an alloy film such as metal silicide. In addition, on the scanning line 3a (gate electrode), the gate insulating film 2, and the first interlayer insulating film 12, a contact hole 5 communicating with the high-concentration source region 1d and a contact hole 5 communicating with the high-concentration drain region 1e are respectively formed thereon. The second interlayer insulating film 4 communicates with the contact hole 8 . The data line 6a (source electrode) is electrically connected to the high-concentration source region 1d through the contact hole 5 communicating with the high-concentration source region 1d. Further, on the data line 6a (source electrode) and the second interlayer insulating film 4, the third interlayer insulating film 7 in which the contact hole 8 communicating with the high-concentration drain region 1e is formed is formed. The pixel electrode 9a is electrically connected to the high-concentration drain region 1e through the contact hole 8 communicating with the high-concentration drain region 1e. The above-mentioned pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 constructed as described above. Wherein, directly below the contact hole 8, the high-concentration drain region 1e of the semiconductor layer 1a and the conductivity increasing film 13a provided under the high-concentration drain region 1e are provided. Therefore, even if the high-concentration drain region 1e of the semiconductor layer 1a is penetrated during the etching process when the contact hole 8 is opened, the electrical connection can be maintained through the raised film 13a of the lower layer, thereby preventing fatal pixel defects. In addition, since the opening area of the contact hole 8 can be made as flat as possible, the film thicknesses of the scanning line 3a, the capacitance line 3b, and the raising film 13a can be made equal to each other. In addition, as shown in FIG. 2, by extending the heightening film 13a in the spaced area between the scanning line 3a and the capacitance line 3b, an area as flat as possible can be formed. If this structure is adopted, around the contact hole 8 and between the wiring of the scanning line 3a and the capacitance line 3b, since no step height difference will occur on the surface of the interlayer insulating film under the pixel electrode 9a, The occurrence area of liquid crystal rotational displacement can be minimized. Therefore, the pixel aperture ratio can be further improved. In addition, the raised film 13a may be provided not below the drain region but above the drain region to be electrically connected to the drain region. If such an elevated film is formed at the same time as the data line using the same material, the elevated film can be formed without increasing the number of steps. In addition, in this case, it is effective for further flattening if the film thicknesses of the data lines and the scanning lines or capacitance lines are made substantially the same.

The TFT 30 preferably has the LDD structure as described above, but it may also have a bias structure in which impurity ion implantation is not performed on the low-concentration source region 1b and the low-concentration drain region 1c, and the gate electrode 3a may be used as a mask at high Impurity ions are implanted at a lower concentration and a self-adjusting TFT is formed in a high-concentration source region and drain region in a self-matching manner.

In addition, in the structure shown in FIG. 3, two gate electrodes 3a, which are supplied with the same scanning signal through the gate insulating film 2, may be provided between the high-concentration source region 1d and the high-concentration drain region 1e of the TFT 30 to be used as A TFT with a double gate (double gate) structure with resistors connected in series. Thereby, the leakage current of the TFT 30 can be reduced. In addition, if the TFT of the double-gate structure has the above-mentioned LDD structure or bias structure, the leakage current of the TFT 30 can be further reduced, and a high contrast ratio can be realized. In addition, due to the double-gate structure, redundancy can be provided, so not only can pixel defects be greatly reduced, but also high-contrast image quality can be achieved due to low leakage current during high-temperature operation. Of course, there may be more than three gate electrodes 3a disposed between the high-concentration source region 1d and the high-concentration drain region 1e of the TFT 30.

Here, in general, the polysilicon layer such as the channel region 1a', the low-concentration source region 1b, and the low-concentration drain region 1c of the semiconductor layer 1a will generate current due to the photoelectric conversion effect of polysilicon when light is irradiated, and make the TFT The transistor characteristic of 30 deteriorates, but in this embodiment, since the data line 6a (source electrode) is formed with a light-shielding metal film such as A1, and makes it cover the scanning line 3a (gate electrode) from the upper side, so at least it can effectively The incident light (that is, the light from the upper side in FIG. 3 ) is prevented from irradiating the channel region 1a' and the LDD regions 1b, 1c of the semiconductor layer 1a. In addition, as mentioned above, since the light-shielding film 11a is provided on the lower side of the TFT 30, it can effectively prevent at least retroreflected light (that is, light from the lower side in FIG. 3 ) from affecting the channel region 1a' and the LDD of the semiconductor layer 1a. Incidence of areas 1b, 1c.

In addition, as shown in FIG. 1, a storage capacitor 70 is provided for each of the pixel electrodes 9a. More specifically, the storage capacitor 70 includes a first storage capacitor electrode 1f made of a polysilicon film extending from the high-concentration drain region 1e of the semiconductor layer 1a, a dielectric film formed in the same process as the gate insulating film 2, The capacitor line 3b (second storage capacitor electrode), the second and third interlayer insulating films 4 and 7, and the second and third interlayer insulating films 4 are formed in the same process as the scanning line 3a (gate electrode). and 7 a part of the pixel electrode 9a opposite to the capacitance line 3b. Since such a storage capacitor 70 is provided, high-definition display can be performed even if the duty ratio is small. The capacitor line 3b (second storage capacitor electrode) is provided on the surface of the TFT array substrate 10 substantially parallel to the scanning line 3a (gate electrode), as shown in FIG. 2 . In addition, as shown in this embodiment, the light-shielding film 11a is provided under the first storage capacitor electrode 1f through the first interlayer insulating film 12, so that the first interlayer insulating film 12 functions as a dielectric film, so that the Increased storage capacity. Therefore, a liquid crystal panel with higher image quality can be realized.

(Manufacturing process of liquid crystal panel)

Hereinafter, a manufacturing process of the liquid crystal panel having the above-mentioned structure will be described with reference to FIGS. 4 to 7 . 4 to 6 are process diagrams showing each layer on the TFT array substrate side in correspondence with the AA' cross section of FIG. 2 in each process. In addition, FIG. 7 is a process diagram showing each layer on the TFT array substrate side in correspondence with the BB' cross section in FIG. 2 , and shows a process based on (17) in FIG. 6 . In Fig. 4 to Fig. 7, in order to make the size of each layer and each component reach the degree that can be recognized on the figure, each layer and each component are represented by different reduced scales.

First, with reference to FIGS. 4 to 6, a manufacturing process of a part including the TFT 30 corresponding to the A-A' cross section of FIG. 2 will be described.

As shown in step (1) of FIG. 4 , a TFT array substrate 10 such as a quartz substrate or hard glass is prepared. Here, it is best to perform pretreatment, that is, annealing treatment in an inert gas atmosphere such as N2 (nitrogen) and a high temperature of about 900-1300° C., so as to reduce the distortion of the TFT array substrate 10 during subsequent high-temperature processing. That is, the TFT array substrate 10 is previously heat-treated at the same temperature or higher according to the temperature when the high-temperature treatment is performed at the highest temperature of the manufacturing process.

On the entire surface of the TFT array substrate 10 after the above-mentioned treatment, Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), Mo (molybdenum) and Pb (lead) are covered by sputtering. A metal alloy film such as metal or metal silicide is used to form the light-shielding film 11 with a film thickness of about 1000 to 5000 angstroms, preferably about 2000 angstroms. On the other hand, when used in an application where the amount of incident light does not reach the level where crosstalk occurs, it is not necessary to form the light shielding film 11 .

Next, as shown in step (2), on the formed light-shielding film 11, a mask corresponding to the pattern of the light-shielding film 11 is formed by photolithography, and the light-shielding film 11 is etched through the mask to form a light-shielding film. Membrane 11a. In this case, the light-shielding film 11a may be formed in an island shape, or may be formed in a stripe shape along a scanning line or a data line. In addition, if formed in a grid shape as shown in FIG. 2, the resistance of the light-shielding film 11a can be reduced.

Then, as shown in step (3), on the light-shielding film 11a, for example, by normal pressure or reduced pressure CVD method, etc., using TEOS (tetraethylorthosilicate) gas, TEB (tetraethylborate) Gas, TMOP (tetramethyloxyphosphate) gas, formed by NSG (boron and phosphorus-free silicate glass film), PSG (phosphorus-containing silicate glass film), BSG (boron-containing silicic acid Salt glass film), BPSG (phosphorous and boron containing silicate glass film) or other silicate glass film, and the first interlayer insulating film 12 composed of a silicon nitride film or a silicon oxide film. The film thickness of the first interlayer insulating film 12 is about 8000 to 15000 angstroms.

Next, as shown in step (4), the conductive film 13 is formed by reduced-pressure CVD or sputtering. The conductive film 13 is made of a polysilicon film or a refractory metal film such as W (tungsten), Ti (titanium), Cr (chromium), Mo (molybdenum), Ta (tantalum), or an alloy film thereof, and the film thickness of the conductive film 13 is , may be the same as the film thickness of the scanning lines or capacitance lines formed in a later process. This point will be described later.

Then, as shown in step (5), the island-shaped raised film 13a is left directly under the pixel electrode 9a and the drain region of the semiconductor layer 1a in the later step through photolithography and etching. The laying of the raised film 13a is to prevent defects from being generated even if the semiconductor layer is penetrated when the contact hole 8 for connecting the pixel electrode 9a to the drain region of the semiconductor layer 1a is etched. There is also no problem in laying directly under the contact hole 5 for connecting the data line 6a to the source region of the semiconductor layer.

Next, as shown in step (6), in a relatively low temperature environment of about 450-550°C, preferably about 500°C, use monosilane gas, disilane gas, etc. at a flow rate of about 400-600cc/min, An amorphous silicon film is formed on the raised film 13a by reduced-pressure CVD (for example, CVD at a pressure of about 20 to 40 Pa). Then, an annealing treatment is carried out at about 600-700° C. for about 1-10 hours, preferably 4-6 hours in a nitrogen atmosphere, so as to grow into a solid phase with a thickness of about 500-2000 angstroms, preferably about 1000 angstroms. Polysilicon film 1. At this time, if an n-channel type TFT 30 is formed, a small dose of a dopant of V-type elements such as Sb (antimony), As (arsenic), and P (phosphorus) can be doped by ion implantation or the like. If the p-channel type TFT 30 is formed, it can be doped with a small dose of dopant of type III elements such as B (boron), Ga (gallium), and In (indium) by ion implantation or the like. In addition, the polysilicon film 1 may be directly formed by a reduced-pressure CVD method or the like without going through the step of forming an amorphous silicon film. Alternatively, the polysilicon film 1 may be amorphized (amorphized) by implanting silicon ions into the polysilicon film deposited by the reduced-pressure CVD method or the like, and then the recrystallized polysilicon film 1 may be formed by annealing or the like. In addition, it is also possible to grow silicon nuclei in the solid phase by performing annealing treatment by irradiation with a laser such as an excimer laser.

Next, as shown in the step (7), the island-shaped semiconductor layer 1 a is formed in a predetermined pattern by a photolithography step, an etching step, and the like. In this case, not only a channel region and a source/drain region of a switching element but also a region serving as one electrode of a storage capacitor for adding capacitance for improving pixel retention characteristics is collectively formed.

Then, as shown in step (8), the semiconductor layer 1a is thermally oxidized at a temperature of about 900 to 1300° C., preferably at a temperature of about 1000° C., to form a relatively thin thermal oxidation layer with a thickness of about 100 to 500 angstroms. The oxide film is further formed by depositing a relatively thin high temperature silicon oxide film (HTO film) or silicon nitride film with a thickness of about 100 to 1000 angstroms by a reduced pressure CVD method to form a gate insulating film 2 having a multilayer structure. As a result, the thickness of the semiconductor layer 1a is about 200-1500 angstroms, preferably about 350-500 angstroms, and the thickness of the gate insulating film 2 is about 200-1500 angstroms, preferably about 300-1000 angstroms. In particular, by shortening the above-mentioned high-temperature thermal oxidation time, it is possible to prevent warpage due to heat when a large substrate of about 8 inches is used. However, it is also possible to form the gate insulating film 2 having a single-layer structure by thermally oxidizing only the polysilicon layer 1 . Alternatively, in order to increase the withstand voltage strength of the gate insulating film 2, a silicon nitride film may also be used. In addition, the gate insulating film 2 and the dielectric film of the storage capacitor are formed in the same process.

Next, as shown in step (9) of FIG. 5, after the polysilicon film 3 is deposited by a reduced-pressure CVD method or the like, the polysilicon film 3 is rendered conductive by thermal diffusion of phosphorus (P). Alternatively, a doped polysilicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may also be used. As shown in step (10), scanning lines 3a (gate electrodes) and capacitor lines 3b (second storage capacitor electrodes) in a predetermined pattern as shown in FIG. 8 are formed by a photolithography process using a mask, an etching process, etc. . The film thickness of the scanning line 3 a is, for example, about 1000 to 8000 angstroms. At this time, by making the film thickness substantially equal to that of the heightening film 13a, the opening shape of the contact hole can be prevented from being enlarged.

However, the scanning line 3a (gate electrode) may be formed not from a polysilicon layer but from a refractory metal film such as W or Mo or a metal silicide film, or these metal films or metal silicide films may be combined with polysilicon The films combine to form a multilayer structure. In this case, if the scanning line 3a (gate electrode) is arranged as a light-shielding film corresponding to a part or all of the area covered by the second light-shielding film 22 shown in FIG. A part or all of the second light-shielding film 22 may be omitted because of the light-shielding property it has. In particular, this case is advantageous in that it is possible to prevent a decrease in the aperture ratio of the pixel due to a deviation in adhesion between the counter substrate 20 and the TFT array substrate 10 .

Next step, as shown in the operation (11), when making the TFT 30 an n-channel type TFT with an LDD structure, at first, the scanning line 3a (gate electrode) is used as a diffusion mask, and doped with P at a low concentration. The dopant 300 of V type elements (for example, the dose of P ions is 1-3×1013/cm2), so as to form the low-concentration source region 1b and the low-concentration drain region 1c in the semiconductor layer 1a. Therefore, the semiconductor layer 1a under the scanning line 3a (gate electrode), becomes the channel region 1a'. In addition, the semiconductor layer 1a under the capacitor line 3b (second storage capacitor electrode) becomes the first storage capacitor electrode 1f of the storage capacitor 70 using the gate insulating film 2 as a dielectric. The resistance may be reduced by implanting P ions or the like in advance into the portion where the first storage capacitor electrode 1f is formed.

Next, as shown in step (12), a resist layer 302 is formed on the scanning line 3a (gate electrode) using a mask whose width is wider than that of the scanning line 3a (gate electrode), and then similarly doped at a high concentration. The dopant 301 of V-type elements such as P (for example, the dose of P ions is 1˜3×1015/cm2) is used to form the high-concentration source region 1d and the high-concentration drain region 1e. On the other hand, when making the TFT a p-channel type, the region of the n-channel type TFT 30 is covered with a resist to protect it, and steps (11) and (12) are repeated again. At this time, doping is performed with a dopant of a type III element such as B to form a low-concentration source region 1b and a low-concentration drain region 1c as well as a high-concentration source region 1d and a high-concentration drain region 1e on the semiconductor layer 1a. In the case of the above-mentioned LDD structure, there is an advantage that the short channel effect can be reduced. In addition, for example, a TFT with an offset structure can be formed without low doping, or a self-regulating TFT can be formed by ion implantation using B ions using the scanning line 3a (gate electrode) as a mask.

In the peripheral portion of the TFT array substrate 10, a peripheral driving circuit having a complementary structure composed of n-channel TFTs and p-channel TFTs can be formed in parallel with the above-mentioned steps. In this way, in this embodiment, peripheral driving circuits such as data line driving circuits and scanning line driving circuits can be formed in the same process when forming the TFT 30, so it is advantageous in terms of manufacturing.

Then, as shown in step (13), for example, a silicate glass film made of NSG, PSG, BSG, BPSG, etc., a silicon nitride film or a silicon oxide film, etc. The second interlayer insulating film 4 is formed so as to cover the scanning line 3a (gate electrode) and the capacitor line 3b (second storage capacitor electrode). The film thickness of the second interlayer insulating film 4 may be relatively thick in order not to add capacitance between wirings, and is preferably about 5000 to 15000 angstroms.

In the next step, as shown in step (14), after annealing at about 1000° C. for about 20 minutes to activate the high-concentration source region 1d and high-concentration drain region 1e , dry by reactive etching, reactive ion beam etching, etc. The contact hole 5 corresponding to the data line 6a (source electrode) is formed by etching. In this case, the method of forming the contact hole 5 by anisotropic etching such as reactive etching or reactive ion beam etching has the advantage that the shape of the opening can be substantially the same as that of the mask. However, if the combination of dry etching and wet etching is used to open holes, since the contact hole 5 can be processed into a tapered hole shape, there is an advantage that disconnection can be prevented at the time of wiring connection. In addition, a contact hole for connecting the scanning line 3a (gate electrode) to a wiring not shown in the figure is opened in the second interlayer insulating film 4 by the same process as that of the contact hole 5 .

Next, as shown in the step (15) of FIG. 6, on the second interlayer insulating film 4, a light-shielding A1 film is deposited with a thickness of about 1000 to 8000 angstroms, preferably about 3000 angstroms, by sputtering or the like. Metal-containing film 6 composed of low-resistance metal or metal silicide.

Then, as shown in step (16), data line 6a (source electrode) is formed through a photolithography step, an etching step, and the like. As the etching process, dry etching such as reactive etching and reactive ion beam etching is used, which has the advantage of preventing excessive etching and forming a wiring pattern with high precision according to the size of the mask.

In the next step, as shown in step (17), for example, use normal pressure or reduced pressure CVD and TEOC gas to form silicate glass films such as NSG, PSG, BSG, BPSG, silicon nitride films or silicon oxide films, etc. The third interlayer insulating film 7 is formed so as to cover the data 6a (source-gate electrodes). The film thickness of the third interlayer insulating film 7 may be relatively thick in order not to add capacitance between the data line 6a and the pixel electrode 9a formed in a later process, and is preferably about 5000 to 15000 angstroms. In addition, since the level difference between the wiring and the TFT 30 as a switching element may cause rotational displacement of the liquid crystal, an organic film or SOG (Spin-on-Glass) may be spin-coated, or a flat film may be formed by performing CMP treatment. , to replace or cover the silicate glass film constituting the third interlayer insulating film 7. With such a structure, the region where the rotational displacement of the liquid crystal occurs can be minimized, and a high pixel aperture ratio can be realized even if the pixel is miniaturized.

Next, as shown in step (18), contact hole 8 for electrically connecting pixel electrode 9a to high-concentration drain region 1e is formed by dry etching such as reactive etching and reactive ion beam etching. In this case, the method of forming the contact hole 8 by anisotropic etching such as reactive etching or reactive ion beam etching has the advantage that the shape of the opening can be substantially the same as that of the mask. However, if the hole is drilled in combination of dry etching and wet etching, since the contact hole 8 can be processed into a tapered hole shape, there is an advantage that disconnection can be prevented at the time of wiring connection. In addition, immediately below the opening area of the contact hole 8, not only the drain region of the semiconductor layer is laid, but also the raised film 13a as a conductive film is laid, so even if the semiconductor layer is penetrated, no leakage will occur. fatal flaw. Since the thickness of the channel region 1a' of the semiconductor layer 1a can be reduced by laying the raised film 13a, the characteristics of the device can be improved.

Then, as shown in the step (19), on the third interlayer insulating film 7, a transparent conductive thin film 9 such as an ITO film is deposited with a thickness of about 500 to 2000 angstroms by sputtering, etc., and further, as in the step (20) ), the pixel electrode 9a is formed through a photolithography process, an etching process, and the like. When the liquid crystal panel 100 is applied to a reflective liquid crystal device, the pixel electrode 9a made of an opaque material having a high reflectance such as Al may be formed. In this case, when forming the third interlayer insulating film 7, it is necessary to planarize by CMP treatment so that the pixel electrode 9a has a mirror surface.

Next, on the pixel electrode 9a, apply a polyimide series alignment film coating solution, and then perform a grinding process in a prescribed direction to have a prescribed pretilt angle, thereby forming an alignment film as shown in FIG. twenty three.

On the other hand, for the counter substrate 20 shown in FIG. 3 , first, a glass substrate or the like is prepared, and after sputtering metal chromium, for example, the second light-shielding film 22 is formed through a photolithography process and an etching process. In addition, the second light-shielding film 22 may be made of a material such as black resin in which carbon or Ti is dispersed in a photoresist, in addition to metal materials such as Cr, Ni, and Al. If a light-shielding film is formed on the TFT array substrate 10, since the opening area is defined on the TFT array substrate 10, it is not necessary to form a second light-shielding film 22 on the opposite substrate, so a liquid crystal panel with uniform transmittance can be realized. There is no need to consider the bonding accuracy of the TFT array substrate 10 and the opposite substrate 20 .

Thereafter, a transparent conductive thin film such as ITO is deposited to a thickness of about 500 to 2000 angstroms by sputtering or the like on the entire surface of the opposing substrate 20 to form the opposing electrode 21 . Further, on the counter electrode 21, apply a polyimide series alignment film coating solution, and then perform grinding treatment in a predetermined direction to make it have a predetermined pretilt angle, thereby forming the alignment film shown in FIG. twenty three.

Finally, the TFT array substrate 10 on which the above-mentioned layers have been formed is formed by using a sealing material in which a gap material composed of glass fibers or glass beads having a predetermined diameter (for example, a diameter of about 1 to 6 μm) is mixed in a predetermined amount. The alignment films 19 and 22 are bonded to the opposite substrate 20, and the liquid crystal mixed with a variety of nematic liquid crystals, for example, is attracted into the space between the two substrates by vacuum suction or the like, thereby forming The liquid crystal layer 50 has a predetermined film thickness.

Here, a manufacturing process for opening the contact hole 8 provided in the region between the scanning line 3a and the capacitance line 3b will be described. Fig. 7 is a cross-sectional view along line BB' of Fig. 2, and step (a) of Fig. 7 corresponds to step (17) of Fig. 6 described above. In addition, about the process of FIG. 7(a)-(d), it demonstrates with reference to FIG. 17(a)-(d) of a conventional example.

As shown in step (a) of FIG. 7, in the liquid crystal panel of this embodiment, the contact holes 8 are insulated between the third layers by making the thicknesses of the scanning lines 3a, the capacitance lines 3b, and the heightening films 13a substantially the same. The open area on the film 7 is in a flat state.

Next, as shown in step (b) of FIG. 7 , exposure is performed using a photomask 303 with a step exposure device or the like. When the resist 302 is a positive type resist, the portion on the photomask 303 where the light-shielding chrome film 304 is not provided (that is, the portion through which light is transmitted) is removed. The resist 302 on the 3rd interlayer insulating film 7, since the opening area of the contact hole 8 is flat, so no irregular reflection will occur during exposure, so it can be compared with that on the photomask 303. The portion of the light-shielding chromium film 304, that is, the resist 302 is removed to the same size as the pattern diameter for opening a contact hole. Therefore, since there is no retraction of the resist as shown in FIG. 17(b) of the conventional example, it is possible to open a contact hole as designed. Therefore, even if the pixel is miniaturized, the processing yield does not decrease, and thus a liquid crystal panel with a high pixel opening ratio can be realized.

Next, as shown in step (c) of FIG. 7 , the contact hole 8 is formed by anisotropic dry etching such as reactive etching and reactive ion beam etching, so that the enlargement of the opening diameter of the contact hole 8 can be prevented to the greatest extent. In addition, even if wet etching is performed to form the side wall of the contact hole 8 into a tapered shape, since the resist does not shrink back as in the past, the hole diameter does not increase, so a fine contact hole can be formed. .

Finally, as shown in step (d) of FIG. 7, after the pixel electrodes 9a are provided, the pixels in the image display area of the TFT array substrate 10 can be formed.

(The second embodiment of the liquid crystal panel)

A second embodiment of the liquid crystal panel of the present invention will be described with reference to Fig. 8 and Fig. 9 . 8 is a plan view showing a plurality of adjacent pixel groups on a TFT array substrate 10 constituting a liquid crystal panel, and FIG. 9 is a cross-sectional view taken along line C-C' in FIG. 8, showing the structure of a TFT as a switching element of a pixel. . In FIG. 9 , each layer and each component are shown on different reduced scales in order to make the size of each layer and each component reach the degree that can be recognized on the figure. In addition, in FIGS. 8 and 9 , the same components as those in FIGS. 2 to 7 are denoted by the same reference numerals, and description thereof will be omitted.

In the second embodiment, the overall structure of the liquid crystal panel is basically the same as that of the first embodiment shown in FIGS. 2 and 3, as shown in FIG. 11a'. For example, in the case of a liquid crystal panel for use in which strong light does not need to be incident, such as a direct-view type liquid crystal panel, it is not necessary to lay the light shielding film 11a'.

Therefore, as shown in FIG. 9, when the light-shielding film 11a' is not provided, the first interlayer insulating film 12 does not need to be formed when the surface of the TFT array substrate 10 has no protrusions and is sufficiently cleaned. Therefore, the step of forming the light-shielding film 11a' and the step of depositing the first interlayer insulating film 12 can be omitted. That is, the steps (1) to (3) in FIG. 4 can be deleted, so the effects in terms of manufacturing yield and cost are the same.

In addition, if the third interlayer insulating film 7 itself is formed as described in the second embodiment, or a planarized film such as an organic film is formed on the third interlayer insulating film by CMP treatment, then the contact hole is formed. In the photolithography process at 8 o'clock, irregular reflection at the time of exposure can be prevented, so a fine contact hole 8 can be realized. According to such a structure, it is not necessary to make the film thickness of the raising film 13a the same as the film thickness of the scanning line 3a and the capacitance line 3b.

(The third embodiment of the liquid crystal panel)

A third embodiment of the liquid crystal panel of the present invention will be described with reference to FIG. 10 . FIG. 10 is a plan view showing a plurality of adjacent pixel groups on a TFT array substrate 10 constituting a liquid crystal panel.

In the third embodiment, the overall structure of the liquid crystal panel is basically the same as that of the first embodiment shown in FIGS. 2 and 3, and an example is given when the pixel pitch L in the X direction is narrow. In this embodiment, the pixel pitch is one-third of the pixel pitch L shown in the first embodiment, a color filter is provided on the counter substrate, and data is formed by three pixels. It can be used as a single-panel projector or a notebook computer display using only one liquid crystal panel equipped with color filters.

Thus, if the pixel pitch L in the X direction is narrow, the distance between the data lines 6a is short, so the possibility of short-circuiting the pixel electrodes 9a through the data lines 6a and the contact holes 8 increases. The increase is particularly remarkable in the case of forming the data line 6a with an Al (aluminum) film. The reason for this is that the melting point of the Al film is low, so that the third interlayer insulating film 7 cannot be formed into a porous structure under high-temperature treatment. Therefore, the etching rate increases when the contact hole 8 is opened. In particular, when wet etching is performed to form the sidewall of the opening into a tapered shape, the opening diameter of the contact hole 8 on the third interlayer insulating film tends to increase. In addition, when the raising film 13a as an etching shielding layer is not provided as in the past, if only dry etching is performed, the selectivity ratio between the semiconductor layer 1a and the interlayer insulating film may be penetrated, so sometimes It has to be carried out simultaneously with wet etching, so it is difficult to form fine opening apertures.

FIG. 11 is a graph showing the relationship between the variation of the pixel pitch L and the defective rate when the contact hole 8 is designed as a 2 μm square and the width of the data line 6a is 5 μm. Fig. 11(a) is a liquid crystal panel manufactured according to the existing manufacturing process, and Fig. 11(b) is the result obtained on the liquid crystal panel manufactured according to the manufacturing process of this embodiment. It can be seen from the figure that in the conventional example of (a), when the pixel pitch is 20 μm or less, the defect rate caused by pixel defects increases sharply, but in this embodiment, if it is not reduced to Below 10 µm, the defective rate due to pixel defects does not increase. Therefore, if the liquid crystal panel of this embodiment is adopted, even if the pixel is further miniaturized or the aperture ratio is higher, a short circuit rarely occurs between the data line 6a and the scanning line 3a or between the capacitance line 3b and the pixel electrode 9a. Moreover, the contact hole 8 between the drain region of the semiconductor layer 1a and the pixel electrode 9a will not penetrate through, so the yield will not be reduced.

Also, when the distance between the contact hole 8 and the data line 6a is extremely close as in the third embodiment, the film thickness of the raising film 13a can be set to be substantially the same as the film thickness of the data line 6a. That is, the interlayer insulating film on the data line 6a and the opening area of the contact hole 8 can be made substantially flat. With this configuration, too, the enlargement of the opening diameter of the contact hole 8 can be suppressed, and the step difference can be made gentle, so that the rotational displacement of the liquid crystal can be reduced.

In addition, according to this embodiment, the contact hole 8 is opened at a line-symmetrical position with respect to the center line 9c (see FIGS. 2, 8, and 10) of the opening area, so that the pixel electrodes around the contact hole 8 The step height difference of 9a (refer to FIG. 3 ) is in a state of line symmetry with respect to the opening area. This is particularly effective when TN liquid crystals are used, and whether right-handed liquid crystals or left-handed liquid crystals are used for the liquid crystal layer 50, the rotational displacement of the liquid crystals such as reverse tilt is likely to occur almost the same. That is, when using any one of the liquid crystals in the rotation mode, it is possible to prevent the occurrence of significant rotational displacement before it happens. As the liquid crystal layer 50, no matter whether it is a right-handed liquid crystal or a left-handed liquid crystal, it can be used in the same way, so it is practical. convenient.

According to the present embodiment having the above-mentioned structure, compared with the case where the pixel electrode 9a is connected to the drain of the TFT through the contact hole 8 formed at the corner of each pixel as in the conventional example shown in FIG. The utilization efficiency is improved. In particular, in the case of the present embodiment, since the opening area is a rectangle approximately square, that is, has a rotationally symmetric planar shape, the ratio of the light irradiation area such as a circle to the opening area is high. , thus improving the light utilization efficiency. Of course, the opening area may also be in other rotationally symmetrical shapes such as a circle, a regular dodecagon, a regular octagon, a regular hexagon, and a square. In addition, in this embodiment, as shown in FIG. 2, FIG. 8, and FIG. 10, the width of the hole area in the X direction is defined by two adjacent data lines 6a, and the width of the hole area in the Y direction is defined by Adjacent scanning lines 3a and capacitance lines 3b sandwiching the aperture area are defined. By opening the contact hole 8 in the interval area between the adjacent scanning line 3a and the capacitance line 3b which are not sandwiched by the opening area, the two-dimensional interval area of the image display area can be effectively utilized. Therefore, the area of the hole can be effectively enlarged, so that the utilization efficiency of light can be significantly improved.

(Structure of liquid crystal panel)

Adopting the liquid crystal panel of this embodiment, the TFT30 as the switching element of the pixel is a polysilicon (p-Si) type TFT, so when forming the TFT30, it can be formed on the TFT array substrate 10 in the same process. Pixel peripheral drive circuit. The overall structure of such a liquid crystal panel 100 incorporating peripheral driving circuits will be described with reference to FIGS. 12 and 13 . 12 is a plan view of the TFT array substrate 10 together with components formed thereon viewed from the opposing substrate side, and FIG. 13 is a cross-sectional view taken along line H-H' of FIG. 12 including the opposing substrate.

In FIG. 12, on the TFT array substrate 10, a light-shielding peripheral partition frame 53 for defining an image display area is provided, and a sealing material 52 is provided in parallel on the outside thereof. In the outer region of the sealing material 52, the data line driving circuit 101 and the mounting terminal 102 are provided along one side of the TFT array substrate 10, and the scanning line driving circuit 104 is provided along two sides adjacent to the above-mentioned one side. In addition, on the other side of the TFT array substrate 10, a plurality of wirings 105 for connecting the scanning line driving circuits 104 provided on both sides of the image display area are provided. When there is no problem with the signal delay of the scanning lines, the scanning line driving circuit 104 may be formed only on one side. Of course, the data line driving circuit 101 can also be arranged on both sides of the image display area. In addition, a vertical conduction material 106 for electrically conducting between the TFT array substrate 10 and the opposing substrate 20 is provided on at least one part of the corner of the opposing substrate 20 . Furthermore, as shown in FIG. 13 , the counter substrate 20 having substantially the same profile as that of the sealing material 52 shown in FIG. 12 is bonded to the TFT array substrate 10 with the sealing material 52 .

The data line driving circuit 101 and the scanning line driving circuit 104 are electrically connected to the data line 6a (source electrode) and the scanning line 3a (gate electrode) respectively via wiring. In the data line driving circuit 101, a shift register circuit for sequentially transmitting start signals according to the clock signal is included, and the sampling circuit is controlled by the driving signal sequentially output from the data line driving circuit 101, and the display not shown in the figure is used to control the sampling circuit. The image signal converted by the information processing circuit into a form that can be displayed instantaneously is supplied to the data line 6a through the sampling circuit. In addition, in the scanning line driving circuit 104, a shift register circuit for sequentially transmitting start signals according to the clock signal is included, and the data line driving circuit 101, in synchronization with sequentially transmitting the gate voltage to the scanning lines 3a in the form of pulses, The signal voltage corresponding to the image signal is transmitted to the data line 6a. In each pixel portion corresponding to the intersection of the data line 6a and the scanning line 3a, a TFT 30 for driving liquid crystal is provided. The sampling circuit may be formed in the data line driving circuit, or may be formed in the area of the peripheral dividing frame 53 . In this way, by forming the sampling circuit in the peripheral partition frame 53 which is conventionally a non-signal area, the space can be effectively used, and the size and performance of the data line driving circuit 101 can be realized.

In FIG. 13, the liquid crystal layer 50 is composed of liquid crystal obtained by mixing one or more kinds of nematic liquid crystals, for example. The sealing material 52 is an adhesive for bonding the two substrates 10 and 20 along their peripheries, for example, made of a photocurable resin or a thermosetting resin, and is mixed therein for making the distance between the two substrates (the gap between the substrates) ) is the gap material (spacer) such as glass fiber or glass beads of the specified value. Further, on the side of the counter substrate 20 facing the liquid crystal 50, a counter electrode 21 composed of a second light-shielding film 22, an ITO film as a transparent conductive film, and the like is provided. In addition, although not shown in FIG. 13 , on the incident side of the incident light from the counter substrate 20 and the exiting side of the outgoing light from the TFT array substrate 10, according to TN (twisted nematic) mode, STN (super TN) Depending on the operation mode such as D-STN (dual-STN) mode, or normal white mode/normal black mode, polarizing film, retardation film, polarizing plate, etc. are arranged in predetermined directions.

In addition, in the liquid crystal panel 100, as an example, the liquid crystal layer 50 is composed of nematic liquid crystals, but if a polymer-dispersed liquid crystal in which liquid crystals are dispersed in polymers as fine particles is used, it is not necessary to provide the alignment film 23 and the above-mentioned Polarizing film, polarizing plate, etc., and has the advantages of improving the brightness of the liquid crystal panel and reducing power consumption due to the improvement of light utilization efficiency. In addition, this embodiment can be applied to various liquid crystal materials (liquid crystal phase states), operation modes, liquid crystal alignments, driving methods, and the like. As mentioned above, in the liquid crystal panel of this embodiment, the peripheral driving circuit for driving the image display area can be integrally formed on the TFT array substrate 10, and there is no need to attach an additional peripheral driving circuit through tape packaging or COG mounting. Therefore, A super small liquid crystal panel can be realized. In addition, ICs used to drive liquid crystal panels can be greatly reduced, so there are significant advantages in terms of cost.

(A liquid crystal panel using a macro lens)

The macro lens 200 is formed, for example, by the manufacturing method disclosed in JP-A-6-194502. FIG. 14 is an example thereof. The macro lens 200 can be formed by forming a film of a photosensitive material on the counter substrate 20, and then patterning it by photolithography so that a portion corresponding to each lens is left. Then, using the thermal deformation and surface tension of the photosensitive material, an array pattern with a smooth convex surface of each lens is formed on the opposite substrate 20, and then, the array pattern of the photosensitive material is used as a mask for dry etching Processing, engraving an array pattern of photosensitive material on the opposite substrate 20, so as to form the macro lens 200 with the smooth convex surface of each lens engraved on the surface. Alternatively, the traditional so-called "thermal deformation method" can also be used to form the macro lens 200 .

On the entire surface of the macro lens 200, a cover glass 202 is adhered with an adhesive 201, and a second light-shielding film 22, a counter electrode (common electrode) 21, and an alignment film 23 are sequentially formed thereon. In this case, the second light-shielding film 22 is provided in a matrix along the boundaries of the macro lenses 200 such that the centers of the openings coincide with the lens centers 200 a of the macro lenses 200 .

In FIG. 14 , the counter electrode 21 is formed on the entire surface of the counter substrate 20 . Such a counter electrode 21 can be formed by, for example, depositing an ITO film or the like to a thickness of about 500 to 2000 angstroms by sputtering or the like, and then performing a photolithography process, an etching process, or the like. The alignment film 23 is made of, for example, an organic thin film such as a polyimide film. Such an alignment film 23 can be formed, for example, by applying a polyimide-based coating liquid and then performing a rubbing treatment in a predetermined direction to have a predetermined pretilt angle. The second light shielding film 22 is provided in a predetermined area facing the TFT 30 . Such a second light-shielding film 22 can be formed, for example, by a sputtering process using metal materials such as Cr or Ni, a photolithography process, and an etching process, or it can be formed of a black resin in which carbon or Ti is dispersed in a photoresist. and other materials. The second light-shielding film 22 not only shields the semiconductor layer 1a of the TFT 30 from light, but also has functions of improving contrast and preventing color mixing of colorants. Alternatively, for example, as shown in FIG. 15 , a macro lens formed by pasting a transparent plate (macro lens array) with a convex surface of each lens on the surface of the opposite substrate 20 may be provided on the opposite substrate 20. 200'. In addition, such a macro lens may be attached to the surface of the counter substrate 20 opposite to the liquid crystal layer 50 .

In particular, in this embodiment, the opening area of the pixel electrode 9a shown in FIGS. Location. In addition, the contact hole 8 is opened at a line-symmetrical position with respect to the center line 9c of the opening area. Furthermore, the macro lens 200 (or 200') has a lens center point 200a (or 200a') at a position opposite to the approximate center point 9b.

According to this embodiment, when light enters from the side of the counter substrate 20, the incident light is transmitted by the macro lens having the lens center point 200a (or 200a') at a position opposite to the approximate center point 9b (center of gravity) of the opening area. 200 (or 200') converges on the pixel electrode 9a around the approximate center point 9b of the opening area. Therefore, the light condensed by the macro lens 200 (or 200') forms a circular (or approximately circular or elliptical) light irradiation area in the aperture area. Here, the contact hole 8 is opened at a line-symmetrical position with respect to the center line 9c of the opening area. Therefore, it is possible to enlarge the line-symmetric aperture area located near the center of each pixel. In addition, since the aperture area is in a line-symmetrical state with respect to the center line 9c passing through the approximate center point 9b of the aperture area, the light irradiation area such as a circle is located at a line-symmetric position within the line-symmetric aperture area. Formed (the center of a circle etc. coincides with the approximate center point 9b). Therefore, the ratio of the light irradiation area to the opening area is high, thereby improving the utilization efficiency of light. As for the light-gathering ability of the macro lens, it is sufficient to make the light-irradiated area just fit into the opening area, and it is not necessary to reduce the light-irradiated area beyond the required limit.

In addition, in the present embodiment, the pixel electrode 9a is driven by TFT in structure, but besides TFT, for example, active matrix elements such as TFD (Thin Film Diode: thin film diode) can also be used, and further, liquid crystal can also be used The panel configuration is a passive matrix type liquid crystal panel. Even in this case, as long as the macro lens is used to condense the light on the pixel electrode, the hole region described in this embodiment is line-symmetric or rotationally symmetric and the center of the lens is aligned with the hole region. The structure in which the substantially central points of the light-emitting diodes are opposite is also effective in improving the light utilization efficiency as in the case of the present embodiment.

(Electronic equipment)

Hereinafter, an embodiment of an electronic device including the liquid crystal panel of this embodiment described in detail above will be described with reference to FIGS. 18 to 21 .

First, FIG. 18 shows a schematic configuration of an electronic device including the liquid crystal panel of this embodiment.

In FIG. 18 , electronic equipment is structurally provided with a display information output source 1000 , a display information processing circuit 1002 , a drive circuit 1004 , a liquid crystal panel 100 , a clock generation circuit 1008 and a power supply circuit 1010 . The display information output source 1000 includes memory such as ROM (read only memory), RAM (random access memory), and optical disk drive, and a tuning circuit for tuning and outputting image signals. The display information such as the image signal of the format is output to the display information processing circuit 1002 . The display information processing circuit 1002 includes various well-known processing circuits such as an amplification/polarity inversion circuit, a phase expansion circuit, a rotation circuit, a gamma correction circuit, and a clamping circuit. Digital signals are sequentially generated and output to the drive circuit 1004 together with the clock signal CLK. The driving circuit 1004 is used to drive the liquid crystal panel 100 . The power supply circuit 1010 supplies predetermined power to each of the above-mentioned circuits. In addition, the drive circuit 1004 may be mounted on the TFT array substrate constituting the liquid crystal panel 100, and the display information processing circuit 1002 may also be mounted in addition.

Next, in FIGS. 19 to 21 , specific examples of electronic devices having the above configurations are shown, respectively.

In FIG. 19, a liquid crystal projector 1100 as an example of electronic equipment has three liquid crystal modules including a liquid crystal panel 100 on which the above-mentioned drive circuit 1004 is mounted on a TFT array substrate. Each module constitutes a light valve 100R for RGB, Projectors for 100G and 100B. In the liquid crystal projector 1100, when the projection light is emitted from the lamp unit 1102, which is a white light source such as a metal halide lamp, it is divided into light components R and G corresponding to the three primary colors of RGB by three reflectors 1106 and two dichroic mirrors 1108. , B, and light valves 100R, 100G, and 100B corresponding to the respective colors are respectively introduced. At this time, in order to prevent light loss due to a long optical path, the B light is introduced through a relay lens system 1121 composed of an incident lens 1122 , a relay lens 1123 and an exit lens 1124 . Then, the light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are recombined by the dichroic prism 1112 and projected on the screen 1120 as a color image through the projection lens 1114 .

In particular, in this embodiment, if the above-mentioned light-shielding film is provided on the lower side of the TFT, the reflected light and projected light generated by the projection optical system in the liquid crystal projector according to the projected light from the liquid crystal panel 100 will pass through. Even if the light reflected from the surface of the TFT array substrate, part of the projected light (part of the R light and part of the G light) passed through the dichroic prism 1112 after being emitted from other liquid crystal panels 100, etc. , It is also possible to sufficiently shield the channel region of the TFT or the like for switching the pixel electrode. Therefore, even if a prism suitable for miniaturization is used in the projection optical system, there is no need to attach an AR film for preventing retroreflected light between the TFT array substrate of each liquid crystal panel and the prism or to perform AR coating treatment on the polarizer , so it is very advantageous in making the structure small and simple.

In addition, by aligning the clear viewing directions of the liquid crystal panels constituting the three light valves 100R, 100G, and 100B, it is possible to suppress color unevenness and decrease in contrast. Therefore, when TN liquid crystals are used as liquid crystals, it is necessary to invert only the liquid crystal clear direction of the light valve 100G with respect to the image display area and the other light valves 100R and 100B. Here, if the light valve equipped with the liquid crystal panel of this embodiment is used, regardless of whether the TN liquid crystal is right-handed or left-handed, since the shape of the opening of the pixel is basically the same on the left and right, even if the liquid crystal is rotationally displaced, the same light valve can be used. way of identification. Therefore, when the light valves 100R, 100G, and 100B having different rotation directions of liquid crystals are synthesized by the prism, color unevenness and decrease in contrast do not occur in the displayed image, so that a high-quality projector can be realized.

In Fig. 20, a portable personal computer (PC) 1200 compatible with multimedia as another example of electronic equipment has the above-mentioned liquid crystal panel 100 in its upper cover casing, and also has a keyboard 1202 for accommodating CPU, memory, modem, etc. Ontology 1204 together.

In addition, as shown in FIG. 21 , in the case of the liquid crystal panel 100 without the driver circuit 1004 and the display information processing circuit 1002 installed, the IC 1324 including the driver circuit 1004 and the display information processing circuit 1002 is placed on the periphery of the TFT array substrate 10 The anisotropic conductive film inside is physically and electrically connected to a TCP (Tape Carrier Component) mounted on a polyimide tape 1322, and can be produced, sold, used, etc. as a liquid crystal device.

In addition to the electronic equipment described with reference to FIGS. 19 to 21, examples of the electronic equipment shown in FIG. Notebooks, desktop calculators, word processors, engineering workstations (EWS), portable phones, TV phones, POS terminals, and devices with touch pads, etc.

As described above, according to this embodiment, by employing a relatively simple structure, a liquid crystal panel and an electronic device including the liquid crystal panel can be realized without reducing the processing yield and the pixel opening ratio even if the pixel size is reduced.

According to the liquid crystal panel of the present invention, since the raising film is formed under the contact hole opening on the interlayer insulating film for connecting the drain region of the TFT as a switching element to the pixel electrode, the interlayer The surface of the insulating film is flattened. Therefore, the level difference in the region where the contact hole is formed can be made gentle. Therefore, the rotational displacement of the liquid crystal can be prevented, and the expansion of the opening shape and size of the contact hole can be suppressed when exposing the resist mask in the photolithography process.

According to the liquid crystal panel of the present invention, the formation position of the contact hole for connecting the drain region of the TFT as the switching element to the pixel electrode in the interlayer insulating film is located for supplying the corresponding pixel electrode. The approximate center position between the data line of the image signal and the data line adjacent to the data line can prevent the short circuit between the data line and the pixel electrode, so even if the pixel is miniaturized, it will not cause a decrease in the processing yield. reduce.

Claims (9)

1. liquid crystal board, liquid crystal is enclosed between the a pair of the 1st and the 2nd substrate, on above-mentioned the 1st substrate, the multi-strip scanning line that has many data lines, intersects with above-mentioned many data lines, with a plurality of thin film transistor (TFT)s of corresponding setting of intersecting of above-mentioned each data line and above-mentioned each sweep trace, corresponding and by a plurality of pixel capacitors and the memory capacitance of rectangular configuration with above-mentioned a plurality of thin film transistor (TFT)s

Above-mentioned thin film transistor (TFT) disposes gate electrode at semiconductor layer by gate insulating film, on above-mentioned semiconductor layer and above-mentioned gate electrode, dispose interlayer dielectric, the drain region of above-mentioned thin film transistor (TFT) is connected with above-mentioned pixel capacitors by the contact hole that forms on above-mentioned interlayer dielectric, the electric capacity line that is used as an electrode of above-mentioned memory capacitance disposes along above-mentioned sweep trace

It is characterized in that: above-mentioned contact hole, be configured between above-mentioned each sweep trace and above-mentioned each electric capacity line, and film is increased in formation below above-mentioned contact hole.

2. liquid crystal board according to claim 1, it is characterized in that: above-mentioned sweep trace and above-mentioned electric capacity line form simultaneously with same material, the dielectric film of above-mentioned gate insulating film and above-mentioned memory capacitance forms simultaneously with same material, and forms another electrode of above-mentioned semiconductor layer and above-mentioned memory capacitance simultaneously with same material.

3. liquid crystal board according to claim 1 and 2 is characterized in that: above-mentioned at least a portion of increasing film, form around above-mentioned contact hole, and at least one side in above-mentioned sweep trace and the above-mentioned electric capacity line, to increase membrane plane recessed along above-mentioned.

4. liquid crystal board according to claim 1 is characterized in that: the above-mentioned film of increasing, and to form with above-mentioned sweep trace and the non-overlapping mode of above-mentioned electric capacity line.

5. liquid crystal board according to claim 1 is characterized in that: the above-mentioned film of increasing, and by constituting with the roughly the same thickness of at least one side of above-mentioned sweep trace and above-mentioned electric capacity line.

6. liquid crystal board according to claim 1 is characterized in that: the above-mentioned film of increasing is the conducting film that forms simultaneously with same material with above-mentioned data line on above-mentioned drain region.

7. liquid crystal board according to claim 1 is characterized in that: the above-mentioned film of increasing is the conducting film that forms under above-mentioned drain region.

8. liquid crystal board, on substrate, the multi-strip scanning line that has many data lines, intersects with above-mentioned many data lines, with the thin film transistor (TFT) of above-mentioned each data line and the corresponding setting of above-mentioned each sweep trace, with a plurality of pixel capacitors of the corresponding setting of above-mentioned a plurality of thin film transistor (TFT)s, and memory capacitance

Above-mentioned thin film transistor (TFT) disposes gate electrode at semiconductor layer by gate insulating film, on above-mentioned semiconductor layer and above-mentioned gate electrode, dispose interlayer dielectric, the drain region of above-mentioned thin film transistor (TFT) is electrically connected by contact hole and the above-mentioned pixel capacitors that forms on above-mentioned interlayer dielectric, the electric capacity line of an electrode of above-mentioned memory capacitance disposes along above-mentioned sweep trace

It is characterized in that: above-mentioned contact hole is configured between above-mentioned each sweep trace and above-mentioned each electric capacity line, forms below above-mentioned contact hole and increases film, and the above-mentioned film of increasing is the conducting film that is electrically connected with above-mentioned drain region.

9. liquid crystal board, it is characterized in that: liquid crystal with clamping in a pair of substrate and the above-mentioned a pair of substrate, on a substrate of above-mentioned a pair of substrate, the multi-strip scanning line that has many data lines, intersects with above-mentioned many data lines, with a plurality of thin film transistor (TFT)s of above-mentioned each data line and the corresponding setting of above-mentioned each sweep trace, corresponding and by a plurality of pixel capacitors of rectangular configuration with above-mentioned a plurality of thin film transistor (TFT)s

On an above-mentioned substrate, to above-mentioned pixel capacitors give respectively decide memory capacitance the electric capacity line dispose along above-mentioned sweep trace,

Above-mentioned pixel capacitors is electrically connected by the drain region of contact hole with the semiconductor layer that constitutes above-mentioned thin film transistor (TFT),

Above-mentioned contact hole be used for to above-mentioned pixel capacitors supply with picture signal data line and and the data line of this data line adjacency between approximate centre position and perforate between adjacent electric capacity line and sweep trace,

Below the above-mentioned drain region of the above-mentioned semiconductor layer that constitutes the above-mentioned thin film transistor (TFT) under the above-mentioned contact hole, be provided with by what the conducting film that is electrically connected with above-mentioned drain region constituted and increase film,

The above-mentioned film of increasing begins to be arranged under the above-mentioned contact hole not and above-mentioned sweep trace and above-mentioned electric capacity line overlaid.

Images