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CN101088160B - 半导体模块和电力母线系统布置 - Google Patents

半导体模块和电力母线系统布置 Download PDF

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CN101088160B
CN101088160B CN2005800442792A CN200580044279A CN101088160B CN 101088160 B CN101088160 B CN 101088160B CN 2005800442792 A CN2005800442792 A CN 2005800442792A CN 200580044279 A CN200580044279 A CN 200580044279A CN 101088160 B CN101088160 B CN 101088160B
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semiconductor
semiconductor element
substrate
power
contact
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CN101088160A (zh
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诺伯特·塞利格
安德烈亚斯·富克斯
马克-马赛厄斯·巴克兰
马赛厄斯·霍夫施泰特
汉斯-乔基姆·克纳克
安德烈亚斯·内格尔
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Siemens Corp
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Abstract

本发明涉及一种具有至少一个半导体模块(2)和至少一个电力母线系统(3)的布置，其中，所述半导体模块具有至少一个基板(6)和至少一个布置在所述基板上的半导体元件(21，22)，所述半导体元件具有一电触头(24)和至少一个其他电触头(27)，所述母线系统具有至少一个用于为所述半导体元件的触头提供一供电电压的供电母线(31)，为使所述供电母线与所述半导体元件的其他触头之间彼此电绝缘，所述半导体元件和/或所述供电母线上布置有一电绝缘膜(7)。所述半导体元件的触头采取的是平面接触，其中，使用绝缘膜来实现所述平面接触。由于绝缘膜的存在，无需再在半导体模块上浇注硅。由此产生一简单而紧凑的结构。本发明特别用于提供功率半导体模块的功率半导体元件。功率半导体模块特别用在转换器上。

Description

半导体模块和电力母线系统布置
技术领域
本发明涉及一种半导体模块和电力母线系统(电流母线系统)布置。
背景技术
所述半导体模块例如为一具有一基板(电路载体、载体)、且所述基板上安装有多个以相应方式电气相连的半导体元件的半导体模块。半导体元件的触头在半导体模块中的内部连接通过使用接合线而实现。为实现电绝缘，接合线和半导体元件均被灌封在一灌封材料中。所述灌封材料例如为硅。封装半导体模块布置在一外壳中。外壳用于保护半导体模块，同时还用作电连接件(负载端子)的载体。电连接件对外与电力母线系统导电相连。电力母线系统具有一供电母线，通过所述供电母线可向半导体模块的其中一个触头提供一供电电压。
WO 03/030247 A2中公开了一种通过接合线来实现触头内部连接的方案。其中，以大面积及平面接触的方式接触布置在基板上的半导体元件的电触头的接触面。为实现接触，在半导体元件上层压一绝缘膜。通过在绝缘膜上开窗口来露出半导体元件的接触面，随后通过在接触面上和绝缘膜区域内进行金属沉积处理来实现电接触。
发明内容
本发明的目的是提供一种由半导体模块及其电力母线系统构成的简单而紧凑的布置。
为达成这一目的，提供一种由至少一个半导体模块和至少一个电力母线构成的布置，其中，半导体模块具有至少一个基板和至少一个半导体元件，所述半导体元件布置在该基板上，且具有一电触头和至少一个其他电触头；所述母线系统具有至少一个用于为半导体元件的触头提供一供电电压的供电母线；为使供电母线与半导体元件的其他触头之间彼此电绝缘，半导体元件和/或供电母线上布置有一电绝缘膜。
所述布置对于功率半导体模块而言特别有利。因此根据一特别实施方案，所述半导体模块为一功率半导体模块，所述半导体元件为一选自绝缘栅双极晶体管(IGBT)、二极管、金属氧化物半导体场效应管(MOSFET)、晶闸管(Tyristor)和/或双极晶体管的功率半导体元件。
由于所述绝缘膜的存在，便无需再采取例如浇注硅而实现的附加绝缘措施。供电母线只与待接触的电触头导电相连。此外也无需再使用外壳。半导体元件或具有多个半导体元件的半导体模块在无外壳的情况下，与电力母线系统相连。由此会产生一个与现有技术相比更简单、更紧凑的布置。
半导体元件优选地以一种会使其触头的电接触面远离基板的方式布置在基板上，半导体元件的其他触头的接触面朝向基板。半导体元件例如通过这一接触面焊接或粘接在基板上。
根据一特别的实施方案，半导体元件布置在一基板上，绝缘膜以这样的方式安装在半导体元件和基板上，使得半导体元件的一表面轮廓和/或基板的一表面轮廓体现在绝缘膜的表面轮廓中，该轮廓表面远离半导体元件和/或基板的。其中，绝缘膜可采取粘接的安装方式。优选地，绝缘膜被层压在半导体元件和基板上。最好在不使用胶粘剂的情况下实现所述层压处理，也就是说，绝缘膜并非以粘接方式安装在半导体元件和基板上。此外也可附加地或仅在电力母线系统的供电母线上层压或粘接一绝缘膜。
优选以平面接触的方式，也就是不通过接合线而实现对半导体模块的半导体元件的触头的电接触。借此可充分利用绝缘膜的绝缘作用，进行大面积接触。通过平面接触可实现对半导体元件的低电感接触。借助平面接触还可实现比接合线接触更坚固的结构。
下面对一种具有电绝缘膜且对其半导体元件的触头进行平面接触的半导体模块的制备方法进行详细说明：此处涉及的半导体模块具有一基板和多个布置在所述基板上的半导体元件。为制备所述半导体模块，提供一例如为直接铜接合(Direct Copper Bonding，DCB)基板，所述基板上借助一导电连接件安装有制备半导体模块所需的半导体元件，这些半导体元件通过导电通路以相应方式彼此电气相连。DCB基板具有一用氧化铝(Al2O3)或氮化铝(AlN)制成的承载层。所述承载层的两侧安装有建构成导电通路的导电铜层。所述导电连措施例如为一焊接剂或一导电胶粘剂。将半导体元件焊接或粘接在基板上，也可考虑使用一低温连接技术(NTV)。借助上述方法不仅可实现对半导体元件的电接触，还可将其机械固定在基板上。还可考虑将电触头制备成一个导电的连接措施。半导体元件不采取机械固定的方式，这一点例如通过采用一具有导电能力的膏体(导电膏)即可实现。
在安装在基板上的半导体元件上层压一绝缘膜，所述绝缘膜例如为一含有聚酰亚氨的塑料薄膜(聚酰亚氨薄膜)。例如在真空条件下进行这一层压步骤。为此例如使用一真空挤压机。通过在真空条件下进行的层压处理，可在半导体元件和绝缘膜之间以及基板和绝缘膜之间形成一特别牢固而紧密的连接。必要时可在层压步骤之后进行一温度处理步骤。借此可提高绝缘膜与半导体元件及基板之间的连接强度。特别在使用一导电膏的情况下，层压绝缘膜可起到将半导体元件定位和/或机械固定在基板上的作用。
将绝缘膜层压到半导体元件上后，要将半导体元件的待接触的触头暴露出来，为此例如实施一光刻处理步骤。或者，也可使用激光烧蚀法。这两种方法均是通过材料去除来在绝缘膜上开一窗口。通过这一窗口露出半导体元件的触头。随后在所述触头上沉积导电材料。为在绝缘膜上建构导电通路，同样也在绝缘膜上沉积导电材料。以气相和/或液相形式进行所述沉积处理，例如使用一物理气相沉积法(Physical Vapour Deposition，PVD)或化学气相沉积法(Chemical Vapor Deposition，CVD)来进行所述气相沉积。液相沉积以电解方式进行，进行电解沉积。其中，可重复进行各处理步骤，直至产生所需层厚。也可制备具有不同功能的部分金属化层。借此可产生一多层结构，具有多个层叠布置的金属化分层。
为能通过绝缘膜获得有效的电绝缘效果，需为绝缘膜选定一为此所需的膜强度(膜厚)。必要膜厚取决于各种因素，例如绝缘膜的绝缘材料或半导体元件的类型。因此，可考虑选择从几个μm到几百个μm范围的膜厚。
为能通过绝缘膜获得必要的绝缘效果，可层压一尽可能厚的单个绝缘膜。但也可通过多个层叠的分绝缘膜来实现相应的绝缘效果，绝缘膜具有一由至少两个层叠布置的分绝缘膜构成的多层结构。借此可在绝缘膜的总膜厚相对较小的情况下也能取得有效的绝缘效果。
根据一特别实施方案，所述布置为一具有一中间电路电容器的转换器装置，且所述中间电路电容器通过供电母线与半导体模块的半导体元件相连。所述转换器由不同组件(元件)构成。所述转换器例如具有多个功率组件，其中一个功率组件例如为一由多个功率半导体元件构成的开关。所述转换器的另一功率组件例如为一中间电路或中间电路的一组成部分。所述组成部分例如为所述中间电路电容器。根据转换器的具体拓扑结构，中间电路电容器采用不同的建构方式，例如为一电解电容器。也可考虑使用多层电容器形式的中间电路电容器。所述多层电容器可实施为分立元件。特别是还可考虑将多层电容器和母线一起建构成转换器的一电力部分。
半导体模块和电力母线系统可永久性地彼此相连，母线系统与半导体模块例如粘接或焊接在一起。举例而言，半导体元件的一待接触的触头或半导体模块的一连接导体与供电母线焊接或粘接在一起。半导体模块和电力母线系统之间也可采取可解除的连接方式，也就是说，半导体模块和电力母线系统之间或半导体元件的一触头和供电母线之间的连接可以非破坏性方式解除。可解除的连接例如通过一压力接点、螺旋接点或插式接点而实现。例如通过一弹簧接点建立压力接点。
根据一特别实施方案，半导体模块的基板与一冷却装置导热地相连。所述冷却装置可建构为使一冷却流体流过基板。如果基板由一例如为氧化铝或氮化铝的导热材料制成，就可通过基板有效地将热量从功率半导体元件散发到冷却装置的冷却流体中。其中，基板自身为冷却装置的一组成部分。
根据一特别实施方案，所述冷却装置为一冷却体。基板例如借助一导热胶粘剂粘接在所述冷却体上，借此可通过基板和所述胶粘剂将功率半导体元件的热量有效地散发到冷却体上。所述冷却体例如为一用铝或铜制成并且配有散热片。
所述半导体模块可具有一带有多个半导体元件的单个基板，优选地，设置多个用于对上述半导体元件的各触头进行电接触的供电母线。其中，一个供电母线可同时为多个半导体元件的触头提供必要电压。其中，电流母线设计为可为半导体模块的半导体元件的工作提供一所需电流。这一点特别适用于功率半导体模块。
根据一特别实施方案，所述半导体模块具有多个基板，各基板分别具有至少一个半导体元件，所述半导体元件具有一触头和至少一个其他触头。其中，基板上的半导体元件的触头与母线系统的一供电母线接触，所述半导体元件的其他触头借助一布置在半导体元件上的电绝缘膜与供电母线彼此电绝缘。借此可通过一电力母线实现对复数个半导体元件的电触头的电接触，而所述半导体元件可布置在复数个基板上。
综上所述，借助本发明可实现下列重要优点：
一借助本发明可实现一简单而紧凑的半导体模块和电力母线系统布置；
—由于使用绝缘膜，无需再采取浇注硅而实现附加绝缘；
—无需设置一个用于整合电连接件的外壳，该外壳须与外部电力母线相连。
附图说明
下面借助附图所示的多个实施例，对本发明作进一步说明。其中各附图均为示意性的并不代表现实比例：
图1为一布置的横截面侧视图，所述布置具有至少一个半导体模块与一电力母线；
图2为图1所示的布置的局部图；
图3为图1所示的布置的另一局部图；
图4为另一布置的截面图；
图5为供电母线与连接导体之间可分开的弹簧接点示意图。
具体实施方式
根据第一实施例，布置1具有多个半导体模块2与一个电力母线系统3的。
电力母线3具有一多层结构，母线3由一供电母线31、一其他供电母线32以及一布置在供电母线31和32之间的绝缘层33构成。两个供电母线31和32通过绝缘层33而彼此电绝缘。供电母线31和32上可施加不同的电压。
半导体模块2为功率半导体模块23，分别具有一基板6。所述基板上分别安装有至少一个半导体元件21。所述半导体元件21为MOSFET形式的功率半导体元件22。
功率半导体模块23的基板6均为DCB基板，每个DCB基板6均由一氧化铝承载层61和设置在其两侧的铜导电层62和63构成。导电层62上焊接有半导体元件22，形成相应的导电通路。
每个焊接在导电层62上的功率半导体元件22均具有一远离基板6的接触面24(图3)。为此，功率半导体元件22分别通过一其他触头，例如一MOSFET的漏极触头的一接触面27，焊接在导电层62上。其替代方案可以是，功率半导体元件22与导电层62通过粘接，或者采用低温连接技术，或者仅采用导电膏来实现相互电接触，而非机械固定。
为实现对所述功率半导体元件22的接触面24(例如MOSFET的源极触头)的大面积和平面地电接触，功率半导体元件22上用真空技术层压有一绝缘膜7。其中，绝缘膜7这样层压在基板6和功率半导体元件22上，使得功率半导体元件22的一轮廓表面25与基板6的一轮廓表面64体现在绝缘膜7的表面轮廓72中，所述表面轮廓(72)远离所述基板6和功率半导体元件22。使用导电膏时，通过绝缘膜7实现功率半导体元件22在基板6上的机械固定。通过在绝缘膜7上开一窗口71，露出功率半导体元件22的触头或接触面24。通过激光烧蚀来形成窗口71。通过一由导电材料构成的多层沉积物26来对接触面24进行平面电接触。
通过使用绝缘膜7来实现对功率半导体模块23的功率半导体元件22的平面接触，可确保功率半导体元件22的接触面24与电力母线3的一供电母线31之间的电接触。与此同时，功率半导体元件23的其他接触面27与电力母线3的供电母线31彼此电绝缘。其他接触面27与电力母线3的一其他供电母线32之间彼此电接触。为对电接触进行控制，沉积物26上层压有一其他绝缘膜8。绝缘膜8具有一窗口81，通过这一窗口可实现沉积物26与供电母线31之间的接触。
为实现对一功率半导体元件22的接触面24的电接触，电力母线3的供电母线31与功率半导体模块的一接触头28导电相连。接触头28由一安装在基板6或一铜导电层621上的连接导体29提供。与功率半导体元件22的其他触头27相接触的导电层62与导电层621之间彼此电绝缘。连接导体29具有用于对功率半导体元件22的接触面24进行电接触的金属沉积物26。供电母线31和连接导体29在接触头28处焊接在一起(图2)。作为替代方案，供电母线31和连接导体也可借助一可分开的弹簧触头41彼此导电相连(图5)。
为对所述布置1进行冷却，功率半导体模块23安装在一共用冷却体4上。根据第一实施方式，功率半导体模块23分别通过DCB基板6的其他导电层62焊接在所述冷却体上。作为替代方案，也可借助一具有导热能力的导电胶粘剂将功率半导体模块固定在所述冷却体上。
根据另一实施例，所述布置1为一转换器装置11(图4)。除可实现一电源电路12的功率半导体模块23外，所述转换器装置还具有中间电路电容器13。所述中间电路电容器13与母线系统3相连，与母线3共同构成所述转换器装置的一电力部分。所述中间电路电容器13为一多层电容器。

Claims (10)

1. 一种由至少一个半导体模块(2，23)和至少一个电力母线(3)构成的布置，其中，
所述半导体模块(2)具有至少一个基板(6)和至少一个布置在所述基板(6)上的半导体元件(21，22)，所述半导体元件具有一电触头(24)和至少一个其他电触头(27)，
所述母线(3)具有至少一个用于为所述半导体元件(21)的触头(24)提供一供电电压的供电母线(31)，以及
为使所述供电母线(31)与所述半导体元件(21，22)的其他触头(27)之间彼此电绝缘，所述半导体元件(21，22)和/或所述供电母线(31)上布置有一电绝缘膜(7)。
2. 根据权利要求1所述的布置，其中，所述半导体元件(21，22)以一种会使其触头(24)的一电接触面远离所述基板(6)的方式布置在所述基板(6)上。
3. 根据权利要求1或2所述的布置，其中，所述绝缘膜(7)以这种方式安装在所述半导体元件(22)和所述基板(6)上，使得所述半导体元件(21，22)的一表面轮廓(25)和/或所述基板(6)的一表面轮廓(64)体现在所述绝缘膜(7)的轮廓表面(72)中，所述轮廓表面(72)远离所述半导体元件(21，22)和/或所述基板(6)。
4. 根据权利要求1至3中任一项权利要求所述的布置，其中，所述绝缘膜(7)层压在所述半导体元件(21，22)和/或所述供电母线(31)上。
5. 根据权利要求1至4中任一项权利要求所述的布置，其中，所述半导体元件(21，22)通过所述绝缘膜(7)固定在所述基板(6)上。
6. 根据权利要求1至5中任一项权利要求所述的布置，其中，所述半导体模块(2)为一功率半导体模块(23)，所述半导体元件(21)为一选自IGBT、二极管、MOSFET、晶闸管和/或双极晶体管的功率半导体元件(22)。
7. 根据权利要求6所述的布置，其中，所述布置(1)为一具有一中间电路电容器(13)的转换器装置(11)，且所述中间电路电容器(13)通过所述供电母线(31)与所述功率半导体模块(23)的功率半导体元件(22)相连。
8. 根据权利要求1至7中任一项权利要求所述的布置，其中，所述半导体模块(2)与所述供电母线(31)可分开地连接在一起。
9. 根据权利要求2至8中任一项权利要求所述的布置，其中，所述半导体模块的基板(6)与一冷却装置(4)导热相连。
10. 根据权利要求1至9中任一项权利要求所述的布置，其中，
所述半导体模块(2)具有多个基板(6)，其分别具有至少一个半导体元件(21，22)，所述半导体元件具有一触头(24)和至少一个其他触头(27)；
所述基板(6)上的半导体元件(21，22)的触头(24)与所述母线(3)的一供电母线(31)接触；以及
所述半导体元件(21，22)的其他触头(27)借助一布置在所述半导体元件(21，22)上的电绝缘膜(7)与所述供电母线(31)彼此电绝缘。
CN2005800442792A 2004-12-22 2005-11-28 半导体模块和电力母线系统布置 Expired - Fee Related CN101088160B (zh)

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PCT/EP2005/056257 WO2006067021A1 (de) 2004-12-22 2005-11-28 Anordnung eines halbleitermoduls und einer elektrischen verschienung

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Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006006423B4 (de) * 2006-02-13 2009-06-10 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul und zugehöriges Herstellungsverfahren
DE102006057248B4 (de) * 2006-12-05 2009-07-16 Semikron Elektronik Gmbh & Co. Kg Halbleitermodul
DE102007003875A1 (de) * 2007-01-25 2008-08-07 Siemens Ag Stromrichter
DE102008017454B4 (de) * 2008-04-05 2010-02-04 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit hermetisch dichter Schaltungsanordnung und Herstellungsverfahren hierzu
DE102009015757A1 (de) * 2009-04-01 2010-10-14 Siemens Aktiengesellschaft Druckunterstützung für eine elektronische Schaltung
DE102009046403B4 (de) 2009-11-04 2015-05-28 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul in Druckkontakttechnik
DE102010014940B4 (de) * 2010-04-14 2013-12-19 Semikron Elektronik Gmbh & Co. Kg Leistungshalbleitermodul mit Anschlusselementen
DE102012215651A1 (de) * 2012-09-04 2014-03-06 Semikron Elektronik Gmbh & Co. Kg Verbindungselement zur elektrisch leitenden Verbindung einer ersten Leistungselektronikeinrichtung mit einer zweiten Leistungselektronikeinrichtung
DE102013008193A1 (de) 2013-05-14 2014-11-20 Audi Ag Vorrichtung und elektrische Baugruppe zum Wandeln einer Gleichspannung in eine Wechselspannung
EP2804209A1 (en) * 2013-05-17 2014-11-19 ABB Technology AG Moulded electronics module
DE102013215592A1 (de) * 2013-08-07 2015-02-12 Siemens Aktiengesellschaft Leistungselektronische Schaltung mit planarer elektrischer Kontaktierung
EP2966934B1 (de) 2014-07-08 2016-09-14 Eberspächer catem GmbH & Co. KG Steuervorrichtung für eine elektrische Heizvorrichtung und Verfahren zu deren Herstellung

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4881117A (en) * 1983-02-28 1989-11-14 Sgs-Ates Componenti Elettronici S.P.A. Semiconductor power device formed of a multiplicity of identical parallel-connected elements
CN1443369A (zh) * 2000-05-17 2003-09-17 欧佩克·欧拉帕舍·盖塞尔沙夫特·冯·雷斯坦沙布莱特两合公司 外壳器件及其中所用的接触单元

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3348105A (en) * 1965-09-20 1967-10-17 Motorola Inc Plastic package full wave rectifier
EP0584668B1 (de) * 1992-08-26 1996-12-18 eupec Europäische Gesellschaft für Leistungshalbleiter mbH & Co. KG Leistungshalbleiter-Modul
DE19617055C1 (de) * 1996-04-29 1997-06-26 Semikron Elektronik Gmbh Halbleiterleistungsmodul hoher Packungsdichte in Mehrschichtbauweise
KR100214560B1 (ko) * 1997-03-05 1999-08-02 구본준 반도체 멀티칩 모듈
DE19847029A1 (de) * 1998-10-13 2000-04-27 Semikron Elektronik Gmbh Umrichter mit niederinduktivem Kondensator im Zwischenkreis
AU2002340750A1 (en) * 2001-09-28 2003-04-14 Siemens Aktiengesellschaft Method for contacting electrical contact surfaces of a substrate and device consisting of a substrate having electrical contact surfaces
DE10314172B4 (de) * 2003-03-28 2006-11-30 Infineon Technologies Ag Verfahren zum Betreiben einer Anordnung aus einem elektrischen Bauelement auf einem Substrat und Verfahren zum Herstellen der Anordnung

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4881117A (en) * 1983-02-28 1989-11-14 Sgs-Ates Componenti Elettronici S.P.A. Semiconductor power device formed of a multiplicity of identical parallel-connected elements
CN1443369A (zh) * 2000-05-17 2003-09-17 欧佩克·欧拉帕舍·盖塞尔沙夫特·冯·雷斯坦沙布莱特两合公司 外壳器件及其中所用的接触单元

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DE102004061936A1 (de) 2006-07-06
DE502005004060D1 (de) 2008-06-19
EP1829107A1 (de) 2007-09-05
WO2006067021A1 (de) 2006-06-29
ATE394793T1 (de) 2008-05-15
EP1829107B1 (de) 2008-05-07

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