CN101087132A - Adjustment method of clock fifty percent idle percent based on phone mixing - Google Patents

Abstract

The invention discloses a clock 50% duty ratio adjustment method based on phase synthesis, the steps of which are: (1), pulse generation: through the pulse generation circuit, the input source clock is converted into a narrow pulse signal, and the frequency remains unchanged (2), half-period delay: the narrow pulse signal obtained in step (1) is delayed by half a period; (3), mirror image delay: the pulse signal delayed by half-period in step (2) is delayed by half-period again, obtains A pulse signal with a difference of one period from the pulse signal in step (1); (4), phase synthesis: phase superimpose the pulse signals output in step (2) and step (3), and obtain a frequency that is twice the source clock Pulse signal; (5), frequency division by two: the pulse signal synthesized in the step (4) is divided by two to obtain the same as the source clock frequency, the phase is consistent and the duty cycle is 50% of the clock signal as the output signal. The invention can adjust the 50% duty cycle of the clock signal whose frequency and duty cycle both change within a certain range, has strong anti-Voltage Temperatre interference ability, and has high quality of the clock waveform after frequency division and output.

Description

Clock 50% Duty Cycle Adjustment Method Based on Phase Synthesis

technical field

The invention mainly relates to the field of a method for adjusting a 50% duty cycle of a CMOS clock signal, in particular to a method for adjusting a 50% duty cycle of a clock based on phase synthesis.

Background technique

With the continuous improvement of the main frequency of integrated circuits, the clock cycle becomes shorter and shorter. In some circuits with strict timing requirements, such as register read and write circuits, and clock signal double-edge sampling circuits in DDR technology, the slight jitter of the clock edge will have a great impact on the timing relationship of the circuit, and even cause the system to fail to work correctly. In a CMOS circuit, due to factors such as the mismatch between the driving capabilities of the PMOS transistor and the NMOS transistor, and the interference of the parasitic capacitance distribution of the interconnection, the source clock signal may be seriously distorted in duty cycle during transmission. For this reason, there is an urgent need to adjust the duty cycle of such clocks to improve system performance.

At present, there are many ways to adjust the duty ratio: phase-locked loop PLL (Phase Locked Loop) method, complementary phase synthesis CPB (Complementary Phase Blending) method, delay locked loop DLL (Delay Locked Loop) method, pulse width control loop PWCL ( Pulse Width Control Loop) method, etc., the main body of these methods are analog circuits.

In the PLL method, due to the existence of a feedback loop, the circuit design is complex, the adjustment accuracy is high but it is prone to fluctuations, and it usually takes hundreds of clock cycles to lock the phase. Due to its own structural limitations, it is difficult for the analog PLL to generate a higher frequency 50% duty cycle clock signal, and the design requirements are extremely accurate to ensure that the circuit can still work normally when process deviations and voltage temperature changes occur. In the complementary phase synthesis method, due to the reliance on complementary clock signals, the method is no longer applicable when the devices are mismatched. When the duty cycle of the input clock is around 50%, a more accurate 50% duty cycle clock can be obtained; but when the duty cycle of the input clock deviates from 50%, the duty cycle of the output clock is not ideal, and the application range is narrow . In the DLL method, the phase detector is slow, which limits the improvement of regulation performance. When the pulse width control method is used, the change of the phase is likely to interfere with the locking result of the PLL or DLL, and even cause locking failure in bad cases.

It can be seen that there are many common defects in using the analog method to realize the duty ratio adjustment, and the anti-interference ability is poor. However, some open-loop digital clock duty ratio adjustment technologies do not consider the phase deviation between the output clock and the source clock, and the adjustment operation is too long, generally requiring 5-10 clock cycles to complete. The present invention adopts a pure digital method and proposes a clock signal 50% duty cycle adjustment method based on phase synthesis technology, which eliminates various defects in the above design, and only needs 4 clock cycles for the adjustment operation, and there is no complicated feedback loop, making the duty cycle adjustment easier and more efficient.

Contents of the invention

The problem to be solved by the present invention is that: aiming at the technical problems existing in the prior art, the present invention provides a clock signal capable of adjusting 50% duty cycle of a clock signal whose frequency and duty cycle both change within a certain range, and has anti-VT The 50% duty ratio adjustment method of the clock based on the phase synthesis has the advantages of strong interference ability and high quality of the clock waveform after the frequency division output.

In order to solve the above-mentioned technical problems, the solution proposed by the present invention is: a clock 50% duty ratio adjustment method based on phase synthesis, characterized in that the steps are:

(1) Pulse generation: through the pulse generation circuit, the input source clock is converted into a narrow pulse signal, and the frequency remains unchanged;

(2), half-period delay: the narrow pulse signal gained in step (1) is delayed by half-period;

(3), mirror image delay: the pulse signal that has delayed half cycle in step (2) is delayed half cycle again, obtains the pulse signal that differs one cycle with the pulse signal in step (1);

(4), phase synthesis: the pulse signal output in step (2) and step (3) is carried out phase superposition, obtains the pulse signal that frequency is 2 times of source clock;

(5), frequency division by two: the pulse signal synthesized in step (4) is divided by two to obtain a clock signal with the same frequency as the source clock, consistent phase and a duty cycle of 50% as an output signal.

The concrete process of described step (2) is:

(1) Clock period measurement: The measurement of the clock period is completed by measuring the delay line. The pulse signal obtained in step (1) is divided by two and used as the clock CLK of the measurement delay line. The duration of such a high level is just One clock cycle of the source clock; after the reset circuit is turned off, the high-level signal starts to propagate in the measurement delay line through the initial delay line in the half-cycle delay line, and the input of the initial delay line is always set to high level and reset to low level The pulse signal is always generated within half a cycle when the source clock signal is low, so that the propagation and sampling of the high-level signal can be performed alternately; when the reset signal is low, the clock signal is also low, and the sampling circuit starts sampling delay The output level of the unit, the position where the high-level signal propagation stops, that is, the output terminal of the sampling result, corresponds to the length of the source clock signal cycle. When the reset signal is set high, the sampler is turned off, and the unit in the measurement delay line is reset and cleared. Zero, ready for the next period measurement. After the clock signal is set high again, the high-level signal continues to propagate forward along the measurement delay line;

(2) Clock phase adjustment: a half-period delay is performed on the pulse signal whose period has been measured, and the clock phase adjustment is completed by a variable delay line.

Compared with the prior art, the present invention has the advantages of:

1. The invention has strong anti-VT (Voltage, Temperature) interference ability. When the voltage fluctuates within the allowable range, the mirror delay circuit (MDL) and the main circuit are affected by the same at the same time, so that the circuit delay remains highly consistent, and the same is true when the temperature changes;

2. In the present invention, the two frequency division circuit technology is used, and the clock waveform after the frequency division output of the phase synthesis signal is high in quality, and the clock edge transition is abnormally steep, which is very close to the ideal clock;

3. According to the principle of mirror delay, the present invention adopts a delay full compensation strategy, so that each step realizes high-precision delay matching, greatly reduces the phase deviation between the output clock and the source clock, and maintains the synchronization relationship between the input and output signals .

Description of drawings

Fig. 1 is a schematic flow sheet of the present invention;

Fig. 2 is a timing diagram corresponding to the process in Fig. 1;

Fig. 3 is a structural schematic diagram of a half-period delay line;

Fig. 4 is the structural representation of measuring delay line;

Fig. 5 is a schematic diagram of a logic structure of a variable delay line composed of a NAND gate array.

Detailed ways

The present invention will be described in further detail below in conjunction with the accompanying drawings and specific embodiments.

The present invention uses a pure digital method and utilizes the principle of mirror delay to realize phase synthesis duty ratio adjustment without a feedback loop. The key to making the output clock reach a 50% duty ratio is how to generate a mirror image with a phase difference of 180° from the source clock. clock. In the process of measuring the clock period, according to the principle of mirroring, the numerically controlled delay line will delay the phase of the source clock signal by half a period, and then, the phase synthesis of the two clocks with a phase difference of half a period is carried out through the two-input OR gate. In this way, the synthesized clock has an edge jump at every half cycle point, which is equivalent to multiplying the frequency of the source clock. Obviously, the clock after phase synthesis passes through the frequency division circuit by two, and the output is the same frequency clock with a duty cycle of 50%.

In order to avoid phase overlap after clock phase synthesis, a narrow pulse generation circuit must be used to uniformly shape the clocks with different original input duty ratios into narrow pulse signals. However, there is a certain delay in the pulse generation circuit, and there is inevitably a clock skew when the source clock and the half-period delayed clock are phase-combined, and there is also a phase skew when the synthesized clock passes through the frequency division circuit. To compensate for these skews, a matching delay line MDL (Matching Delay Line) is added between the pulse generator and the OR gate. The delay of the matching delay line should be

t _MDL =t _CLK -t _PULSE -t _OR -t _FD

Note: t _MDL - matched delay line delay, t _CLK - clock period

t _PULSE - pulse generator delay, t _OR - OR gate delay

t _FD - Delay of frequency divider circuit by two

Thus, the rising edge of the output clock is skewed by exactly one clock period,

t _SKEW =t _PULSE +t _MDL +t _OR +t _FD =t _CLK

In this way, the delay of each part of the circuit is fully compensated, that is, the output without skew is realized. However, considering that it is difficult to achieve accurate full-cycle delay matching under different clock frequencies, and in order to save the number of delay units, MDL finally adopts the delay of the output signal of the variable delay line that has been delayed by half a cycle in the half-cycle delay line. half cycle to achieve the purpose of delaying the whole cycle, so that the design of MDL can completely transplant the variable delay line logic in the half cycle delay line, thus greatly reducing the design difficulty.

In summary, the technical scheme of the clock 50% duty ratio adjustment method based on phase synthesis in the present invention is shown in Figure 1 and Figure 2, and consists of five steps, which include: pulse generation, half-cycle delay, mirror delay, Phase synthesis and two-way frequency output. After the input clock goes through these five steps, the output is a high-quality clock with a duty cycle of 50%.

(1), pulse generation

Pulse generation means that through the pulse generation circuit, the source clock is converted into a narrow pulse signal, and the frequency remains unchanged. That is, the input in Fig. 2 is passed through the pulse generating circuit to obtain the pulse signal shown at node A.

There is a reason for such a conversion, because if the duty cycle of the input clock is distorted, the duty cycle may not always be less than 50%, and may be greater than 50%. For the method in the present invention, if the original clock is directly processed, it is very likely that the high-level overlap of the clock will cause a function error, and the phase overlap is likely to occur when the phase is synthesized, so the original input must be generated by a pulse generating circuit. Source clocks with different duty ratios are uniformly shaped into narrow pulse signals.

Generally speaking, the pulse generation circuit can be realized by sampling the transition edge of the input signal in a very narrow window.

(2), half cycle delay

Half cycle delay refers to delaying the pulse signal obtained in step 1 by half cycle. Accurate half-period delay of the clock is a key part of the method of the present invention, and the adjustment accuracy of the duty ratio can be guaranteed only if the delay is accurate. Step 2 includes two steps: measurement of clock period and adjustment of clock phase, as shown in Figure 3.

①. Clock cycle measurement

The clock cycle measurement refers to the measurement of the cycle of the pulse signal generated in step 1. In Fig. 3, t _std is the period value of the pulse signal measured.

The measurement of the clock cycle is completed by the measurement delay line, and the structure of the measurement delay line is shown in Figure 4. It is composed of 8 groups of delay units, and each group of delay units contains 2 groups of NAND gates and 1 sampling circuit. Each NAND gate group is composed of two NAND gates connected in series to control the transmission of the high-level signal; the sampling circuit samples and outputs the transmission stop position of the high-level signal.

The working principle of the measurement delay line: the pulse signal obtained in step 1 is divided by two and used as the clock CLK of the measurement delay line, as shown in Figure 4. In this way, the duration of a high level is exactly one clock period of the source clock. After the reset circuit is turned off, the high-level signal starts propagating in the measurement delay line through the initial delay line in the half-cycle delay line (HCDL). The input of the initial delay line is always set to a high level, and the reset low-level pulse signal is always generated within half a cycle when the source clock signal is low, so that the propagation and sampling of the high-level signal can be performed alternately. When the reset signal is set low, the clock signal is also low level, the sampling circuit is started, and the output level of the sampling delay unit is started. The position where the propagation of the high-level signal stops, that is, the output terminal of the sampling result, corresponds to the period length of the source clock signal. When the reset signal is set high, the sampler is turned off, and the units in the measurement delay line are reset and cleared to prepare for the next period measurement. After the clock signal is set high again, the high signal continues to propagate forward along the measurement delay line.

②. Clock phase adjustment

Clock phase adjustment refers to the half-period delay of the pulse signal whose period is measured. Clock phase adjustment is accomplished by a variable delay line, as shown in Figure 5, consisting of a series of NAND gates. D1 to D8 are 8 control ports respectively, CLK_IN is connected to the pulse signal in step 1, and CLK_OUT is the output delayed by half cycle, as shown in node B in Figure 2 .

The phase adjustment delays the pulse signal obtained in step 1 by t _std /2 each time the value of t _std is determined. Each output result of the sampling delay unit in the clock period measurement is sent to the control terminals D1-D8 of the variable delay line. Because each delay unit in the measurement delay line contains 2 NAND gate groups, and the variable delay line has only 1 NAND gate group correspondingly. Therefore, after the variable delay line receives the sampling results, each control port is set high or low accordingly, and starts to guide the incoming pulse signal to output along the half-period delayed loop.

(3), mirror delay

Mirror delay refers to delaying the pulse signal delayed by half a cycle in step 2 for another half cycle to obtain a pulse signal with a difference of one cycle from the pulse signal in step 1, as shown by node C in Figure 2. This function is realized by a mirrored delay line (MDL). The logic structure of the mirrored delay line is exactly the same as that of the variable delay line in step 2.

This step is introduced to compensate the skew caused by pulse generation and phase synthesis to the source clock signal, because the pulse generation circuit and phase synthesis circuit have their own delays, so that the output signal phase of the variable delay line is in phase with the source clock There is a delay in the ratio, as long as the output signal of the variable delay line is delayed by the same time, the non-skewed rising edge output after phase synthesis can be realized.

(4), phase synthesis

Phase synthesis refers to the phase superposition of the outputs of step 2 and step 3 to obtain a pulse signal whose frequency is twice that of the source clock.

After steps 1, 2, and 3 are completed, there are two pulse clocks with a phase difference of half a period, that is, node B and node C in FIG. 2 . To get a 50% duty cycle, the phases of these two clocks must be superimposed. The invention uses two-input OR gates to perform phase synthesis on the two pulse signals at nodes B and C. The obtained synthesized signal is shown as node D in FIG. 2 .

(5), two frequency division

Frequency division by two refers to dividing the frequency of the pulse signal synthesized in step 4 by two to obtain an output clock signal with the same frequency as the source clock, the same phase and a duty cycle of 50%, that is, the output in Figure 2.

As described in step 4, the duty cycle of the clock at node D is already 50%, but its frequency is twice that of the original clock, so in order to obtain a clock with the same frequency as the source clock, the present invention needs to double the synthesized pulse signal. crossover.

Claims (2)

1, a kind of clock 50% duty cycle adjustment method based on phase synthesis, it is characterized in that the steps are: (1) Pulse generation: through the pulse generation circuit, the input source clock is converted into a narrow pulse signal, and the frequency remains unchanged; (2), half-period delay: the narrow pulse signal gained in step (1) is delayed by half-period; (3), mirror image delay: the pulse signal that has delayed half cycle in step (2) is delayed half cycle again, obtains the pulse signal that differs one cycle with the pulse signal in step (1); (4), phase synthesis: the pulse signal output in step (2) and step (3) is carried out phase superposition, obtains the pulse signal that frequency is 2 times of source clock; (5), frequency division by two: the pulse signal synthesized in step (4) is divided by two to obtain a clock signal with the same frequency as the source clock, consistent phase and a duty cycle of 50% as an output signal. 2. The clock 50% duty ratio adjustment method based on phase synthesis according to claim 1, characterized in that the specific process of the step (2) is: (1) Clock period measurement: The measurement of the clock period is completed by measuring the delay line. The pulse signal obtained in step (1) is divided by two and used as the clock CLK of the measurement delay line. The duration of such a high level is just One clock cycle of the source clock; after the reset circuit is turned off, the high-level signal starts to propagate in the measurement delay line through the initial delay line in the half-cycle delay line, and the input of the initial delay line is always set to high level and reset to low level The pulse signal is always generated within half a cycle when the source clock signal is low, so that the propagation and sampling of the high-level signal can be performed alternately; when the reset signal is low, the clock signal is also low, and the sampling circuit starts sampling delay The output level of the unit, the position where the high-level signal propagation stops, that is, the output terminal of the sampling result, corresponds to the length of the source clock signal cycle. When the reset signal is set high, the sampler is turned off, and the unit in the measurement delay line is reset and cleared. Zero, ready for the next period measurement. After the clock signal is set high again, the high-level signal continues to propagate forward along the measurement delay line; (2) Clock phase adjustment: a half-period delay is performed on the pulse signal whose period has been measured, and the clock phase adjustment is completed by a variable delay line.

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