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CN101086720A - System and related method capable of controlling multiple data access - Google Patents

System and related method capable of controlling multiple data access Download PDF

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Publication number
CN101086720A
CN101086720A CN 200610091202 CN200610091202A CN101086720A CN 101086720 A CN101086720 A CN 101086720A CN 200610091202 CN200610091202 CN 200610091202 CN 200610091202 A CN200610091202 A CN 200610091202A CN 101086720 A CN101086720 A CN 101086720A
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signal
access
data
clock
address
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CN100573487C (en
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朱胜源
赖敬文
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Novatek Microelectronics Corp
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Novatek Microelectronics Corp
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Abstract

When the data system receives the request commands issued by different hosts, the data system generates corresponding phase control signals and access signals according to the format of each request command, and then generates a time sequence signal which corresponds to each request command and comprises a plurality of enabling time periods according to each phase control signal, wherein only one time sequence signal comprises the enabling time periods at the same time point. Then, the corresponding control signal is output to a storage device in the starting period of each time sequence signal, so that the storage device only needs to respond to a requirement instruction issued by a corresponding host at the same time point, and further, the access of multiple data is effectively controlled.

Description

The system of controlling multiple access data and correlation technique
Technical field
The present invention is relevant to a kind of system and correlation technique of controlling multiple access data, especially refers to a kind ofly control the system and the correlation technique of multiple access data by setting up the clock signal generating means.
Background technology
Along with the evolution of digital Age and user increase sharply to the functional requirement of infosystem, the reading of numerical data, transmitting, store, use, must constantly strengthen with speed of displaying and correctness thereupon, promptly is the accessing operation of relational storage in the system and wherein influence the usefulness of infosystem the most significant.In addition, now at a high speed and in the powerful infosystem, tend to storer built-in in the system is at length divided the work, so that the accessing operation between associative processor and the storer is stable clear and definite.Common on the market infosystem can be divided into (Synchronous) or asynchronous (Asynchronous) data access structure synchronously at present.The synchronizing information system mainly utilizes synchronous clock (Synchronous Clock) signal to come the output/input signal of control store and the control signal of internal system accurately, make the access speed of storer obtain to guarantee, and can save the time of fill order and transmission data with correct performance.On the other hand, the nonsynchronous information system then need not to carry out according to synchronizing clock signals the accessing operation of storer, but when relevant input signal or instruction change, the operation of carrying out data storage or reading.
Variation along with the infosystem function, the design of system is also more and more complicated, no matter be synchronous or nonsynchronous information system, usually need to receive the instruction that a plurality of main frame is assigned, when receiving the requirement instruction of different main frames desire access datas in same time point, infosystem needs suitably to arrange to carry out the different orders that require instruction, makes each main frame all can successfully carry out the access of data.Because the nonsynchronous information system does not use synchronizing clock signals to carry out accessing operation, therefore needing in addition, the design arbitration mechanism decides the different right of priority that require instruction.Though the synchronizing information system can arrange the different execution sequences that require instruction by the synchronizing clock signals with fixed cycle, the transmission clock signal can consume a large amount of power.In addition, Fu Za integrated circuit (IC) chip often can't only be used single synchronizing clock signals now, and the necessary design of adopting a plurality of synchronizing clock signals, when signal transfers to another clock signal zone by a clock signal area, owing to exist the difference of frequency and phase place between the clock signal of different circuit, thereby the requirement instruction that the non-synchronous data transmission is carried out in the different clocks zone occurred crossing over.Therefore, the asynchronous design that does not rely on relevant clock signal will become more and more important, and it can not only promote the infosystem performance and reduce power consumption, and designs fairly large infosystem.
Please refer to Fig. 1, the functional block diagram of Fig. 1 has illustrated U.S. Pat 4339808 " ASYNCHRONOUSEVENT PRIORITIZING CIRCUIT " in the arbitration circuit 10 of a disclosed asynchronous events.Arbitration circuit 10 comprises a latch (Latch) 12, a latch controllers (Latch Control) 14, one priority logic (Priority Logic) circuit 16, and a delay circuit 18.Latch 12 receives the asynchronous requirement instruction REQUEST that two main frames are assigned respectively 1And REQUEST 2, and produce corresponding output signal Q1 and Q2 according to gating signal (Strode Signal) S that latch controllers 14 transmits.Latch controllers 14 is according to clear signal CLEAR 1, CLEAR 2Reach output signal Q1, Q2 and produce gating signal S, and gating signal S is reached latch 12 and delay circuit 18.Delay circuit 18 is exported corresponding delaying strobe signal S ' to priority logic circuit 16 according to gating signal S.Priority logic circuit 16 can be arbitrated the right of priority of output signal Q1 and Q2, and produces corresponding enabling signal (Grant Signal) GRANT according to the delaying strobe signal S ' that delay circuit 18 transmits 1And GRANT 2, the system that makes can be according to enabling signal GRANT 1And GRANT 2Carry out REQUEST 1Or REQUEST 2The arbitration circuit 10 of prior art uses delay circuit 18 to come the multiple access of control data, because of the variation of external temperature or operating voltage, makes the characteristic of delay circuit 18 depart from predetermined value, and then influences the accuracy and the correctness of data access easily.
Please refer to Fig. 2, the functional block diagram of Fig. 2 has illustrated U.S. Pat 6591323 " MEMORYCONTROLLER WITH ARBITRATION AMONG SEVERAL STROBE REQUESTS " in the control circuit 20 of a disclosed asynchronous events.Control circuit 20 comprises one storehouse/quene state machine (Pool/QueueState Machine) SM1, transaction processing state machine (Transaction Processor StateMachine) SM2-SM4, thesaurus state machine (Bank State Machine) SM5-SM8, an order moderator (Command Arbitrator) 22, one order output trigger (Command Output FlipFlop) 24, and dynamic random memory (Dynamic Random Access Memory, DRAM) 26.The control circuit 20 of prior art receives the asynchronous requirement instruction that a plurality of main frame is assigned by storehouse/quene state machine SM1, and the status mechanism that is provided by transaction processing state machine SM2-SM4 and thesaurus state machine SM5-SM8 is judged the different right of priority that require instruction again.Because status mechanism needs a synchronous clock signal as its trigger pip, so the control circuit 20 of prior art only can be applied to the synchrodata system, and can't be applied to the non-synchronous data system.
Summary of the invention
The invention provides a kind of data system of controlling multiple access data, it comprises a memory storage, is used for receiving a control signal and an address signal, and according to the data of being deposited on this pairing address of this address signal of control signal access; One multiple access control device is used for receiving a plurality of requirement instructions of being assigned when a plurality of main frames are desired this memory storage of access, and requires instruction to produce a corresponding phase control signal and an access signal according to each that receives; One clock signal generating means, be used for receiving this phase control signal that this multiple access control device is produced, and produce respectively corresponding to each according to a phase reference signal and each phase control signal and to require instruction and to comprise a plurality of clock signals of enabling the period, only there is a clock signal to comprise in these a plurality of clock signals during wherein same time point and enables the period; One access control device, be used for receiving this clock signal that this access signal that this multiple access control device produced and this clock signal generating means are produced, and control signal to this memory storage at corresponding this of period output of enabling of each clock signal; And an address control device, be used for receiving this clock signal that this access signal that this multiple access control device produced and this clock signal generating means are produced, and produce address signal corresponding to each access signal.
The present invention provides a kind of method of controlling multiple access data in addition, it comprises (a) and receives a plurality of requirement instructions, (b) produce a phase control signal and an access signal that requires instruction corresponding to each, (c) produce respectively corresponding to each according to each phase control signal and require instruction and comprise a plurality of a plurality of clock signals of enabling the period, only having a clock signal to comprise in these a plurality of clock signals during wherein same time point enables the period, (d) according to this access signal, the period of enabling at each clock signal is exported a corresponding control signal, (e) produce a address signal corresponding to each access signal, and (f) according to the data of this control signal and this address signal access one memory storage internal memory.
Description of drawings
Fig. 1 is the functional block diagram of an asynchronous events arbitration circuit in the prior art.
Fig. 2 is the functional block diagram of an asynchronous events control circuit in the prior art.
Fig. 3 is the functional block diagram of the data system of a controlling multiple access data among the present invention.
Fig. 4 is the signal graph of data system when carrying out multiple access data in the first embodiment of the invention.
Fig. 5 is the signal graph of data system when carrying out multiple access data in the second embodiment of the invention.
Fig. 6 is the signal graph of data system when carrying out multiple access data in the third embodiment of the invention.
Fig. 7 is the signal graph of data system when carrying out multiple access data in the fourth embodiment of the invention.
Fig. 8 is the process flow diagram of data system of the present invention when carrying out multiple access data.
The main element symbol description
10 arbitration circuits, 12 latchs
14 latch controllers, 16 priority logic circuit
18 delay circuits, 20 control circuits
22 order moderators, 24 order output triggers
26 DRAM, 30 data systems
32 multiple access control device, 34 clock signal generating meanss
36 access control devices, 38 address control devices
40 self-excited oscillators, 42 pulse producers
44 data buffers, 46 memory storages
S gating signal S ' delaying strobe signal
T1-T3 time point E1, E2 enable the period
TRIGGER trigger pip REF phase reference signal
810-860 step SM1 storehouse/quene state machine
SM2-SM4 transaction processing state machine
SM5-SM8 thesaurus state machine
CLEAR 1, CLEAR 2Clear signal
GRANT 1, GRANT 2Enabling signal
Q1, Q2 output signal
REQUEST 1-REQUEST NRequire instruction
ACCESS 1-ACCESS NAccess signal
CONTROL 1-CONTROL NControl signal
ADDRESS 1-ADDRESS NAddress signal
PHASE 1-PHASE NPhase control signal
CLOCK 1-CLOCK NClock signal
Embodiment
Please refer to Fig. 3, Fig. 3 is the functional block diagram of the data system 30 of a controlling multiple access data among the present invention.Data system 30 comprises a multiple access control device 32, a clock signal generating means 34, an access control device 36, an address control device 38, a data buffer 44, and a memory storage 46.Data system 30 can receive the order that a plurality of external system is assigned, and in Fig. 3, external system represented by main frame 1-main frame N, and the requirement order that main frame 1-main frame N is assigned when desiring accessing storage devices 46 internal storage datas is respectively by REQUEST 1-REQUEST N Represent.Data system 30 receives the requirement order REQUEST that main frame 1-main frame N is assigned by multiple access control device 32 1-REQUEST N, multiple access control device 32 is again according to requiring order REQUEST 1-REQUEST NProduce corresponding phase control signal PHASE respectively 1-PHASE NWith access signal ACCESS 1-ACCESS N, and a trigger pip TRIGGER.
Clock signal generating means 34 is coupled to multiple access control device 32, comprises a self-excited oscillator (Self-Excited Oscillator) 40 and one pulse producer (Pulse Generator) 42.After receiving trigger pip TRIGGER, self-excited oscillator 40 can produce a phase reference signal REF, and pulse producer 42 is again according to reference signal REF and phase control signal PHASE 1-PHASE NProduce respectively corresponding to requiring order REQUEST 1-REQUEST NClock signal CLOCK 1-CLOCK NClock signal CLOCK 1-CLOCK NIn each clock signal comprise a plurality of enabling the period, and only have a clock signal to comprise at one time to enable the period clock signal CLOCK 1-CLOCK NRelation can describe in detail after this.
Access control device 36 is coupled to multiple access control device 32 and clock signal generating means 34, can receive corresponding to requiring order REQUEST 1-REQUEST NAccess signal ACCESS 1-ACCESS NWith clock signal CLOCK 1-CLOCK N, and respectively at clock signal CLOCK 1-CLOCK NThe period of enabling export corresponding control signal CONTRL 1-CONTROL NTo memory storage 46.Address control device 38 also is coupled to multiple access control device 32 and clock signal generating means 34, can receive corresponding to requiring order REQUEST 1-REQUEST NAccess signal ACCESS 1-ACCESS NWith clock signal CLOCK 1-CLOCK N, and output corresponds respectively to control signal CONTRL 1-CONTROL NAddress signal ADDRESS 1-ADDRESS NTo memory storage 46, address signal ADDRESS 1-ADDRESS NRepresentative requires order REQUEST respectively 1-REQUEST NRelative address when memory storage 46 is carried out data access.
Memory storage 46 can be the storer of any kind of, and (Dynamic Random Access Memory DRAM) does explanation for example with the dynamic random memory in the present embodiment.After receiving a control signal and corresponding address signal thereof, the data of storing on the corresponding address of memory storage 46 meeting access address signals.For instance, suppose that memory storage 46 receives control signal CONTRL in a time point 1And corresponding address signal ADDRESS 1, as control signal CONTRL 1During requirement order that representative data reads, memory storage 46 can be with address signal ADDRESS 1The data of storing on the corresponding address reach main frame 1 by data buffer 44; As control signal CONTRL 1During requirement order that representative data writes, data can by data buffer 44 can write storage devices 46 in address signal ADDRESS 1Corresponding address.
Because the requirement order that meets agreement assigned of main frame, data system 30 could correctly be discerned carrying out associative operation, so the present invention requirement order REQUEST that can be assigned according to main frame 1-main frame N 1-REQUEST NForm, produce corresponding phase control signal PHASE 1-PHASE N, phase control signal PHASE 1-PHASE NComprised respectively and required order REQUEST 1-REQUEST NThe information of middle parameters.So, the pulse producer 42 of clock signal generating means 34 can be respectively according to phase control signal PHASE 1-PHASE NAdjust the phase reference signal REF that self-excited oscillator 40 is produced, to produce respectively corresponding to requiring order REQUEST 1-REQUEST NClock signal CLOCK 1-CLOCK N
Please refer to Fig. 4, Fig. 4 has illustrated the signal graph of data system 30 when carrying out multiple access data in the first embodiment of the invention.In first embodiment of the invention, suppose that when time point T1 data system 30 receives the requirement order REQUEST that main frame 1 and main frame 2 are assigned simultaneously 1With REQUEST 2, phase reference signal REF, trigger pip TRIGGER, clock signal CLOCK that this moment, data system 30 was produced 1And CLOCK 2, and the requirement order REQUEST that receives 1And REQUEST 2Respectively by the waveform REF among Fig. 4, waveform TRIGGER, waveform CLOCK 1, waveform CLOCK 2, waveform REQUEST 1With waveform REQUEST 2Represent.Trigger pip TRIGGER starts self-excited oscillator 40 when time point T1, and then produces phase reference signal REF.Require order REQUEST according to being relevant to 1And REQUEST 2Phase control signal PHASE 1, PHASE 2And phase reference signal REF, the clock signal CLOCK that pulse producer 42 is produced 1With clock signal CLOCK 2Respectively comprise a plurality of enabling the period.Clock signal enable the period of period for tool noble potential in its waveform, clock signal CLOCK 1With clock signal CLOCK 2The period of enabling represent by E1 among Fig. 4 and E2 respectively.The length of enabling period E1 and E2 is relevant to and requires order REQUEST 1And REQUEST 2Form, and only have a clock signal to comprise when putting at one time to enable the period.So, when access control device 36 respectively at clock signal CLOCK 1And CLOCK 2Enable period output control signal CONTROL 1And CONTROL 2During to memory storage 46, memory storage 46 only can respond the wherein requirement of a main frame in main frame 1 and the main frame 2 at one time, so the present invention can control multiple access data by comprising a plurality of clock signals of enabling the period.
Please refer to Fig. 5, Fig. 5 has illustrated the signal graph of data system 30 when carrying out multiple access data in the second embodiment of the invention.In second embodiment of the invention, suppose that equally when time point T1 data system 30 receives the requirement order REQUEST that main frame 1 and main frame 2 are assigned simultaneously 1And REQUEST 2, phase reference signal REF, trigger pip TRIGGER, clock signal CLOCK that this moment, data system 30 was produced 1And CLOCK 2, and the requirement order REQUEST that receives 1And REQUEST 2Also respectively by the waveform REF among Fig. 5, waveform TRIGGER, waveform CLOCK 1, waveform CLOCK 2, waveform REQUEST 1With waveform REQUEST 2Represent.In second embodiment of the invention, suppose that data system 30 has been finished the requirement order REQUEST that main frame 1 is assigned when time point T2 1, and do not receive the requirement order that other main frame is assigned, this moment clock signal CLOCK 2After time point T2, be all and enable the period, finish the requirement order REQUEST that main frame 2 is assigned during at time point T3 up to data system 30 2Till.
Please refer to Fig. 6 and Fig. 7, Fig. 6 and Fig. 7 have illustrated the signal graph of data system 30 when carrying out multiple access data among the present invention third and fourth embodiment respectively.In the present invention third and fourth embodiment, tentation data system 30 is carrying out the requirement order REQUEST that main frame 1 is assigned 1Process in, receive the requirement order REQUEST that main frame 2 is assigned at time point T2 2, phase reference signal REF, trigger pip TRIGGER, clock signal CLOCK that this moment, data system 30 was produced 1With clock signal CLOCK 2, and the requirement order REQUEST that receives 1And REQUEST 2Also respectively by the waveform REF among Fig. 6, waveform TRIGGER, waveform CLOCK 1, waveform CLOCK 2, waveform REQUEST 1With waveform REQUEST 2Represent.In third embodiment of the invention, time point T2 does not correspond to the integral multiple in phase reference signal REF cycle, that is data system 30 can't stop to carry out the requirement order REQUEST that main frame 1 is assigned immediately when time point T2 1, therefore work as data system 30 and receive the requirement order REQUEST that main frame 2 is assigned in time point T2 2The time, data system 30 can continue to carry out requirement order REQUEST 1Extremely the next one corresponds to the time point T3 of the cycle integral multiple of phase reference signal REF, and then enables period E1 and E2 clock signal CLOCK by comprising 1With clock signal CLOCK 2Control the access of multiple data.In like manner, in fourth embodiment of the invention, time point T2 corresponds to the integral multiple in phase reference signal REF cycle, that is data system 30 can stop to carry out the requirement order REQUEST that main frame 1 is assigned immediately when time point T2 1, therefore work as data system 30 and receive the requirement order REQUEST that main frame 2 is assigned in time point T2 2The time, data system 30 can be enabled period E1 and E2 clock signal CLOCK by comprising immediately 1With clock signal CLOCK 2Control the access of multiple data.
Please refer to Fig. 8, Fig. 8 is the process flow diagram of data system 30 of the present invention when carrying out multiple access data.The process flow diagram of Fig. 8 comprises the following step:
Step 810: receive and require instruction REQUEST 1-REQUEST N
Step 820: produce respectively corresponding to requiring to instruct REQUEST 1-REQUEST NPhase control signal PHASE 1-PHASE NAnd access signal ACCESS 1-ACCESS N
Step 830: respectively according to phase control signal PHASE 1-PHASE NGeneration comprises a plurality of clock signal CLOCK that enable the period 1-CLOCK N
Step 840: respectively at clock signal CLOCK 1-CLOCK NEnable period output control signal CONTROL 1-CONTROL M
Step 850: respectively according to access signal ACCESS 1-ACCESS NGeneration is corresponding to requiring to instruct REQUEST 1-REQUEST NAddress signal ADDRESS 1-ADDRESS NAnd
Step 860: according to control signal CONTROL 1-CONTROL NWith corresponding address signal ADDRESS 1One ADDRESS NThe data of access one memory storage internal memory.
In data system of the present invention, when not receiving any requirement order, the self-excited oscillator 40 of clock signal generating means 34 can't be activated, therefore can consumed power.When receiving the requirement order that different main frame assigns, multiple access control device 32 can start self-excited oscillator 40, and the form of ordering according to each requirement produces corresponding phase control signal, make the pulse producer 42 of clock signal generating means 34 to adjust the phase reference signal that self-excited oscillator 40 is produced, and then generation require order and comprise a plurality of clock signals of enabling the period corresponding to each according to each phase control signal.In the clock signal that pulse producer 42 is produced, only having a clock signal to comprise when same time point enables the period, therefore the present invention can export the corresponding memory storage 46 that controls signal in the period of enabling of each clock signal by access control device 36, make memory storage 46 only need respond the requirement instruction that a corresponding main frame is assigned at one time, so can effectively control the access of multiple data.
The above only is the preferred embodiments of the present invention, and all equivalences of carrying out according to claim of the present invention change and revise, and all should belong to covering scope of the present invention.

Claims (8)

1.一种可控制多重数据存取的数据系统，其包含；1. A data system capable of controlling multiple data access, comprising; 一存储装置，用来接收一控制信号和一地址信号，并依据该控制信号存取该地址信号所对应的地址上所存的数据；A storage device, used to receive a control signal and an address signal, and access the data stored on the address corresponding to the address signal according to the control signal; 一多重存取控制装置，用来接收多个主机欲存取该存储装置时所下达的多个要求指令，并依据接收到的每一要求指令产生相对应的一相位控制信号及一存取信号；A multiple access control device is used to receive multiple request commands issued by multiple hosts when they want to access the storage device, and generate a corresponding phase control signal and an access command according to each received request command Signal; 一时序信号发生装置，用来接收该多重存取控制装置所产生的该相位控制信号，并依据一相位参考信号及每一相位控制信号分别产生对应于每一要求指令且包含多个启用时段的一时序信号，其中同一时间点时该多个时序信号中仅有一时序信号包含启用时段；A timing signal generating device is used to receive the phase control signal generated by the multiple access control device, and generate a signal corresponding to each request command and including a plurality of enabling periods according to a phase reference signal and each phase control signal A timing signal, wherein at the same time point, only one timing signal among the plurality of timing signals includes an enabling period; 一存取控制装置，用来接收该多重存取控制装置所产生的该存取信号与该时序信号发生装置所产生的该时序信号，并在每一时序信号的启用时段输出相对应的该控制信号至该存储装置；以及An access control device, used to receive the access signal generated by the multiple access control device and the timing signal generated by the timing signal generating device, and output the corresponding control during the activation period of each timing signal signal to the memory device; and 一地址控制装置，用来接收该多重存取控制装置所产生的该存取信号与该时序信号发生装置所产生的该时序信号，并产生对应于每一存取信号的地址信号。An address control device is used to receive the access signal generated by the multiple access control device and the timing signal generated by the timing signal generating device, and generate an address signal corresponding to each access signal. 2.如权利要求1所述的数据系统，其还包含：2. The data system of claim 1, further comprising: 一数据缓中装置，用来存储该多重存取控制装置输出的存取信号、欲写入该存储装置的数据以及该存储装置所输出的数据。A data cache device is used to store the access signal output by the multiple access control device, the data to be written into the storage device and the data output by the storage device. 3.如权利要求1所述的数据系统，其该时序信号发生装置系包含：3. The data system as claimed in claim 1, wherein the timing signal generating device comprises: 一自激振荡装置，用来于接收到该多重存取控制装置产生的一触发信号时产生该相位参考信号；以及a self-oscillating device for generating the phase reference signal upon receiving a trigger signal generated by the multiple access control device; and 一脉冲发生装置，用来产生该多个时序信号。A pulse generating device is used to generate the multiple timing signals. 4.如权利要求1所述的数据系统，其该存储装置为一动态随机存储存储器。4. The data system of claim 1, wherein the storage device is a dynamic random access memory. 5.一种控制多重数据存取的方法，其包含下列步骤：5. A method for controlling multiple data access, comprising the following steps: (a)接收多个要求指令；(a) receiving multiple request instructions; (b)产生对应于每一要求指令的一相位控制信号及一存取信号；(b) generating a phase control signal and an access signal corresponding to each request command; (c)依据每一相位控制信号分别产生对应于每一要求指令且包含多个启用时段的多个时序信号，其中同一时间点时该多个时序信号中仅有一时序信号包含启用时段；(c) generating a plurality of timing signals corresponding to each required instruction and including a plurality of enabling periods according to each phase control signal, wherein at the same time point, only one timing signal of the plurality of timing signals includes enabling periods; (d)依据该存取信号，在每一时序信号的启用时段输出相对应的一控制信号；(d) outputting a corresponding control signal during the activation period of each timing signal according to the access signal; (e)产生对应于每一存取信号的一地址信号；及(e) generating an address signal corresponding to each access signal; and (f)依据该控制信号和该地址信号存取一存储装置内存的数据。(f) accessing data in a memory device according to the control signal and the address signal. 6.如权利要求5所述的方法，其中步骤(c)系依据一相位参考信号及每一相位控制信号分别产生对应于每一要求指令且包含多个启用时段的多个时序信号。6. The method as claimed in claim 5, wherein step (c) is to generate a plurality of timing signals corresponding to each request command and including a plurality of enabling periods according to a phase reference signal and each phase control signal. 7.如权利要求6所述的方法，其还包含产生该相位参考信号。7. The method of claim 6, further comprising generating the phase reference signal. 8.如权利要求7所述的方法，其还包含在接收到该要求指令时产生一触发信号，并在接收到该触发信号时产生该相位参考信号。8. The method of claim 7, further comprising generating a trigger signal when receiving the request command, and generating the phase reference signal when receiving the trigger signal.
CN 200610091202 2006-06-07 2006-06-07 System and related method for controlling multiple data access Expired - Fee Related CN100573487C (en)

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US6343324B1 (en) * 1999-09-13 2002-01-29 International Business Machines Corporation Method and system for controlling access share storage devices in a network environment by configuring host-to-volume mapping data structures in the controller memory for granting and denying access to the devices
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