CN101079318A - Static random access memory cells and arrays - Google Patents

Abstract

The invention provides a static random access memory unit and an array, wherein the static random access memory unit comprises a first load element, a first pull-down transistor and a switch box coupled between the first load element and the first pull-down transistor. The switch box is used for receiving a switch control signal, cutting off a first connection between the first load element and the first pull-down transistor during a read operation of the static random access memory unit, and conducting the first connection during a write operation. The SRAM cells and arrays of the present invention avoid static noise and tolerate higher noise and higher device mismatch. Due to the improved noise tolerance, the SRAM cell can be used in very small-sized technologies, and the operating voltage can also be reduced.

Description

Static random access memory cells and arrays

technical field

The present invention relates to a semiconductor device, in particular to a memory unit, and more particularly to a design and manufacturing method of a static random access memory (static random access memory, SRAM) unit.

Background technique

SRAM is commonly used on integrated circuits. SRAM cells have the advantage of retaining data without needing to be refreshed. FIG. 1 shows a circuit diagram of a conventional SRAM cell using six transistors, including pass-gate transistors PG0 and PG1 , pull-up transistors PU0 and PU1 , and pull-down transistors PD0 and PD1 . The gates of the pass-gate transistors PG0 and PG1 are controlled by a wordline (wordline) WL to determine whether to select the current SRAM cell. A latch consisting of pull-up transistors PU0, PU1 and pull-down transistors PD0, PD1 is used to store the state. The storage state can be read out via the bitline BL and the bitline BLB, wherein the storage state read from the bitline BLB is in opposite phase.

Before the start of the read operation, since the voltage of the word line WL is a low voltage (eg, 0V), the pass gate transistors PG0 and PG1 are not turned on. In order to read stored data, the bit lines BL and BLB are precharged to the power supply VDD. Assuming that the data stored in advance is "1", it indicates that the node C is at a high potential and the node CB is at a low potential. When the word line WL is activated, the transfer gate transistors PG0 and PG1 are turned on. The data "0" stored at the node CB will cause the voltage of the bit line BLB to be discharged to "0" from the power supply VDD via the pass gate transistor PG1. In other words, a high potential at node C will maintain the bit line BL at "1". Next, the difference signal between the bit lines BL and BLB is detected and read out from the output buffer.

Due to the shrinking size of integrated circuits, the read and write margins of SRAM cells will be reduced. Due to static noise, the read and write ranges are reduced, which may cause errors in read and write operations, respectively. The sensed disturb at node CB may be too high to cause the state of the SRAM cell to flip over, so that the content of the SRAM cell is inverted. Figure 2 shows the simulated voltages of nodes C and CB during a read operation, where no transition occurs. It should be noted that during the read operation, the voltages of the nodes C and CB have glitches. Then, the voltages of the nodes C and CB return to the original stored values. FIG. 3 shows the simulated voltages of nodes C and CB during an erroneous read operation. It should be noted that during the read operation, the voltages of nodes C and CB are switched. Figure 3 shows the result of conventional readout ranges below static noise. Other factors causing this error may include, for example, reducing the voltage of the power supply VDD, and a high threshold voltage mismatch between the pull-up transistor and the pull-down transistor.

Therefore, it is necessary to provide a new SRAM cell which can avoid errors caused by static noise.

Contents of the invention

The present invention is made to solve the above-mentioned problems in the prior art. According to an embodiment of the present invention, a static random access memory unit is provided, including: a first load element, a first pull-down transistor, and a switch coupled between the first load element and the first pull-down transistor box. The switch box is used to receive the switch control signal, to cut off the first connection between the first load element and the first pull-down transistor during the read operation of the static random access memory unit, and to turn on the first connection between the first load element and the first pull-down transistor during the write operation. Through the first connection.

According to the SRAM unit, wherein the switch box is coupled to a switch control circuit for providing a switch control signal to the switch box, wherein during the read operation of the SRAM unit, The switch control signal cuts off a first connection between the first load element and the first pull-down transistor, and turns on the first connection during a write operation of the SRAM unit.

According to the SRAM unit, further comprising: a second load element; and a second pull-down transistor forming a lock with the first load element, the first pull-down transistor, and the second load element memory, wherein the switch box is further coupled between the second load element and the second pull-down transistor.

According to the SRAM unit, the first load element is a resistor.

According to the SRAM unit, wherein the first load element is a P-type metal-oxide-semiconductor transistor.

According to the SRAM unit, the switch box includes one of a metal oxide semiconductor transistor and a bipolar transistor.

According to the SRAM cell, further comprising a transfer gate element coupled to at least one of the first load element and the first pull-down transistor, wherein the transfer gate element is substantially selected from a metal oxide A group consisting of a material semiconductor transistor and a bipolar transistor.

According to the SRAM cell, wherein the first pull-down transistor includes a bipolar transistor.

According to another embodiment of the present invention, an array of static random access memory cells is provided, which is arranged in multiple rows and multiple columns, wherein each static random access memory cell includes a load element, a pull-down transistor, and is coupled to The switch box between the load element and the pull-down transistor. The switch box is used to receive a switch control signal, cut off the connection between the load element and the pull-down transistor during the read operation of the SRAM unit, and switch off the connection between the load element and the pull-down transistor during the write operation of the SRAM unit. Through the above connection. The SRAM array further includes: a plurality of word lines coupled to the SRAM cells located in the row of the array, and one of the word lines is coupled to the SRAM cells located in the same row. a memory unit; a plurality of bit lines coupled to the SRAM unit located in the column of the array, and one of the bit lines coupled to the SRAM unit located in the same column; and a plurality of The switch control line is coupled to the switch box of the SRAM unit.

According to the SRAM array, at least some of the switch control lines are coupled to the SRAM cells in the row of the array, and one of the switch control lines is coupled to the SRAM cells in the same row. The above-mentioned switch box of the above-mentioned static random access memory unit.

According to the SRAM array, at least some of the switch control lines are coupled to the SRAM cells in the row of the array, and one of the switch control lines is coupled to the SRAM cells in the same column. The above-mentioned switch box of the above-mentioned static random access memory unit.

According to the SRAM array, wherein the switch control lines include: a first group of switch control lines coupled to the SRAM cells located in the row of the array, and the switch control lines one coupled to the SRAM cells in the same row; and a second group of switch control lines coupled to the SRAM cells in the row of the array, and the switch control lines One of them is coupled to the above-mentioned SRAM unit located in the same column.

According to the SRAM array, it further includes a switch control circuit coupled to the switch control line, wherein the SRAM cells further include four, five, six, eight, ten, twelve or ten Four transistors and content addressable memory, or a combination thereof.

According to the SRAM array, wherein the switch control circuit does not turn on the switch box corresponding to one of the SRAM cells during the read operation of the SRAM cells, and During the write operation of the SRAM unit, the switch box corresponding to one of the SRAM units is turned on.

According to the SRAM array, wherein the switch control circuit does not turn on and perform the above-mentioned SRAM for reading or writing when the above-mentioned SRAM unit is performing a read or write operation The memory cell is coupled to the switch boxes of the other SRAM cells of the same word line.

The static random access memory unit and the array of the present invention can avoid static noise, and can tolerate higher noise and higher device mismatch. Due to the improved noise tolerance, SRAM cells can be used in very small size technologies, and the operating voltage can also be reduced.

Description of drawings

FIG. 1 shows a circuit diagram of a conventional six-transistor SRAM cell.

Figure 2 shows the simulated voltages at the nodes of a conventional SRAM cell during a typical read operation.

FIG. 3 shows simulated voltages at nodes of a conventional SRAM cell during an erroneous read operation.

Figure 4 shows a schematic diagram of a preferred embodiment.

Figure 5 shows a preferred embodiment where the switch box is composed of NMOS transistors.

FIG. 6 shows a schematic timing diagram of the voltages of the word line WL and the switch control line SC.

Figure 7 shows simulated voltages at nodes of a preferred SRAM cell embodiment.

Figure 8 shows an array of preferred SRAM cells.

9 to 16 show schematic circuit diagrams of other embodiments of the present invention.

Wherein, the reference signs are explained as follows:

22 switch box

30 switch control circuit

40, 42 connection line

BL, BLB, BL1, BL1B, B2L, BL2B bit lines

C, CB, Cd, CdB, Cu, CuB nodes

PD0, PD1, PG0, PG1, PG01, PG02, PG11, PG12, PU0, PU1 transistors

SC switch control line

SW0, SW1 switch

VDD, VSS power supply

WL, WL1, WL2 word lines

Detailed ways

In order to make the above-mentioned and other purposes, features, and advantages of the present invention more clearly understood, the preferred embodiments are specifically listed below, and in conjunction with the accompanying drawings, the detailed description is as follows:

Example:

The making and using of the preferred embodiments of the invention are described in detail below. It can be appreciated, however, that the present invention provides many practicable inventive concepts that can be embodied in a wide variety of specific contexts. The description of the specific embodiments of the present invention is only to illustrate the specific method of making and using the present invention, but it is not intended to limit the scope of the present invention.

The present invention provides a memory cell that avoids static noise. FIG. 4 shows a schematic circuit diagram of a preferred embodiment of the present invention, which includes an SRAM cell 20 . The SRAM unit 20 further includes two load elements including a pull-up transistor PU0 and a pull-up transistor PU1 , and four transistors including a pull-down transistor PD0 , a pull-down transistor PD1 , a pass-gate transistor PG0 and a pass-gate transistor PG1 . In a preferred embodiment, the pull-up transistor PU0 and the pull-up transistor PU1 are used as load elements. In another embodiment, resistors are used to replace the pull-up transistors PU0 and PU1.

A switch box 22 is located between the load element and the pull-down transistor and controls the electrical path between the load element and the pull-down transistor. The switch control circuit 30 is also electrically connected to the switch control line SC to control the switch box 22 . If the switch box 22 is turned on, the switch (marked by a rectangle) in the switch box 22 is turned on, and then the load element and the pull-down transistor are electrically connected. However, if the switch box 22 is not turned on, the switches in the switch box 22 are not turned on, and then the load element is electrically separated from the pull-down transistor.

FIG. 5 shows an exemplary embodiment of the circuit diagram shown in FIG. 4 . The read operation of the preferred embodiment as well as the write operation will be described using an exemplary embodiment. In this embodiment, the switch box 22 includes two NMOS transistors SW0 and SW1 used as switches, wherein the switch SW0 is used for electrically connecting or electrically separating the pull-up transistor PU0 and the pull-down transistor PD0, and the switch SW1 is used for The pull-up transistor PU1 and the pull-down transistor PD1 are electrically connected or electrically separated.

During the read operation of the SRAM cell, the word line WL is active, so the pass gate transistors PG0, PG1 are turned on. The switch control signal on the switch control line SC does not turn on the switch SW0 and the switch SW1. FIG. 6 shows a schematic timing diagram of the voltages of the word line WL and the switch control line SC. Preferably, transitions of the switch control signal substantially follow transitions of the signal on word line WL, although changes in the switch control signal may slightly lead or lag changes in word line WL. Preferably, switch SW0 and switch SW1 are not turned on only for a short period of time, and are turned on as soon as the read operation is completed.

Referring to FIG. 5 , assuming that before the read operation, the SRAM cell 20 stores “1”, then the nodes Cu and Cd are high potentials, and the nodes CuB and CdB are low potentials. During the read operation, the data "0" stored at the node CdB discharges the bit line BLB to "0" via the transfer gate transistor PG1, so the voltage of the node CdB is determined by the power supply VSS and the precharge voltage of the bit line BLB , which is the same as the equivalent resistance of the pass-gate transistor PG1 and the pull-down transistor PD1. Therefore, as shown in Figure 7, the voltage at node CdB will have glitches. However, a glitch will not cause a transition of all SRAM cells. Meanwhile, although small glitches may occur, generally the voltages of nodes Cd, Cu, and CuB are maintained close to those before the read operation according to the time sequence of the voltages on the switch control line SC with respect to the voltage of the word line WL. respective status. Nodes Cd and Cu maintain bit line BL at "1" during all read operations.

During the read operation, the node CuB is electrically separated from the node CuB, thus substantially maintaining the undisturbed state "0". Therefore, SRAM cell 20 can tolerate high static noise and component mismatch.

During the write operation of the SRAM cell, the word line WL is active, so the pass gate transistors PG0, PG1 are turned on. The switch SW0 and the switch SW1 are also turned on by the switch control signal on the switch control line SC. Therefore, the SRAM unit 20 will behave as if the switch box 22 were not present. The nodes CuB and CdB will be charged to the power supply VDD by the pre-charged bit line BLB passing through the pass gate transistor PG1. In other words, the node Cu and the node Cd will be discharged to the power supply VSS through the pass gate transistor PG0 through the bit line BL. Therefore, new data is written to the SRAM unit 20 .

The previously described SRAM cell embodiments may be used to form memory arrays. Figure 8 shows a SRAM array comprising preferred SRAM cells. For simplicity, only 3×3 arrays are used, where rows are numbered n-1, n, and n+1, and columns are numbered m-1, m, and m+1 . Each square symbol represents a SRAM cell, and is electrically connected to a word line WL, a bit line BL, and a switch control line SC, wherein each line is numbered separately. The switch control line SC is electrically connected to the switch control circuit 30 . As shown in FIG. 8, in a preferred embodiment, SRAM cells electrically connected to the same word line are controlled by the same switch control line, eg, SCn-1, SCn, and SCn+1. In another embodiment, SRAM cells electrically connected to the same bit line are controlled by the same switch control line. In yet another embodiment, each SRAM cell can be controlled by the switch control circuit 30 respectively. For example, yet another implementation can be achieved by electrically connecting a first set of switch control lines to columns of an SRAM array, and a second set of switch control lines to rows of an SRAM array. example.

During standby mode, in which no read or write operations are performed, the switch boxes of the SRAM cell (see FIG. 5 ) are also fully turned on, thereby maintaining stored data.

During a read operation, the switch case of the SRAM cell being read is preferably non-conductive. The preferred states of the switch boxes in the remaining SRAM units are described in Table 1 and Table 2, and the description of the 3×3 array only corresponds to the SRAM unit in FIG. 8 . However, it can be understood that the following table is just an example of setting the switch boxes in the SRAM array, and thus is not intended to limit the scope of the present invention. Assuming that only the SRAM cell with the row number n and the column number m (represented by cell (n)(m)) is being read, then the optimal state of the switch box is shown in Table 1.

Table 1 Switch Box Status During Read Operation bit line m-1 bit line m bit line m+1 word line n-1 close close close word line n close close close word line n+1 close close close

In the embodiment shown in Table 1, during the read operation of cell (n)(m), even if only one SRAM cell is being read, all switch boxes in the SRAM array are not will be turned on. After the read operation is completed, all switch boxes are turned on.

Table 2 Switch Box Status During Read Operation bit line m-1 bit line m bit line m+1 word line n-1 open open open word line n close close close word line n+1 open open open

Table 2 shows another preferred setting. Table 2 indicates that during the read operation of cell (n)(m), switch boxes electrically connected to the same word line WLn (same row n as in Table 2) will not be turned on, while other switches in the same memory array box will be turned on. After the read operation is completed, all switch boxes in the SRAM array are turned on.

During a write operation, the switch case of the SRAM cell being written is preferably non-conductive. In the same array, the preferred states of the switch boxes in the remaining SRAM cells are described in Table 3 and Table 4, wherein the description of the 3×3 array only corresponds to the SRAM cells in FIG. 8 . Assuming only cells (n)(m) are being written, then the preferred switch case state is:

Table 3 Switch Case Status During Write Operation bit line m-1 bit line m bit line m+1 word line n-1 open open open word line n close open close word line n+1 open open open

In the embodiment shown in Table 3, during the writing operation of cell (n)(m), except for cell (n)(m), the switches electrically connected to the same word line (such as the same row n in Table 3) box will not be turned on, while the remaining switch boxes in the same memory array will be turned on. After the write operation is completed, all the switch boxes in the SRAM array are turned on.

Table 4 Switch Case Status During Write Operation bit line m-1 bit line m bit line m+1 word line n-1 close open close word line n close open close word line n+1 close open close

Table 4 shows another preferred embodiment of the state of the switch box. In the embodiment shown in Table 4, during the write operation, except for the SRAM cell electrically connected to the same bit line as the cell (n) (m), the other switch boxes in the memory array are not will be turned on. After the write operation is completed, all the switch boxes in the SRAM array are turned on.

During the previously described read operation and write operation, when the SRAM cell is being read/written, the switch boxes electrically connected to the same word line are preferably also not turned on. The reason is that during read/write, when the cell is operating, the SRAM cells on the same word line are false read, because the word line of these cells (the same word line when the cell is operating) Be moved. Therefore, these switch boxes are preferably non-conducting to avoid unwanted state transitions due to spurious readouts.

By implementing the methods provided by the present invention, those skilled in the art will understand that various other embodiments can be implemented to achieve high static noise tolerance. FIG. 9 shows another embodiment of the present invention, which is similar to the embodiment of FIG. 5 except that the connection lines 40, 42 are located on the same side of the switch box 22 as the pass-gate transistors PG0, PG1. In FIG. 5 , the corresponding connection lines 40 , 42 are located on different sides of the switch box 22 from the pass-gate transistors PG0 , PG1 . In FIG. 10 , the pass-gate transistors PG0 , PG1 are located on the same side of the switch box 22 as the load elements PU0 , PU1 , while the connection lines 40 , 42 are located on the other side of the switch box 22 . In FIG. 11 , the connection lines 40 , 42 are located on the same side of the switch box 22 as the pass-gate transistors PG0 , PG1 and the load elements PU0 , PU1 .

Figures 12-15 show an embodiment of an SRAM cell using eight transistors, where the switch box 22 operates similarly to the switch box in the six transistor embodiment. In an embodiment, dynamic power may be provided to dual bitlines BL1, BL2 (same as bitlines BL1B, BL2B) to increase read and/or write range. Dual word lines WL1, WL2 are provided to select the desired bit line voltage. Likewise, by moving the pass-gate transistor and/or the connection line 40, 42 to one side of the load element or pull-down transistor, different embodiments as shown in FIGS. 12-15 can be implemented. For those skilled in the art, commonly used static random access memory cells also include four, five, six, eight, ten, twelve or fourteen transistors and content addressable memory (Content Addressable Memory, CAM), or a combination thereof, Those skilled in the art will understand the respective electrical connections of the switch box 22 .

The switch box 22 can also be composed of bipolar transistors. In addition, other MOS elements (separate or combined) of the previously described embodiments may also be replaced by bipolar transistors. Alternative transistors include (without limitation): transistors within switch box 22 ; pass-gate transistors PG0 , PG1 , and pull-down transistors PD0 , PD1 . FIG. 16 shows an exemplary embodiment in which the switches SW0 and SW1 are composed of bipolar transistors. Additionally, in the previously described embodiments, the switch transistors SW0, SW1 and the pass gate transistors PG0, PG1 are NMOS transistors, but those skilled in the art will appreciate that PMOS transistors can also be used.

Although the switch box 22 (refer to FIG. 5 ) occupies the area of the chip, the cost of the chip area can be compensated. Due to the improved read range of the preferred embodiment of the present invention, the beta ratio (beta ratio) of the static random access memory cell can be small enough not to cause read errors, wherein the beta ratio is the drain current of the pull-down transistor to the transfer ratio of gate transistor drain current. Therefore, the pull-down element can be made smaller, eg, with a small channel width-to-length ratio. In this way, the cost of chip area can be compensated. Another benefit of the reduced beta ratio in the preferred embodiment is that the write range is improved, which results in states being more easily transitioned during write operations.

Preferred embodiments of the invention have various advantageous features. Static noise can be avoided using the SRAM cell composed of the preferred embodiment, and higher noise and higher element mismatch can be tolerated. Due to the improved noise tolerance, SRAM cells can be used in very small size technologies, eg 90nm and below. The operating voltage can also be reduced.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Those skilled in the art should be able to make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection should be subject to the scope defined by the appended claims.

Claims (15)

1. SRAM cell comprises:

One first load elements;

One first pull-down transistor;

One switch enclosure is coupled between above-mentioned first load elements and above-mentioned first pull-down transistor; And

One thread switching control is coupled to above-mentioned switch enclosure.

2. SRAM cell as claimed in claim 1, wherein above-mentioned switch enclosure is coupled to an ON-OFF control circuit, in order to provide a switch controlling signal to above-mentioned switch enclosure, wherein during the read operation of above-mentioned SRAM cell, above-mentioned switch controlling signal cuts off one first line between above-mentioned first load elements and above-mentioned first pull-down transistor, and during the write operation of above-mentioned SRAM cell above-mentioned first line of conducting.

3. SRAM cell as claimed in claim 1 also comprises:

One second load elements; And

One second pull-down transistor, itself and above-mentioned first load elements, above-mentioned first pull-down transistor and above-mentioned second load elements form a latch, and wherein above-mentioned switch enclosure also is coupled between above-mentioned second load elements and above-mentioned second pull-down transistor.

4. SRAM cell as claimed in claim 1, wherein above-mentioned first load elements is a resistance.

5. SRAM cell as claimed in claim 1, wherein above-mentioned first load elements are a P-type mos transistor.

6. SRAM cell as claimed in claim 1, wherein above-mentioned switch enclosure comprises one of metal oxide semiconductor transistor and bipolar transistor.

7. SRAM cell as claimed in claim 1, comprise that also one transmits grid element, be couple at least one above-mentioned first load elements and above-mentioned first pull-down transistor, wherein above-mentioned transmission grid element is selected from the group that is made up of a metal oxide semiconductor transistor and a bipolar transistor substantially.

8. SRAM cell as claimed in claim 1, wherein above-mentioned first pull-down transistor comprises bipolar transistor.

9. SRAM array comprises:

An array has a plurality of SRAM cells, and above-mentioned SRAM cell is arranged in multirow and the multiple row, and wherein each above-mentioned SRAM cell comprises:

One load elements;

One pull-down transistor; And

One switch enclosure is coupled between above-mentioned load elements and the above-mentioned pull-down transistor, and wherein above-mentioned switch enclosure is coupled to a thread switching control;

Many word lines be coupled to the above-mentioned SRAM cell of the above line that is positioned at above-mentioned array, and one of above-mentioned word line are coupled to the above-mentioned SRAM cell that is positioned at delegation;

Multiple bit lines be coupled to the above-mentioned SRAM cell of the above-mentioned row that are positioned at above-mentioned array, and one of above-mentioned bit line is coupled to the above-mentioned SRAM cell that is positioned at same row; And

Many thread switching controls are coupled to the above-mentioned switch enclosure of above-mentioned SRAM cell.

10. SRAM array as claimed in claim 9, wherein the above-mentioned thread switching control of at least a portion is coupled to the above-mentioned SRAM cell of the above line that is positioned at above-mentioned array, and one of above-mentioned thread switching control is coupled to the above-mentioned switch enclosure that is positioned at the above-mentioned SRAM cell of delegation.

11. SRAM array as claimed in claim 9, wherein the above-mentioned thread switching control of at least a portion is coupled to the above-mentioned SRAM cell of the above line that is positioned at above-mentioned array, and one of above-mentioned thread switching control is coupled to the above-mentioned switch enclosure of the above-mentioned SRAM cell that is positioned at same row.

12. SRAM array as claimed in claim 9, wherein above-mentioned thread switching control comprises:

One first group's thread switching control be coupled to the above-mentioned SRAM cell of the above line that is positioned at above-mentioned array, and one of above-mentioned thread switching control is coupled to the above-mentioned SRAM cell that is positioned at delegation; And

One second group's thread switching control be coupled to the above-mentioned SRAM cell of the above line that is positioned at above-mentioned array, and one of above-mentioned thread switching control is coupled to the above-mentioned SRAM cell that is positioned at same row.

13. SRAM array as claimed in claim 9, also comprise an ON-OFF control circuit that is coupled to above-mentioned thread switching control, wherein above-mentioned SRAM cell also comprises four, five, six, eight, ten, 12 or 14 transistors and Content Addressable Memory, or its combination.

14. SRAM array as claimed in claim 13, wherein above-mentioned ON-OFF control circuit is during the read operation of above-mentioned SRAM cell, the pairing above-mentioned switch enclosure of one of above-mentioned SRAM cell of not conducting, and during the write operation of above-mentioned SRAM cell, the pairing above-mentioned switch enclosure of one of above-mentioned SRAM cell of conducting.

15. SRAM array as claimed in claim 13, wherein above-mentioned ON-OFF control circuit is carried out in above-mentioned SRAM cell and is read or during write operation, not conducting with carry out the above-mentioned switch enclosure that the above-mentioned above-mentioned SRAM cell of reading or writing is coupled to other above-mentioned SRAM cell of same word line.

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