CN101075779A - Switching Voltage Regulators with Improved Input Voltage Range - Google Patents

Abstract

The switching voltage regulator has a first switch, a second switch and an inductor, which are coupled to a switching node. The switching control system applies a drive signal to control the first and second switches. The duty cycle detection circuit detects the duty cycle of the drive signal. When the duty cycle is greater than a predetermined critical value, the duty cycle detection circuit generates an above-critical signal. When the duty cycle is less than the predetermined critical value, the duty cycle detection circuit generates a below-critical signal. In response to the above-critical signal and the below-critical signal, the oscillation signal adjustment circuit generates an adjustment current. The oscillation signal generation circuit generates and applies an oscillation signal to the switching control system. The period of the oscillation signal is adjusted by the adjustment current.

Description

Switching Voltage Regulators with Improved Input Voltage Range

technical field

The invention relates to a switching voltage regulator, in particular to a switching voltage regulator with improved input voltage range.

Background technique

FIG. 1(a) shows a circuit diagram of a known switching voltage regulator 10a. The switching voltage regulator 10a converts the input voltage V _in into an output voltage V _out and supplies it to the load Ld. The upper switch SH is coupled between the input voltage _Vin and the switching node SN, and the lower switch SL is coupled between the switching node SN and the ground potential. In the example shown in FIG. 1( a ), the upper switch SH is implemented by a PMOS transistor and the lower switch SL is implemented by an NMOS transistor. The inductor L is coupled between the switch node SN and the output terminal O. The output capacitor C _o is coupled to the output terminal O to filter the output voltage V _out .

The switching voltage regulator 10 a has an oscillation signal generating circuit 11 and a switching control system 15 composed of a latch 12 , a PWM control circuit 13 and a driving circuit 14 . The oscillating signal generating circuit 11 generates a pulse oscillating signal PL and a ramp oscillating signal RM, which oscillate synchronously with each other. The rising edge (rising edge) of the pulse oscillation signal PL corresponds to the peak of the ramp oscillation signal RM, and the falling edge (falling edge) of the pulse oscillation signal PL corresponds to the valley of the ramp oscillation signal RM. The pulse oscillating signal PL is applied to the setting terminal S of the latch 12 , and the ramp oscillating signal RM is applied to the PWM control circuit 13 . When the rising edge of the pulse oscillation signal PL triggers the latch 12 via the setting terminal S, the driving signal DR from the output terminal Q of the latch 12 becomes a high level state. The driving signal DR of high level turns on the upper switch SH and turns off the lower switch SL via the driving circuit 14 , so the switching voltage regulator 10 a enters a so-called ON operation phase. During the ON operation phase, the inductor current _IL increases gradually.

The voltage feedback signal FV represents the output voltage V _out , and the current feedback signal FI represents the inductor current _IL . In response to the voltage feedback signal FV, the current feedback signal FI and the ramp oscillation signal RM, the PWM control circuit 13 applies a control signal CS to the reset terminal R of the latch 12 . Regardless of the current mode or voltage mode PWM control method, when the control signal CS triggers the latch 12 through the reset terminal R, the driving signal DR from the output terminal Q of the latch 12 becomes a low level state. The low-level drive signal DR turns off the upper switch SH and turns on the lower switch SL via the drive circuit 14 , so the switching voltage regulator 10 a enters a so-called OFF operation phase. During the OFF operation phase, the inductor current _IL gradually decreases.

Specifically, the switching voltage regulator 10 a shown in FIG. 1( a ) is a step-down type, which converts a higher input voltage V _in into a lower output voltage V _out . The duty cycle D _a of the step-down voltage regulator 10a can be expressed by the following equation (1a):

${\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; a</span>}}<span\; class="notranslate">\; \&equiv;</span>\frac{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; ON</span>}}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; ON</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; OFF</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; a</span>}<span\; class="notranslate">\; )</span>$

Among them, T _ON represents the time occupied by the ON operation phase in each cycle, and T _OFF represents the time occupied by the OFF operation phase in each cycle. The sum of T _ON and T _OFF is equal to the period T _S of the pulse oscillating signal PL (or the ramp oscillating signal RM).

It can be seen from the equation (1a), when the input voltage V _in is getting closer to the output voltage V _out , T _ON will increase more and more. Since the period T _S of the pulse oscillation signal PL is a fixed value, the increase of T _ON will shorten T _OFF . However, T _OFF must be limited because both the upper switch SH and the lower switch SH need a finite physical time to complete charge accumulation and removal from the non-conductive state to the conductive state from the non-conductive state. to be greater than a predetermined minimum value T _OFF,min to allow correct switching operation. For example, assuming that the minimum value TOFF _,min is set to be 15% of the switching period T _S , the maximum value that can be achieved by the duty cycle D _a is only 0.85. When the input voltage V _in continues to decrease and is less than (V _out /0.85), since T _OFF cannot be shortened any further, the switch-mode voltage regulator 10a cannot continue to regulate the required output voltage V _out . In a broad sense, when the input voltage V _in is less than [T _S /(T _S -T _{OFF, min} )]*V _out , the known switching voltage regulator 10 a cannot provide the required output voltage V _out .

FIG. 1(b) shows a circuit diagram of another known switching voltage regulator 10b. The switching voltage regulator 10 b shown in FIG. 1( b ) is a boost type, that is, it converts a lower input voltage V _in into a higher output voltage V _out . In the boost voltage regulator 10b, the upper switch SH is coupled between the switching node SN and the output terminal O, and the inductor L is coupled between the input voltage _Vin and the switching node SN. Moreover, the ON operation phase is performed by turning off the upper switch SH and turning on the lower switch SL, so that the inductor current _IL gradually increases. The OFF operation phase is performed by turning on the upper switch SH and turning off the lower switch SL, so that the inductor current _IL gradually decreases. The duty cycle _Db of the boost voltage regulator 10b can be expressed by the following equation (1b):

${\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; b</span>}}<span\; class="notranslate">\; \&equiv;</span>\frac{{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; ON</span>}}}{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; ON</span>}}<span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; T</span>}}_{\mathrm{<span\; class="notranslate">\; OFF</span>}}<span\; class="notranslate">\; )</span>}<span\; class="notranslate">\; =</span>\frac{<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; in</span>}}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; V</span>}}_{\mathrm{<span\; class="notranslate">\; out</span>}}}<span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; -</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}\mathrm{<span\; class="notranslate">\; b</span>}<span\; class="notranslate">\; )</span>$

It can be seen from the equation (1b) that when the input voltage V _in is getting closer to the output voltage V _out , T _ON will be shortened more and more. However, since both the upper switch SH and the lower switch SL from the non-conductive state to the conductive state require a finite physical time to complete the charge accumulation and removal, T _ON must be limited becomes greater than a predetermined minimum value T _ON,min to allow correct switching operation. For example, assuming that the minimum value T _{ON, min} is set to be 15% of the switching period T _S , the maximum value that can be achieved by the duty cycle D _b is only 0.85. When the input voltage V _in continues to increase and is greater than (0.85*V _out ), since T _ON cannot be shortened any longer, the switching voltage regulator 10b cannot continue to regulate the required output voltage V _out . In a broad sense, when the input voltage V _in is greater than [(T _S −T _{ON, min} )/T _S ]*V _out , the known switching voltage regulator 10 b cannot provide the required output voltage V _out .

Contents of the invention

In view of the aforementioned problems, the object of the present invention is to provide a switch-mode voltage regulator with improved input voltage range.

According to one aspect of the present invention, a switching voltage regulator is provided for converting an input voltage into an output voltage. The switching voltage regulator has: a first switch, a second switch, an inductor, a switching control system, a duty cycle detection circuit, an oscillation signal adjustment circuit and an oscillation signal generation circuit. The first switch, the second switch and the inductor are commonly coupled to a switching node. When the first switch is turned on and the second switch is not turned on, the inductor current flowing through the inductor increases. When the first switch is off and the second switch is on, the inductor current decreases. The switching control system generates a driving signal to control the first switch and the second switch. The duty cycle detection circuit detects the duty cycle of the driving signal. When the duty cycle is greater than a predetermined threshold, the duty cycle detection circuit generates an above-threshold signal. When the duty cycle is less than the predetermined threshold, the duty cycle detection circuit generates a sub-threshold signal. In response to the above-threshold signal and the below-threshold signal, the oscillating signal adjustment circuit generates an adjustment current. The oscillating signal generating circuit generates and applies an oscillating signal to the switching control system. The period of the oscillating signal is adjusted by the adjusting current.

Description of drawings

Fig. 1 (a) shows the circuit diagram of known switching voltage regulator;

Fig. 1 (b) shows the circuit diagram of another known switching voltage regulator;

FIG. 2 shows a circuit diagram of a switching voltage regulator according to a first embodiment of the present invention;

Fig. 3 shows the detailed circuit diagram of the oscillating signal generating system in Fig. 2;

Fig. 4 shows the operating waveform timing diagram of the oscillating signal generation system in Fig. 2;

FIG. 5 shows a circuit diagram of a switching voltage regulator according to a second embodiment of the present invention;

Fig. 6 shows the detailed circuit diagram of the oscillating signal generating system in Fig. 5;

FIG. 7 shows a timing diagram of operation waveforms of the oscillating signal generating system in FIG. 5 .

[Description of main component symbols]

10a, 10b Switching Voltage Regulators

11 Oscillating signal generating circuit

12 latches

13 PWM control circuit

14 drive circuit

15 switch control system

20, 50 Switching voltage regulator

21, 51 duty cycle detection circuit

22, 52 Oscillation signal adjustment circuit

23, 53 Oscillating signal generation circuit

24,54 Oscillating signal generation system

31 Comparator

32 Click circuit

33 delay circuit

34, 35, 37 NOR logic gates

36 NAND logic gates

56 OR logic gates

57 AND logic gates

SH upper side switch

SL lower side switch

SN switch node

V _in input voltage

V _out output voltage

O output

L inductance

I _L inductor current

Ld load

C _o input capacitance

RM ramp oscillation signal

PL pulse oscillation signal

FV voltage feedback signal

FI current feedback signal

CS control signal

DR driving signal

DS1 first auxiliary signal

DS2 second auxiliary signal

OT Signal above critical

UT Signal below critical

N1～N5 NMOS transistors

P1～P3 PMOS transistors

Detailed ways

The foregoing and other objects, features, and advantages of the present invention will be more apparent from the following description and accompanying drawings. Here, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a circuit diagram of a switching voltage regulator 20 according to a first embodiment of the present invention. The switching voltage regulator 20 is a step-down type, that is, it converts a higher input voltage V _in into a lower output voltage V _out . The switching voltage regulator 20 has a switching control system 15 and an oscillation signal generating system 24 . The switching control system 15 is composed of a latch 12 , a PWM control circuit 13 and a drive circuit 14 . The oscillation signal generation system 24 is composed of a duty cycle detection circuit 21 , an oscillation signal adjustment circuit 22 and an oscillation signal generation circuit 23 .

Specifically, the duty cycle detection circuit 21 detects the duty cycle _Da of the driving signal DR. As the input voltage V _in gets closer to the output voltage V _out , the duty cycle D _a of the driving signal DR becomes larger. When the duty cycle D _a of the driving signal DR exceeds a predetermined threshold, the duty cycle detection circuit 21 generates an above-threshold signal OT. In response to the above-threshold signal OT, the oscillation signal adjustment circuit 22 causes the oscillation signal generation circuit 23 to extend the period T _S of the pulse oscillation signal PL (and the ramp oscillation signal RM). It can be seen from equation (1a) that, when the minimum value T _OFF,min is fixed, a longer period T _S can allow a larger duty cycle D _a . Moreover, the lower limit of the applicable range of the input voltage V _in [T _S /(T _S -T _OFF,min )]*V _out expands closer to the output voltage V _out as the period T _S becomes longer. As a result, the switching voltage regulator 20 according to the present invention can be applied to a wider input voltage range.

On the other hand, in order to prevent the period T _S from being extended too long so that the switching frequency is too low, when the duty cycle _Da of the drive signal DR is lower than the predetermined critical value, the duty cycle detection circuit 21 generates a signal UT below the threshold . In response to the sub-threshold signal UT, the oscillation signal adjustment circuit 22 causes the oscillation signal generation circuit 23 to shorten the period T _S of the pulse oscillation signal PL (and the ramp oscillation signal RM).

Here, the operation of the oscillating signal generating system 24 according to the present invention will be described in detail with reference to FIGS. 3 and 4 as follows. Assume first that the NMOS transistor N1 of the oscillation signal generating circuit 23 is turned on, so that the voltage at the oscillation node N _osc drops to the ground potential. Once the NMOS transistor N1 of the oscillating signal generating circuit 23 enters the non-conducting state, the oscillating current source I _osc immediately charges the oscillating capacitor C _osc , so that the voltage at the oscillating node N _osc gradually rises. The non-inverting input of the comparator 31 receives the voltage at the oscillating node N _osc , and the inverting input thereof receives the reference voltage source V _ref . When the voltage at the oscillation node N _osc exceeds the reference voltage source V _ref , the comparator 31 outputs a rising edge to trigger the click circuit 32 to generate the first auxiliary signal DS1 . After the first auxiliary signal DS1 passes through the delay circuit 33 and the inverter, the second auxiliary signal DS2 is formed. Therefore, the second auxiliary signal DS2 lags behind the first auxiliary signal DS1 by a predetermined delay time dt, and the phase difference between the two waveforms is 180 degrees. Subsequently, the first and second auxiliary signals DS1 and DS2 are coupled into the pulse oscillation signal PL via the NOR logic gate 34 . Once the second auxiliary signal DS2 changes from a high level to a low level, the NOR logic gate 35 outputs a high level signal to turn on the NMOS transistor N1, so that the voltage at the oscillation node N _osc rapidly drops to the ground potential. Therefore, the voltage at the oscillation node N _osc is output as the ramp oscillation signal RM.

The first and second auxiliary signals DS1 and DS2 are applied to the duty cycle detection circuit 21 to help detect the duty cycle _Da of the driving signal DR. The first auxiliary signal DS1 is used to set a threshold. In the duty cycle detection circuit 21 , the three input terminals of the NAND logic gate 36 respectively receive the first auxiliary signal DS1 , the second auxiliary signal DS2 and the driving signal DR. When the duty cycle D _a of the driving signal DR is smaller than the critical value set by the first auxiliary signal DS1, for example, the first, second, and fifth cycles PP1, PP2, and PP5 shown in FIG. 4 , the NAND logic gate 36 The output terminal is maintained at low level. When the duty cycle _D a of the driving signal DR is greater than the threshold value set by the first auxiliary signal DS1, for example, the third and fourth periods PP3 and PP4 shown in FIG. 4, the output terminal of the NAND logic gate 36 generates a pulse, Used as the above-critical signal OT. Please note that the pulse width of the above-threshold signal OT is determined according to the difference between the duty cycle D _a of the driving signal DR and the threshold value. The greater the difference between the duty cycle D _a of the driving signal DR and the threshold value, the greater the pulse width of the above-threshold signal OT will be. For example, in FIG. 4 , the above-threshold signal OT of the third period PP3 has a larger pulse width than the above-threshold signal OT of the fourth period PP4 .

On the other hand, in the duty cycle detection circuit 21 , the three input terminals of the NOR logic gate 37 respectively receive the first auxiliary signal DS1 , the inverted second auxiliary signal DS2 and the driving signal DR. When the duty cycle _{D a} of the driving signal DR is greater than the threshold value set by the first auxiliary signal DS1, such as the third and fourth cycles PP3 and PP4 shown in FIG. flat. When the duty cycle D _a of the driving signal DR is less than the critical value set by the first auxiliary signal DS1, for example, the first, second and fifth cycles PP1, PP2 and PP5 shown in FIG. 4, the output of the NOR logic gate 37 A pulse is generated at the terminal, which is used as the signal UT below the threshold. Please note that the pulse width of the sub-threshold signal UT is determined according to the difference between the duty cycle D _a of the driving signal DR and the threshold value. The greater the difference between the duty cycle D _a of the driving signal DR and the threshold value, the larger the pulse width of the sub-threshold signal UT will be. For example, in FIG. 4 , the sub-threshold signal UT of the first period PP1 has a larger pulse width than the sub-threshold signal UT of the second period PP2 .

The above-threshold signal OT is applied to the oscillating signal adjustment circuit 22 to turn on the PMOS transistor P1 so that the current source _I1 charges the adjustment capacitor C _adj . The potential difference across the two ends of the adjustment capacitor C _adj passes through the level shift transistor N3 to form the adjustment voltage V _adj . The adjustment voltage V _adj is applied to the adjustment resistor R _adj to generate an adjustment current I _adj . Assuming that the PMOS transistors P2 and P3 jointly form a 1×1 current mirror, and the NMOS transistors N4 and N5 jointly form another 1×1 current mirror, then an adjustment current I _adj same as that described above will flow between the drain and the source of the NMOS transistor N5 Pass. In the case where the adjustment current I _adj exists, the current charging the oscillation capacitor C _osc in the oscillation signal generating circuit 23 decreases to become (I _osc −I _adj ). As a result, the voltage rise rate at the oscillation node N _osc slows down, making the period T _s of the ramp oscillation signal RM (and the pulse oscillation signal PL ) longer. For example, in FIG. 4 , the third period PP3 generates a signal OT above the threshold, which makes the period of the fourth period PP4 longer than the previous period by dT ₁ , and the fourth period PP4 also generates a signal OT above the threshold, making the fifth period PP4 The cycle of PP5 was extended by dT ₂ compared to the previous cycle. Since a longer period T _S allows a larger duty cycle D _a to exist, the input voltage V _in can be closer to the output voltage V _out , so that the switching voltage regulator 20 according to the present invention can be applied to a wider range of input voltages scope.

When the pulse width of the above-threshold signal OT is wider, the PMOS transistor P1 of the oscillation signal adjustment circuit 22 remains on for a longer time, so that the adjustment voltage V _adj rises higher. As a result, a larger adjustment current I _adj flows between the drain and source of the NMOS transistor N5 , making the period T _S of the ramp oscillation signal RM (and the pulse oscillation signal PL ) longer.

The sub-threshold signal UT is applied to the oscillation signal adjustment circuit 22 to turn on the NMOS transistor N2 so that the current source _I2 discharges the adjustment capacitor C _adj . As a result, the potential difference across the adjustment capacitor C _adj decreases, so that both the adjustment voltage V _adj and the adjustment current I _adj decrease. Because the current charging the oscillation capacitor C _osc in the oscillation signal generating circuit 23 is (I _osc −I _adj ), the lower adjustment current I _adj makes the voltage rise rate at the oscillation node N _osc recover and increase. As a result, the period T _S of the ramp oscillating signal RM (and the pulse oscillating signal PL) also recovers and shortens accordingly. For example, in FIG. 4 , the fifth period PP5 generates the sub-threshold signal UT, so that the period of the sixth period PP6 is shortened by dT ₃ compared with the previous period. Therefore, when the input voltage V _in is close to the output voltage V _out , the switching voltage regulator 20 according to the present invention can automatically adjust (ie extend or shorten) the switching period T _S to obtain the most appropriate switching period T _S .

Please note that when the gap between the input voltage V _in and the output voltage V _out is large, the duty cycle D _a of the driving signal DR is continuously smaller than the critical value set by the first auxiliary signal DS1, for example, the first auxiliary signal DS1 shown in FIG. 4 and the second period PP1 and PP2. In this case, the sub-threshold signal UT is continuously applied to the oscillating signal adjustment circuit 22 , causing the adjustment capacitor C _adj to be continuously discharged to maintain the potential difference between the two ends at zero. As a result, the period T _S of the ramp oscillating signal RM (and the pulse oscillating signal PL) is maintained at a minimum.

FIG. 5 shows a circuit diagram of a switching voltage regulator 50 according to a second embodiment of the present invention. The second embodiment shown in FIG. 5 is different from the first embodiment shown in FIG. 2 in that the switched-mode voltage regulator 50 according to the second embodiment is a boost type. That is, the switching voltage regulator 50 converts the lower input voltage V _in into a higher output voltage V _out to supply to the load Ld. Therefore, in the switching voltage regulator 50, the upper switch SH is coupled between the switching node SN and the output terminal O, the lower switch SL is coupled between the switching node SN and the ground potential, and the inductor L is coupled between the input voltage V _in and the switching Between nodes SN.

The switching voltage regulator 50 is different from the known switching voltage regulator 10b shown in FIG. The oscillating signal generating circuit 53 together constitutes an oscillating signal generating system 54 . Specifically, the duty cycle detection circuit 51 detects the duty cycle D _b of the driving signal DR. As the input voltage V _in gets closer to the output voltage V _out , the duty cycle D _b of the driving signal DR becomes smaller and smaller. When the duty cycle _Db of the driving signal DR is lower than a predetermined threshold, the duty cycle detection circuit 51 generates a below-threshold signal UT. In response to the sub-threshold signal UT, the oscillation signal adjustment circuit 52 causes the oscillation signal generation circuit 53 to extend the period T _S of the ramp oscillation signal RM (and the pulse oscillation signal PL). From the equation (1b), it can be seen that when the minimum value T _{ON, min} is fixed, a longer period T _S can allow a smaller duty cycle D _b to exist. In addition, the upper limit of the applicable range of the input voltage V _in [(T _S −T _{ON, min} )/T _S ]*V _out expands as the period T _S becomes longer and approaches the output voltage V _out . As a result, the switching voltage regulator 50 according to the present invention can be applied to a wider input voltage range.

On the other hand, in order to prevent the period T _S from being extended too long and the switching frequency being too low, when the duty cycle D _b of the driving signal DR is greater than a predetermined threshold, the duty cycle detection circuit 51 generates an above-threshold signal OT. In response to the above-threshold signal OT, the oscillation signal adjustment circuit 52 causes the oscillation signal generation circuit 53 to shorten the period T _S of the ramp oscillation signal RM (and the pulse oscillation signal PL).

FIG. 6 shows a detailed circuit diagram of the oscillation signal generation system 54 in FIG. 5 . Comparing Fig. 3 with Fig. 6, it can be seen that the oscillation signal generation system 54 of the second embodiment is different from the oscillation signal generation system 24 of the first embodiment in that the duty cycle detection circuit 51 of the oscillation signal generation system 54 uses AND logic gates 56 generates the below-threshold signal UT and uses OR logic gate 57 to generate the above-threshold signal OT.

FIG. 7 shows a timing diagram of operation waveforms of the oscillating signal generating system 54 in FIG. 5 . In the first and second periods PP1 and PP2, the duty cycle _Db of the driving signal DR is greater than the threshold value set by the second auxiliary signal DS2, thus generating the above-threshold signal OT. Assuming that the period T _S of the first period PP1 has reached the minimum value, the periods of the second and third periods PP2 and PP3 are still maintained at the minimum value of the period T _S. In the third period PP3, the duty cycle _Db of the driving signal DR is smaller than the critical value set by the second auxiliary signal DS2, thus generating a signal UT below the threshold, so that the period of the fourth period PP4 is extended by dT compared with the previous period ₁ . In the fourth period PP4, the duty cycle _Db of the drive signal DR is still smaller than the critical value set by the second auxiliary signal DS2, so a signal UT below the threshold is generated, so that the period of the fifth period PP5 is extended compared with the previous period dT ₂ . In the fifth period PP5, the duty cycle _Db of the driving signal DR becomes greater than the critical value set by the second auxiliary signal DS2, thus generating the above-critical signal OT, so that the period of the sixth period PP6 is shortened compared with the previous period dT ₃ . Therefore, when the input voltage V _in is close to the output voltage V _out , the switching voltage regulator 50 according to the present invention can automatically adjust (ie extend or shorten) the switching period T _S to obtain the most appropriate switching period T _S .

While the present invention has been described by way of illustration of preferred embodiments, it should be expressly noted that the invention is not limited to the embodiments disclosed herein. On the contrary, the invention covers various modifications and similar arrangements apparent to those skilled in the art. Accordingly, the scope of the claims should be interpreted in the broadest sense to encompass all such modifications and similar arrangements.

Claims (10)

1, a kind of changeover voltage adjuster is used for an input voltage is converted to an output voltage, comprises:

One first switch;

One second switch;

One inductance, wherein said first switch, described second switch and described inductance coupled in common are switched node in one, make when described first switch conduction and described not conducting of second switch, the inductive current of described inductance of flowing through increases, and when described first not conducting of switch and described second switch conducting, described inductive current reduces;

One switches control system, is used to produce a drive signal to control described first switch and described second switch;

One duty cycle circuit for detecting, be used to detect the duty cycle of described drive signal, when described duty cycle during greater than a predetermined critical value, described duty cycle circuit for detecting produces a critical above signal, and when described duty cycle during less than described predetermined critical value, described duty cycle circuit for detecting produces a critical following signal;

One oscillator signal is adjusted circuit, produces an adjustment electric current in response to described critical above signal and described critical following signal; And

One oscillator signal produces circuit, is used for generation and applies an oscillator signal to described handover control system, and the cycle of wherein said oscillator signal is adjusted by described adjustment electric current.

2, changeover voltage adjuster as claimed in claim 1, wherein:

Described critical above signal makes described oscillator signal adjustment circuit increase described adjustment electric current, and described critical following signal makes described oscillator signal adjustment circuit reduce described adjustment electric current.

3, changeover voltage adjuster as claimed in claim 1, wherein:

Described critical above signal makes described oscillator signal adjustment circuit reduce described adjustment electric current, and described critical following signal makes described oscillator signal adjustment circuit increase described adjustment electric current.

4, changeover voltage adjuster as claimed in claim 1, wherein:

When described adjustment electric current is healed when big, the described cycle of described oscillator signal is adjusted to longer.

5, changeover voltage adjuster as claimed in claim 1, wherein:

When described adjustment electric current was zero, the described cycle of described oscillator signal was in a minimum value.

6, changeover voltage adjuster as claimed in claim 1, wherein:

Described first switch is coupled between described input voltage and described switching node;

Described second switch is coupled between a described switching node and an earthing potential; And

Described inductance coupling high is between described switching node and described output voltage.

7, changeover voltage adjuster as claimed in claim 1, wherein:

Described first switch is coupled between a described switching node and an earthing potential;

Described second switch is coupled between described switching node and described output voltage; And

Described inductance coupling high is between described input voltage and described switching node.

8, changeover voltage adjuster as claimed in claim 1, wherein:

Described input voltage is higher than described output voltage.

9, changeover voltage adjuster as claimed in claim 1, wherein:

Described input voltage is lower than described output voltage.

10, changeover voltage adjuster as claimed in claim 1, wherein:

Described handover control system has:

One pwm control circuit is used to respond described output voltage, described inductive current, produces a control signal with described oscillator signal;

One latch is used to respond described oscillator signal and described control signal and produces described drive signal; And

One drive circuit is used to respond described drive signal and controls described first switch and described second switch.

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