CN101075596A - Stackable semiconductor package structure and manufacturing method thereof - Google Patents

Abstract

The present invention discloses a stacked semiconductor packaging structure and a manufacturing method thereof, wherein the stacked semiconductor packaging structure comprises a first substrate, a semiconductor element, a plurality of bumps, a plurality of first wires, a second substrate and a sealing material. The semiconductor element is located on the first substrate and is electrically connected to the first substrate. The bumps are located above the semiconductor element. The first wires electrically connect the bumps to the first substrate. The bumps are in contact with the second substrate. The sealing material covers the first substrate, the semiconductor element, the bumps, the first wires and the second substrate. In this way, wire bonding operations on the second substrate can be avoided, so the problems of the second substrate being suspended and shaking in the existing packaging structure will not occur.

Description

Stackable semiconductor package structure and manufacturing method thereof

technical field

The present invention relates to a stacked semiconductor packaging structure, and in particular to a stacked semiconductor packaging structure using bumps to support a substrate.

Background technique

Please refer to FIG. 1 , which is a schematic cross-sectional view of a conventional stacked semiconductor package structure. The conventional stacked semiconductor package structure 1 includes a first substrate 11 , a chip 12 , a second substrate 13 , a plurality of wires 14 and a sealing material 15 . The first substrate 11 has a first surface 111 and a second surface 112 . The chip 12 is flip-chip attached to the first surface 111 of the first substrate 11 . The second substrate 13 is adhered on the chip 12 by an adhesive layer 16, the second substrate 13 has a first surface 131 and a second surface 132, wherein the first surface 131 has a plurality of first pads 133 and several second welding pads 134. The surface area of the second substrate 13 is larger than the surface area of the chip 12 , so that a part of the second substrate 13 extends beyond the chip 12 to form a floating portion.

The wires 14 are electrically connected to the first pads 133 of the second substrate 13 to the first surface 111 of the first substrate 11 . The sealing material 15 covers the first surface 111 of the first substrate 11, the chip 12, the wires 14 and part of the second substrate 13, and exposes the second solder joints on the first surface 131 of the second substrate 13. pad 134 to form a mold area opening (Mold Area Opening) 17. In general, the existing stacked semiconductor package structure 1 can be stacked with another package structure 18 or other components in the sealing opening 17, wherein the solder balls 181 of the package structure 18 are electrically connected to the These second pads 134 of the second substrate 13 .

The disadvantages of the conventional stacked semiconductor package structure 1 are as follows. First of all, since the second substrate 13 has a floating portion, the first pads 133 are located on the periphery of the relative position of the chip 12 (that is, the floating portion), and these first pads 133 are opposite to the edge of the chip 12. The distance between positions is defined as an overhang length. Experiments have shown that when the suspended length is greater than three times the thickness of the second substrate 13, and in this case, the suspended part will shake or vibrate during wire bonding operations, and It is unfavorable for the wiring operation. What's more, when the second substrate 13 receives too much downward stress during the wire bonding operation, the second substrate 13 will be cracked. Secondly, because there will be the above-mentioned shaking, vibration or cracking, the suspended part cannot be too long, so that the area of the second substrate 13 is limited, so it needs to be limited in the sealing opening 17 to expose the second substrate 13. The layout space of the second pads 134 on the first surface 131 of the substrate 13 . In addition, during the molding process, the sealing material 15 will overflow between the upper mold (not shown in the figure) and the first surface 131 of the second substrate 13, and the overflowing material will form residual material. (Flash), thereby contaminating the second pads 134.

Therefore, it is necessary to provide a new stacked semiconductor package structure to solve the above problems.

Contents of the invention

The main purpose of the present invention is to provide a stacked semiconductor packaging structure, the structure of which is reasonably arranged, not only can make the packaging structure have good structural stability, but also can ensure that the signal transmission effect is good.

Another object of the present invention is to provide a method for manufacturing a stacked semiconductor package structure, which does not need to perform wire bonding on the second substrate, thereby ensuring the stability of the structure. It is not easy to be polluted, so that it can produce a good signal transmission effect.

In order to achieve the above object or other objects, the present invention adopts the following technical solutions: a stacked semiconductor package structure, which includes: a first substrate, a semiconductor element, several bumps, several first wires, a first Two substrates and a sealing material, wherein the first substrate has a first surface and a second surface; the semiconductor element is located on the first surface of the first substrate and is electrically connected to the first substrate the first surface of the first substrate; the bump is located above the semiconductor element; the first wire is used to electrically connect these bumps to the first surface of the first substrate; the second substrate has a first a surface and a second surface, and the bump is in contact with the second surface of the second substrate; the sealing material is used to cover the first surface of the first substrate, the semiconductor element, The bump, the first wire and the second surface of the second substrate.

To achieve the above object or other objects, the present invention also adopts the following technical solution: a method for manufacturing a stacked semiconductor package structure, which includes steps a to g, wherein step a is to provide a first substrate, and the first A substrate has a first surface and a second surface; step b is attaching a semiconductor element to the first surface of the first substrate, and the semiconductor element is electrically connected to the first surface of the first substrate ; step c is to form a plurality of bumps above the semiconductor element; step d is to form a plurality of first wires for electrically connecting these bumps to the first surface of the first substrate; step e is to provide a The second substrate, the second substrate has a first surface and a second surface; step f is to arrange the second substrate on these bumps, so that these bumps contact the second surface of the second substrate. surface; and step g is using a sealing material to cover the first surface of the first substrate, the semiconductor element, the bumps, the first wires and the second surface of the second substrate.

Compared with the prior art, in the present invention, since there is no need for wire bonding on the second substrate, problems such as suspension and shaking of the second substrate in the existing packaging structure will not occur. Moreover, during the encapsulation process of the encapsulant material, the encapsulant material will not overflow between the upper mold and the first surface of the second substrate, so the first pads will not be polluted. In addition, the upper surface (i.e., the first surface of the second substrate) of the stacked semiconductor package structure of the present invention is a flat surface, which not only has good flatness, but also can place larger or more other package structures. or other components.

Description of drawings

FIG. 1 is a schematic cross-sectional view of a conventional stacked semiconductor package structure.

FIG. 2 is a schematic cross-sectional view of the first embodiment of the stacked semiconductor package structure of the present invention.

FIG. 3 is a flow chart of the manufacturing method of the first embodiment of the stacked semiconductor package structure of the present invention.

4 is a schematic cross-sectional view of a second embodiment of the stacked semiconductor package structure of the present invention.

FIG. 5 is a flow chart of the manufacturing method of the second embodiment of the stacked semiconductor package structure of the present invention.

FIG. 6 is a schematic cross-sectional view of a third embodiment of the stacked semiconductor package structure of the present invention.

Detailed ways

Please refer to FIG. 2 , which is a schematic cross-sectional view of the first embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 2 includes a first substrate 21, a semiconductor element 22, several stud bumps (Stud Bump) 23, several first wires 24, a second substrate 25, a supporting colloid 26, a sealant Material 27, several solder balls 28.

The first substrate 21 has a first surface 211 and a second surface 212 . The semiconductor element 22 is located on the first surface 211 of the first substrate 21 and is electrically connected to the first surface 211 of the first substrate 21 . In this embodiment, the semiconductor device 22 is a chip, and the semiconductor device 22 is flip-chip attached to the first surface 211 of the first substrate 21 .

These bumps 23 (such as gold stud bumps) are located above the semiconductor element 22 . In this embodiment, the bumps 23 are located on the top surface of the semiconductor element 22 . The first wires 24 are used to connect the bumps 23 to the first surface 211 of the first substrate 21 .

The second substrate 25 has a first surface 251 and a second surface 252 . The first surface 251 of the second substrate 25 has a plurality of first welding pads 253 , and the second surface 252 of the second substrate 25 has a plurality of second welding pads 254 . The bumps 23 are in contact with the second pads 254 on the second surface 252 of the second substrate 25 to form an electrical connection. The bumps 23 are used to support the second substrate 25 and transmit signals of the second substrate 25 to the first substrate 21 through the first wires 24 .

The supporting gel 26 is located between the top surface of the semiconductor device 22 and the second surface 252 of the second substrate 25 for increasing the supporting force of the second substrate 25 . The sealing material 27 covers the first surface 211 of the first substrate 21 , the semiconductor element 22 , the bumps 23 , the first wires 24 , the second surface 252 of the second substrate 25 and the supporting glue 26 . The solder balls 28 are located on the second surface 212 of the first substrate 21 .

Under normal circumstances, the stacked semiconductor package structure 2 can then stack another package structure 29 or other components on the first surface 251 of the second substrate 25 , and with the first surface 251 of the second substrate 25 The first pads 253 on the top are electrically connected.

Please refer to the flowchart of the manufacturing method of the first embodiment of the stacked semiconductor package structure of the present invention shown in FIG. 3 . Please also refer to FIG. 2 , the manufacturing method of the stacked semiconductor package structure 2 includes the following steps. Step S301 is to provide a first substrate 21 having a first surface 211 and a second surface 212 . Step S302 is attaching a semiconductor device 22 to the first surface 211 of the first substrate 21 , and the semiconductor device 22 is electrically connected to the first surface 211 of the first substrate 21 . In this embodiment, the semiconductor device 22 is a chip, and the semiconductor device 22 is flip-chip attached to the first surface 211 of the first substrate 21 .

Step S303 is to form a support colloid 26 above the semiconductor device 22 . In this embodiment, the supporting colloid 26 is directly formed and adhered to the top surface of the semiconductor device 22 . It should be noted that this step is an optional step. Step S304 is to form a plurality of bumps 23 (such as gold stud bumps) on the semiconductor element 22 . In this embodiment, the bumps 23 are directly formed and attached to the top surface of the semiconductor device 22 .

Step S305 is to form a plurality of first wires 24 for electrically connecting the bumps 23 to the first surface 211 of the first substrate 21 . Step S306 is to provide a second substrate 25 having a first surface 251 and a second surface 252 . Step S307 is disposing the second substrate 25 on the bumps 23 and the supporting glue 26 , so that the bumps 23 and the supporting glue 26 contact and support the second surface 252 of the second substrate 25 .

Step S308 is a potting process, which uses a sealing material 27 to cover the first surface 211 of the first substrate 21, the semiconductor element 22, the bumps 23, the first wires 24, the supporting glue 26 and the The second surface 252 of the second substrate 25 . Step S309 is to form a plurality of solder balls 28 on the second surface 212 of the first substrate 21 to obtain the stacked semiconductor package structure 2 .

In the present invention, since there is no need to perform wire bonding on the second substrate 25 , problems such as suspension and shaking of the second substrate 13 in the conventional package structure 1 ( FIG. 1 ) will not occur. Furthermore, during the potting process of the sealing material 27, the sealing material 27 will not overflow into between the upper mold (not shown in the figure) and the first surface 251 of the second substrate 25, so these first Solder pad 253 will not be contaminated. In addition, the upper surface of the stacked semiconductor package structure 2 (that is, the first surface 251 of the second substrate 25) is a flat surface, which not only has good flatness, but also can place larger or more other components. A packaging structure 29 or other components.

Please refer to FIG. 4 , which is a schematic cross-sectional view of the second embodiment of the stacked semiconductor package structure of the present invention. The stacked semiconductor package structure 3 includes a first substrate 31, a semiconductor element 32, several second wires 33, an intermediate element 34, several bumps 35, several first wires 36, a second substrate 37, A support colloid 38 , sealing material 39 and several solder balls 40 .

The first substrate 31 has a first surface 311 and a second surface 312 . The semiconductor element 32 is located on the first surface 311 of the first substrate 31 and is electrically connected to the first surface 311 of the first substrate 31 . In this embodiment, the semiconductor element 32 is a first chip, the semiconductor element 32 is adhered on the first surface 311 of the first substrate 31, and is electrically connected to the first substrate 31 by the second wires 33 The first surface 311 of.

The interposer 34 is attached to the semiconductor device 32 . The intermediary element 34 can be a spacer without electrical function; or the intermediary element 34 can be another chip with electrical function.

These bumps 35 (such as gold stud bumps) are located above the semiconductor element 32 . In this embodiment, the bumps 35 are located on the top surface of the intermediary element 34 . The first wires 36 can electrically connect the bumps 35 to the first surface 311 of the first substrate 31 .

The second substrate 37 has a first surface 371 and a second surface 372 . The first surface 371 of the second substrate 37 has a plurality of first welding pads 373 , and the second surface 372 of the second substrate 37 has a plurality of second welding pads 374 . The bumps 35 are electrically connected to and in contact with the second pads 374 on the second surface 372 of the second substrate 37 . The bumps 35 are used to support the second substrate 37 and transmit signals of the second substrate 37 to the first substrate 31 through the first wires 35 .

The supporting glue 38 is located between the top surface of the intermediary element 34 and the second surface 372 of the second substrate 37 for increasing the supporting strength of the second substrate 37 . The sealing material 39 covers the first surface 311 of the first substrate 31 , the semiconductor element 32 , the second wires 33 , the intermediate element 34 , the bumps 35 , the first wires 36 , the second substrate 37 The second surface 372 and the supporting colloid 38 . The solder balls 40 are located on the second surface 312 of the first substrate 31 .

Under normal circumstances, since the upper surface of the stacked semiconductor package structure 3 of the present invention (i.e. the first surface 371 of the second substrate 37) is a flat surface, the stacked semiconductor package structure 3 can be another package structure 41 or other elements are stacked on the first surface 371 of the second substrate 37 and electrically connected to the first pads 373 on the first surface 371 of the second substrate 37 .

Refer to the flow chart of the manufacturing method of the second embodiment of the stacked semiconductor package structure of the present invention shown in FIG. 5 . Please also refer to FIG. 4 , the manufacturing method of the stacked semiconductor package structure 3 includes the following steps. Step S501 is to provide a first substrate 31 having a first surface 311 and a second surface 312 . Step S502 is attaching a semiconductor device 32 to the first surface 311 of the first substrate 31 , and the semiconductor device 32 is electrically connected to the first surface 311 of the first substrate 31 . In this embodiment, the semiconductor element 32 is a first chip. In this step, the semiconductor element 32 is adhered to the first surface 311 of the first substrate 31, and the semiconductor element 32 is bonded by using the second wires 33 Electrically connected to the first surface 311 of the first substrate 31 .

Step S503 is to adhere an interposer 34 to the top surface of the semiconductor device 32 . The intermediary element 34 can be a spacer without electrical function; or the intermediary element 34 can be another chip with electrical function.

Step S504 is to form a support colloid 38 above the semiconductor device 32 . In this embodiment, the supporting gel 38 is directly formed and adhered to the top surface of the intermediary element 34 . It should be noted that this step is an optional step. Step S505 is to form a plurality of bumps 35 (such as gold stud bumps) on the semiconductor element 32 . In this embodiment, the bumps 35 are directly formed and attached to the top surface of the intermediate element 34 .

Step S506 is to form a plurality of first wires 36 to electrically connect the bumps 35 to the first surface 311 of the first substrate 31 . Step S507 is to provide a second substrate 37 having a first surface 371 and a second surface 372 . Step S508 is disposing the second substrate 37 on the bumps 35 and the supporting glue 38 , so that the bumps 35 are in contact with the supporting glue 38 and used to support the second surface 372 of the second substrate 37 .

Step S509 is a potting process, which utilizes a sealing material 39 to cover the first surface 311 of the first substrate 31, the semiconductor element 32, the second wires 33, the intermediate element 34, the bumps 35, the The first wire 36 , the second surface 372 of the second substrate 37 and the supporting glue 38 . Step S510 is to form a plurality of solder balls 40 on the second surface 312 of the first substrate 31 to obtain the stacked semiconductor package structure 3 .

Please refer to FIG. 6 , which is a schematic cross-sectional view of a third embodiment of the stacked semiconductor package structure of the present invention. The difference between the stacked semiconductor package structure 5 and the stacked semiconductor package structure 3 ( FIG. 4 ) of the second embodiment is that the stacked semiconductor package structure 5 has a second chip 42 , and the second chip 42 Adhesive on the intermediary element 34 , and the support glue 38 and the bumps 35 are located on the top surface of the second chip 42 . Moreover, in this embodiment, the intermediary element 34 is a spacer without signal transmission function.

The difference between the manufacturing method of the stacked semiconductor package structure 5 and the method of manufacturing the stacked semiconductor package structure 3 of the second embodiment (FIG. 5) is that after the step S503 shown in FIG. 5, a The step of attaching a second chip 42 on the interposer 34 . And the support gel 38 in step S504 shown in FIG. 5 is directly formed and adhered to the top surface of the second chip 42, and the bumps 35 in step S505 shown in FIG. 5 are directly formed and attached to the the top surface of the second chip 42 .

Claims (10)

1. stack type semiconductor packaging structure, it includes: one first substrate, semiconductor element, some first leads, one second substrate and adhesive materials, wherein said first substrate has a first surface and a second surface; Described semiconductor element is positioned at the first surface of described first substrate, and is electrically connected to the first surface of described first substrate; Described second substrate has a first surface and a second surface; It is characterized in that: stack type semiconductor packaging structure also includes several projections, these projections are positioned at the top of described semiconductor element, these first leads are used for these projections are electrically connected to the first surface of described first substrate, and these projections contact with the second surface of described second substrate; And described adhesive material is used for coating the second surface of the first surface of described first substrate, described semiconductor element, described projection, described first lead and described second substrate.

2. stack type semiconductor packaging structure as claimed in claim 1 is characterized in that: described semiconductor element is a chip, and described semiconductor element is with on the first surface that covers crystal type and be attached to described first substrate, and these projections are positioned on the described chip.

3. stack type semiconductor packaging structure as claimed in claim 1, it is characterized in that: described stack type semiconductor packaging structure also includes a medium element, and described semiconductor element is one first chip, described semiconductor element attaches on the first surface of described first substrate, and utilize some second leads to be electrically connected to the first surface of described first substrate, described medium element attaches on the described semiconductor element, these projections are positioned on the described medium element, and described medium element is one not have the sept of electrical functionality or for another chip.

4. stack type semiconductor packaging structure as claimed in claim 1, it is characterized in that: described stack type semiconductor packaging structure also includes a sept and one second chip, and described semiconductor element is one first chip, described semiconductor element attaches on the first surface of described first substrate, and utilize some second leads to be electrically connected to the first surface of described first substrate, described sept attaches on the described semiconductor element, described second chip attaches on the described sept, and these projections are positioned on described second chip.

5. stack type semiconductor packaging structure as claimed in claim 1, it is characterized in that: the first surface of described second substrate has several first weld pads, the second surface of described second substrate has several second weld pads, these projections connect these second weld pads, described stack type semiconductor packaging structure also includes several soldered balls and a support adhesive member, these soldered balls are positioned at the second surface of described first substrate, and described support adhesive member is positioned on the second surface of described second substrate.

6. the manufacture method of a stack type semiconductor packaging structure, it includes: step a provides one first substrate, and described first substrate has a first surface and a second surface; Step b is the first surface that semiconductor element is attached to described first substrate, and described semiconductor element electric is connected to the first surface of described first substrate; It is characterized in that: the manufacture method of described stack type semiconductor packaging structure also includes step c to step g, and wherein step c forms several projections above described semiconductor element; Steps d is to form some first leads to be used for these projections are electrically connected to the first surface of described first substrate; Step e provides one second substrate, and described second substrate has a first surface and a second surface; Step f is arranged at described second substrate on these projections, makes these projections touch the second surface of described second substrate; Reaching step g is to utilize an adhesive material, in order to the second surface of the first surface that coats described first substrate, described semiconductor element, these projections, these first leads and described second substrate.

7. the manufacture method of stack type semiconductor packaging structure as claimed in claim 6, it is characterized in that: at the semiconductor element described in the step b is a chip, described semiconductor element is with on the first surface that covers crystal type and be attached to described first substrate, and these projections in step c are formed on the semiconductor element.

8. the manufacture method of stack type semiconductor packaging structure as claimed in claim 6, it is characterized in that: after step b, also include one a medium element attached to step on the described semiconductor element, and these projections in step c are formed on the described medium element, and described medium element is one not have the sept of electrical functionality or for another chip.

9. the manufacture method of stack type semiconductor packaging structure as claimed in claim 6, it is characterized in that: after step b, also include one a sept attached to step on the described semiconductor element, and one attach to step on the described sept with one second chip, and these projections in step c are formed on described second chip.

10. the manufacture method of stack type semiconductor packaging structure as claimed in claim 6, it is characterized in that: after step b, also include a step that above described semiconductor element, forms a support adhesive member, and a second surface at described first substrate forms the step of several soldered balls.

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