CN101071981B - Step-up DC/DC converter - Google Patents

Abstract

The boost DC/DC converter of the present invention includes a shielding circuit, a switching boost circuit, a Pulse Width Modulation (PFM) circuit and an AND gate. The shielding circuit is used for outputting a shielding signal according to the magnitude of the load current. The duty cycle of the mask signal will vary with the load current. The invention can enable the system to be selectively operated in a Pulse Width Modulation (PWM) mode, a Pulse Frequency Modulation (PFM) mode and a mixed Pulse shielding mode through the shielding signal corresponding to the load current when the system is in light load, medium load and heavy load so as to achieve the aim of optimizing the system efficiency.

Description

Boost DC/DC Converter

technical field

The present invention relates to a step-up DC/DC converter (DC/DC converter), and in particular to a step-up DC/DC converter using pulse modulation technology.

Background technique

In the power conversion system, when the load changes, the accompanying power conversion efficiency will change. Therefore, when the system is fully loaded or there is a huge load change, we still hope that the system at this time can provide high-efficiency and stable power conversion. . As far as the application level is concerned, electronic products such as processors, random access memories, displays, and mobile phones are not fully loaded at all times, especially mobile communication products such as mobile phones are often on standby to save power. mode, so a power conversion system that can provide high efficiency under any load condition is very important.

FIG. 1 is a schematic circuit diagram of a known step-up DC/DC converter 100. In the case where only the pulse width modulation mode is used, the converter 100 includes a switching boost circuit 110, a pulse width modulation circuit 120 and a load 130. . The switching boost circuit 110 includes an inductor 111 , a diode 112 , a capacitor 113 , and a power transistor 114 . The conduction or non-conduction of the power transistor 114 is switched by means of pulse wave modulation (PWM). When the power transistor 114 is turned on, the diode 112 is reverse biased, and the electric energy from the input voltage V _in1 is stored in the inductor 111 , and the electric energy of the load 130 is provided by the capacitor 113 . When the power transistor 114 is turned off, the diode 112 is forward biased, and the capacitor 113 and the load 130 absorb the power provided by the input voltage V _in1 and the inductor 111 , thus making V _out1 >V _in1 .

The PWM circuit 120 is composed of a control feedback circuit, including an error amplifier 121 , a triangle wave generator 122 , a PWM comparator 123 and a driver 124 . The output _voltage V _out1 of _{the switching} booster circuit ₁₁₀ passes through the error amplifier _{121 and} The reference voltage V _ref1 is compared, and the PWM comparator 123 receives the output signal of the error amplifier 121 and compares it with the output signal of the triangular wave generator 122 to generate the PWM signal PWM_CK. Then the driver 124 amplifies the PWM signal PWM_CK and drives the power transistor 114 .

Please refer to FIG. 2, which is a relationship diagram between the load current and the system efficiency of the step-up DC/DC converter 100 in FIG. 2 shows that the system efficiency of the boost DC/DC converter 100 is lower when the load current I _L1 is small (light load) than when the load current I _{L1 is} large (heavy load). This is because the pulse width modulation is controlled by a fixed frequency, and the power transistor 114 is still switching at the same frequency as the heavy load even under light load, thus dissipating too much unnecessary energy on the power transistor 114 Switching power increases the overall input power loss and reduces system efficiency, so it is necessary to design a step-up DC/DC converter that can improve system efficiency.

Contents of the invention

The purpose of the present invention is to provide a step-up DC/DC converter, which can enable the system to select the pulse width of the system through the shielding signal corresponding to the load current when the system is under light load, medium load and heavy load. In modulation, pulse frequency modulation and hybrid pulse shielding modes, this boost DC/DC converter can optimize the system efficiency to improve the system efficiency deviation of the known boost DC/DC converter at light load. low case.

In order to achieve the above and other objectives, the present invention proposes a step-up DC/DC converter, including a switching boost circuit, a pulse width modulation circuit, a shielding circuit and an AND gate. The switching boost circuit is used to receive an input voltage and provide an output voltage according to a control signal, wherein the output voltage is greater than the input voltage. The pulse width modulation circuit is used for outputting a pulse width modulation signal according to the output voltage and the reference voltage. The masking circuit is used to output a masking signal according to the magnitude of the load current of the step-up DC/DC converter of the present invention. The AND gate is used to receive the pulse width modulation signal and shielding signal and output the control signal, and the duty period of the shielding signal will change with the load current. The shielding circuit includes a load detector and a shielding signal generator. The load detector is used to output a load signal according to the load current, and the mask signal generator is used to generate a mask signal according to the load signal.

In one embodiment, the above step-up DC/DC converter further includes a driver and a voltage divider circuit, the driver can amplify the control signal of the AND gate and output it to the switching boost circuit. The voltage divider circuit includes a first resistor and a second resistor, wherein the first resistor is electrically connected to the output voltage and the second resistor is connected to the first resistor with a first end and grounded with its second end, and the first resistor The junction of the resistor and the second resistor is also electrically connected to the pulse width modulation circuit. The voltage dividing circuit can reduce the output voltage of the switching boost circuit by a preset ratio and then output it to the pulse width modulation circuit.

In one embodiment of the above step-up DC/DC converter, the switching boost circuit includes an inductor, a diode, a capacitor, and a switch. The inductor is electrically connected to the input voltage, the anode of the diode is electrically connected to the inductor, the first end of the capacitor is electrically connected to the cathode of the diode and the output voltage and its second end is grounded, and the first end of the switch is electrically connected to the inductor between the switch and the anode of the diode and the second terminal is grounded, and the first terminal and the second terminal of the switch are turned on or off according to the control signal. In one embodiment, the switch is an NMOS (n-channel Metal-Oxide-Semiconductor) transistor, and receives a control signal through its gate.

The pulse width modulation circuit includes an error amplifier, a triangle wave generator, and a comparator. The error amplifier receives a reference voltage at its first input terminal, and electrically connects the divided voltage of the output voltage with its second input terminal, and then amplifies the voltage from the first input terminal to the second input terminal and outputs it. The triangular wave generator is used to output a triangular wave, and then the comparator outputs a PWM signal according to the comparison result of the triangular wave and the output voltage of the error amplifier. Wherein, when the voltage of the triangular wave is greater than the output voltage of the error amplifier, the comparator will output a logic high potential, otherwise the comparator will output a logic low potential.

In one embodiment of the above step-up DC/DC converter, the load signal can be a voltage signal, and the load signal is an increasing function of the load current. Furthermore, the shielding signal generator also includes a delay chain and a buffer, wherein the delay chain can generate a digital signal according to the load signal and the frequency signal. The register can capture digital signals at regular intervals, and generate shielding signals according to the captured digital signals.

In one embodiment of the above step-up DC/DC converter, the above register is a parallel in/serial out register.

In one embodiment of the above step-up DC/DC converter, the delay chain includes a plurality of delay units, wherein each delay unit receives a load signal. The first delay unit delays the frequency signal for a preset time and outputs it, and the i-th delay unit delays the output of the i-1th delay unit for a preset time, where i is an integer greater than one. The digital signal is a collection of the outputs of the above delay units, and the preset time is a decreasing function of the load current.

In one embodiment of the above step-up DC/DC converter, each delay unit resets the output of the delay unit periodically according to the reset signal. In addition, among the digital signals captured by the register, the number of bits with a value of 1 is an increasing function of the load current. In addition, the duty cycle of the mask signal is an increasing function of the number of bits whose value is 1 among the digital signals captured by the register. If the number of bits with a value of 1 in the digital signal captured by the register is less than a default value, the register generates a mask signal by means of pulse frequency modulation.

In the step-up DC/DC converter of the present invention, when the system is under heavy load, the pulse width modulation mode is adopted; when the system is under light load, the pulse frequency modulation mode is adopted; when the system load is judged not to be heavy When the load or light load is medium load, the system adopts the hybrid pulse shielding mode. That is to say, the step-up DC/DC converter of the present invention can determine whether the shielding mode of the signal is pulse width modulation, pulse frequency modulation or mixed pulse wave shielding mode according to the magnitude of the load current. That is to say, no matter when the system is from heavy load to light load, the switching frequency of the power transistor can be adjusted by shielding the signal, so as to reduce unnecessary power loss on the power transistor and achieve the purpose of improving the power conversion efficiency.

In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are specifically cited below and described in detail with accompanying drawings.

Description of drawings

FIG. 1 is a known step-up DC/DC converter.

FIG. 2 is a relationship diagram between load and efficiency of a known step-up DC/DC converter.

FIG. 3 is a schematic diagram of a step-up DC/DC converter according to an embodiment of the present invention.

FIG. 4 is a schematic diagram of shielding signals in an embodiment of the present invention.

FIG. 5 is an internal structure diagram of a masking signal generator according to an embodiment of the present invention.

FIG. 6 is a schematic diagram of the operating principle of the shielding signal generator according to an embodiment of the present invention.

FIG. 7 is a diagram showing the relationship between a digital signal and a load current according to an embodiment of the present invention.

FIG. 8 is a schematic diagram of the operation of an AND gate according to an embodiment of the present invention.

FIG. 9 is a schematic diagram of the efficiencies of the PWM mode, the Pulse Frequency Modulation mode and the mixed pulse wave shielding mode according to an embodiment of the present invention.

Description of main component marking

100, 300: Boost DC/DC Converter

110, 310: switchable boost circuit

111, 311: Inductor

112, 312: diode

113, 313: Capacitor

114: power transistor

314: switch

130, 380: load

120, 320: Pulse width modulation circuit

121, 321: Error amplifier

122, 322: triangle wave generator

123: PWM comparator

323: Comparator

124, 360: drive

330: shielding circuit

331: Load Detector

332: shielding signal generator

3321: delay chain

3322: buffer

340: AND gate

350: Voltage divider circuit

R ₁ , R ₃ , R ₂ , R ₄ : Resistors

PWM_CK: pulse width modulation signal

DU ₁ ~ DU _n : delay unit

D ₁ ~ D ₅ : digital signal

S _Mask : Shield signal

I _L1 , I _L3 , I _L31 , I _L32 , I _L33 , I _L34 , I _L35 : load current

S _C , d(t): control signal

S _L : load signal

Q: frequency signal

V _in1 , V _in3 : Input voltage

V _out1 , V _out3 : output voltage

V _ref1 , V _ref3 : Reference voltage

T _L : Retrieval time

T _R ; reset time

Detailed ways

The following is an embodiment of the present invention, please refer to FIG. 3 . 3 is a step-up DC/DC converter 300 according to an embodiment of the present invention, which includes a switching boost circuit 310, a pulse width modulation circuit 320, a shielding circuit 330, an AND gate 340, a voltage divider circuit 350, and Drive 360.

The switching boost circuit 310 can provide an output voltage V _out3 according to the input voltage V _in3 according to the control signal S _C , and the output voltage V _out3 is greater than the input voltage V _in3 . Furthermore, the pulse width modulation circuit 320 can output the pulse width modulation signal PWM_CK according to the divided voltage of the output voltage V _out3 (V _out3 ×R ₄ /(R ₃ +R ₄ )) and the reference voltage V _ref3 . The masking circuit 330 can output a masking signal S _Mask according to the load current I _L3 . The AND gate 340 can receive the PWM signal PWM_CK and the mask signal S _Mask and provide the control signal d(t).

In this embodiment, the switching boost circuit 310 includes an inductor 311 , a diode 312 , a capacitor 313 and a switch 314 . The inductor 311 is electrically connected to the input voltage V _in3 , the anode of the diode 312 is electrically connected to the inductor 311 , and the first end of the capacitor 313 is electrically connected to the cathode of the diode 312 and the output voltage V _out3 , and its second end is grounded. The first end of the switch 314 is electrically connected between the inductor 311 and the anode of the diode 312, and its second end is grounded, and the first end of the switch 314 is turned on or off according to the received control signal S _C with the second end. In this embodiment, the switch 314 is an NMOS transistor (n-channel metal oxide semiconductor field effect transistor), whose gate receives the control signal S _C . Since the operation of the switching boost circuit 310 is similar to that of the switching boost circuit 110 in FIG. 1 , details are not described here.

Furthermore, the pulse width modulation circuit 320 in the embodiment includes an error amplifier 321 , a triangular wave generator 322 and a comparator 323 . The error amplifier 321 receives the reference voltage V _ref3 at the first input end, and electrically connects the second input end to the divided voltage of the output voltage V _out3 , and then amplifies the error voltage of the divided voltage between V _ref3 and V _out3 output. The triangular wave generator 322 is used to output a triangular wave, and then the comparator 323 outputs a pulse width modulation signal PWM CK according to the comparison result between the triangular wave and the output of the error amplifier 321 . Wherein, when the voltage of the triangular wave is greater than the output voltage of the error amplifier, the comparator will output a logic high potential, otherwise the comparator will output a logic low potential, and vice versa.

The shielding circuit 330 in this embodiment includes a load detector 331 and a shielding signal generator 332, wherein the load detector 331 detects the load current I _L3 and outputs a corresponding load signal S _L , in this implementation, the load signal S _L is a voltage and its value will become larger as the load current I _L3 increases. The mask signal generator 332 outputs a corresponding mask signal S _Mask according to the value of the load signal _SL .

The boost DC/DC converter 300 of this embodiment further includes a voltage dividing circuit 350 and a driver 360 . The voltage divider circuit 350 includes a first resistor R ₃ and a second resistor R ₄ and is used to multiply the output voltage V _out3 by a preset ratio R ₄ /(R ₃ +R ₄ ) so that V _out3 ×R ₄ / The magnitude of (R ₃ +R ₄ ) is similar to the magnitude of the reference voltage V _ref3 to be output to the comparator 323 . In the voltage divider circuit 350 , the resistor R ₃ is electrically connected to the output voltage V _out3 , the resistor R ₄ is electrically connected to the first resistor R ₃ with a first end, and grounded with a second end. The junction of the resistor R ₃ and the resistor R ₄ is also electrically connected to the pulse width modulation circuit 320 . As in this embodiment, when the output voltage V _out3 is very different from the reference voltage V _ref3 , the voltage divider circuit 350 can divide the output voltage V _out3 so that the divided voltage of the output voltage V _out3 is the same as the reference voltage V _ref3 The values of the two have little difference to be input to the error amplifier 321 . If the output voltage V _out3 is close to the reference voltage V _ref3 , the voltage dividing circuit 350 can be omitted. The driver 360 can amplify the control signal d(t) from the AND gate 340 into a control signal S _C and output it to the switching boost circuit 310 .

FIG. 4 is a schematic diagram of shielding signals in this embodiment. The period of the masking signal S _Mask is T ₁ +T ₂ , where T ₁ is the duty period. The duty cycle _T1 is determined according to the magnitude of the load current I _L3 , that is, when the load current I _L3 increases, the duty cycle _T1 of the mask signal S _Mask will also increase accordingly.

Please refer to FIG. 5 , which is an internal structure diagram of the masking signal generator 332 . The shielding signal generator 332 includes a delay chain 3321 and a buffer ₃₃₂₂ , wherein the delay chain 3321 generates digital signals D ₁ -D _n (wherein n is integer greater than 1). In the following embodiments, it is assumed that N=5 and the register 3322 can regularly capture digital signals D ₁ -D ₅ , and the register 3322 generates a mask signal S _Mask according to the captured digital signals D ₁ -D ₅ to select the current The mode of the masking signal S _Mask required by the system is one of pulse width modulation, pulse frequency modulation or mixed pulse wave masking mode. The register 3322 in this embodiment is a parallel input/serial output register.

Please refer to FIG. 6 , which is a schematic diagram of the working principle of the shielding signal generator 332 . The above-mentioned delay chain 3321 includes 5 delay units DU ₁ ~ DU ₅ , and each delay unit DU ₁ ~ DU ₅ receives the load signal _SL , wherein the first delay unit DU ₁ delays the frequency signal Q by a preset time The output after T _d is D ₁ . And the i-th delay unit DU _i delays the output D _{i-1 of the i-1th} delay unit for a preset time T _d and then outputs it as D _i , for example, the output D ₃ of DU ₃ is delayed compared to the output D ₂ of DU ₂ The preset time T _d , wherein i is an integer greater than one. In this embodiment, the characteristic of the delay unit is that the delay preset time T _d is inversely proportional to the magnitude of the load signal _SL . Therefore, when the load current is large, the load signal _SL also becomes large, and at the same time, the preset time T _d is small. The register 3322 will capture the digital signals D ₁ -D ₅ at the capture time _TL , and when the register 3322 captures, the number of digital signals D ₁ -D ₅ at high potentials will increase. For example, if there are 5 high potentials, the digital signals D ₁ -D ₅ are (11111). Conversely, when the load current is small, the load signal S _L will also be small, and the preset time T _d will be long. When the register 3322 captures, the number of digital signals D ₁ -D ₅ at logic high potentials will be small. , for example, there are only three high potentials, and the digital signals D ₁ -D ₅ are (11100). During the reset time _TR , each of the delay units DU ₁ -DU ₅ is triggered by a reset signal and the output of the reset delay units DU ₁ -DU ₅ is logic low.

Next, FIG. 7 is a relationship diagram between the digital signals D ₁ -D ₅ and the load current I _L3 in this embodiment. When the digital signals (D ₁ -D ₅ ) are (00000) or (10000), the load current is less than I _L32 at this time, which means light load, and the duty cycle of the mask signal S _Mask output by the register 3322 will be smaller, and at this time The masking signal S _Mask makes the boost DC/DC converter 300 operate in the pulse frequency modulation mode. When the digital signal (D ₁ ˜D ₅ ) is (11111), the load current is greater than I _L35 at this time, which means a heavy load, and the duty cycle of the mask signal S _Mask output by the buffer 3322 will be larger, and at this time, the mask signal S _Mask The boost DC/DC converter 300 will operate in the PWM mode. And when the digital signal (D ₁ ˜D ₅ ) is (11000), (11100) or (11110), the load current is between I _L32 and I _L35 at this time, which is medium load, and the shielding signal S output by the register 3322 is The duty cycle of _{the Mask} is between the above two modes, that is, at this time, the mask signal S _Mask makes the boost DC/DC converter 300 operate in the hybrid pulse wave masking mode.

In the hybrid pulse masking mode and the PWM mode, the duty cycle of the masking signal S _Mask is proportional to the number of high potential bits of the digital signals (D ₁ -D ₅ ). For example, when the digital signals (D ₁ ˜D ₅ ) are (11000), the number of bits at logic high potential is 2, and the duty cycle of the mask signal S _Mask is 2/5=40%. On the other hand, when the digital signal (D ₁ ˜D ₅ ) is (11100), the number of bits in logic high potential is 3, and the duty cycle of the mask signal S _Mask is 3/5=60%, and the rest are analogized.

FIG. 8 is a schematic diagram of the operation of the AND gate 340 . When the duty cycle of the shielding signal S _Mask is larger, the pulse number of the control signal d(t) of the AND gate 340 will also increase. As shown in FIG. 8, when the load current I _L32 <I _L33 , the AND corresponding to I _L33 The pulse number of the control signal d(t) of the gate 340 will be more than that of _IL32 , that is to say, the pulse number of the control signal d(t) corresponding to _IL32 is less, so that the switch corresponding to the switch 314 in FIG. 3 The number of times is less, and thus the switching loss of the switch 314 can be reduced to increase the system efficiency.

To sum up, the load detector 331 can detect the value of the load current I _L3 and output the corresponding load signal S _L , then the mask signal generator will provide the mask signal S _Mask according to the load signal S _L , and then the AND gate 340 The control signal d(t) is provided according to the mask signal S _Mask and the pulse modulation signal PWM_CK. Afterwards, the driver 360 outputs the amplified control signal S _C to the switch 314 of the switching boost circuit 310 . Thereby, the step-up DC/DC converter of this embodiment can be selected to operate in the PWM mode, the Pulse Frequency Modulation mode or the Hybrid pulse shielding mode individually according to the magnitude of the load current.

FIG. 9 is a comparison diagram of efficiencies among the PWM mode, the pulse frequency modulation mode and the mixed pulse wave shielding mode in this embodiment. Taking the step-up DC/DC converter 300 used in mobile phones as an example, when it is under heavy load, such as when the mobile phone is in call mode, it uses pulse width modulation mode, and when it is under light load, such as power saving mode, it uses pulse width modulation Frequency modulation mode to reduce the number of switching times, so as to avoid the loss of frequent switching and reduce the power conversion efficiency. At medium load, the hybrid pulse shielding mode is used, so that the power conversion of the system can be maintained at high efficiency, as shown in Figure 9. It can be seen from the above description that the present invention can individually make the system operate in the pulse frequency modulation, mixed pulse masking mode or pulse width modulation mode under light load, medium load and heavy load, so that the system can maintain the efficient state.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art may make some modifications and improvements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be defined by the claims.

Claims (16)

1. A step-up DC/DC converter, characterized in that it comprises: The switchable boost circuit receives an input voltage and provides an output voltage according to a control signal, and the output voltage is greater than the input voltage; a pulse width modulation circuit, outputting a pulse width modulation signal according to the output voltage and the reference voltage; a shielding circuit, outputting a shielding signal according to the load current of the step-up DC/DC converter, the duty cycle of the shielding signal changes with the load current; and an AND gate, receiving the pulse width modulation signal and the masking signal, and outputting the control signal, Wherein the shielding circuit includes: a load detector that outputs a load signal according to the load current; and The shielding signal generator generates the shielding signal according to the load signal. 2. The step-up DC/DC converter according to claim 1, further comprising: The voltage dividing circuit reduces the output voltage by a preset ratio and outputs it to the pulse width modulation circuit. 3. The step-up DC/DC converter according to claim 2, wherein the voltage dividing circuit comprises: a first resistor electrically connected to the output voltage; and a second resistor electrically connected to the first resistor with a first end and grounded with a second end; Wherein the junction of the first resistor and the second resistor is also electrically connected to the pulse width modulation circuit. 4. The step-up DC/DC converter according to claim 1, further comprising: The driver amplifies the control signal and outputs it to the switching boost circuit. 5. The step-up DC/DC converter according to claim 1, wherein the switching boost circuit comprises: an inductor electrically connected to the input voltage; a diode electrically connected to the inductor with an anode; a capacitor electrically connected to the cathode of the diode and the output voltage with a first terminal and grounded with a second terminal; and The switch is electrically connected between the inductor and the anode of the diode with the first end and grounded with the second end, and the first end and the second end of the switch are turned on or off according to the control signal. 6. The step-up DC/DC converter according to claim 5, wherein the switch is an NMOS transistor, and the gate receives the control signal. 7. The step-up DC/DC converter according to claim 1, wherein the pulse width modulation circuit comprises: The error amplifier receives the reference voltage with the first input terminal, electrically connects the output voltage with the second input terminal, amplifies the voltage from the first input terminal to the second input terminal, and outputs it; a triangular wave generator that outputs a triangular wave; and The comparator outputs the pulse width modulation signal according to the comparison result between the triangular wave and the output voltage of the error amplifier. 8. The step-up DC/DC converter according to claim 7, wherein if the voltage of the triangular wave is greater than the output voltage of the error amplifier, the comparator outputs a logic high potential, otherwise the comparator outputs a logic low potential. 9. The step-up DC/DC converter according to claim 1, wherein the load signal is a voltage signal, and the load signal is an increasing function of the load current. 10. The step-up DC/DC converter according to claim 1, wherein the shielding signal generator comprises: a delay chain that generates a digital signal based on the load signal and the frequency signal; and The register acquires the digital signal regularly, and generates the mask signal according to the acquired digital signal. 11. The step-up DC/DC converter according to claim 10, wherein the register is a parallel input/serial output register. 12. The step-up DC/DC converter according to claim 10, wherein the delay chain comprises: A plurality of delay units, each of the above-mentioned plurality of delay units receives the load signal, wherein the first delay unit delays the frequency signal for a preset time and outputs it, and the i-th delay unit outputs the load signal of the i-1-th delay unit The output is delayed by the preset time, i is an integer greater than 1, the digital signal is a set of the outputs of the plurality of delay units, and the preset time is a decreasing function of the load current. 13. The step-up DC/DC converter according to claim 12, wherein each of the plurality of delay units resets the output of the delay unit periodically according to a reset signal. 14. The step-up DC/DC converter according to claim 10, wherein in the digital signal captured by the register, the number of bits with a value of 1 is an increasing function of the load current. 15. The step-up DC/DC converter according to claim 10, wherein the duty cycle of the mask signal is an increasing function of the number of bits whose value is 1 among the digital signals captured by the register. 16. The step-up DC/DC converter according to claim 15, wherein if the number of bits with a value of 1 in the digital signal captured by the register is less than a default value, then the register is The masking signal is generated by pulse frequency modulation.

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