CN101067778A - Interface circuit and method with high access efficiency - Google Patents

Abstract

An interface circuit and method for high access efficiency is disclosed, the interface circuit including a plurality of bidirectional buffers and logic circuitry, responsive to a read request from a system component, configured to determine whether requested data is currently located in the bidirectional buffers and designated to be written from the bidirectional buffers to an external memory, wherein the logic circuitry is further configured to supply the data from the bidirectional buffers to the requesting system component without first writing the data to the external memory, thereby improving data access efficiency to the memory.

Description

Interface circuit and method with high access efficiency

technical field

The invention relates to a bus arbitration of a computer system, in particular to a memory interface circuit and method with high access efficiency.

Background technique

A memory controller is designed to interface various types of memory on behalf of one or more requestors (eg, processors, peripheral devices, etc.). Typically, a memory controller is used to provide certain latency and bandwidth characteristics. It is often desirable to provide low-latency and high-band access to the memory. However, optimization for lower latency may reduce the frequency band. Likewise, optimization of boost frequency bands may result in increased latency. Therefore, designers of memory controllers often have to make a trade-off between low latency and high band characteristics.

The latency and bandwidth characteristics of the memory controller can be preselected. For example, a memory controller may be optimized to match processor accesses based on the memory controller's expected workload, with latency typically being the dominant characteristic. Other workloads may be frequency-band rather than latency-heavy. For example, in a network environment, a large number of data packets may be written to or read from memory. Of course the aforementioned accesses require low latency, but having a high frequency band may be more important than low latency, to ensure that packets can be written to or read from memory in a timely manner without missing packets, or without having to be interrupted by the use of flow control. Reduce the network packet transmission rate.

FIG. 1 is a block diagram of multiple devices on a system bus communicating with external memory in a prior art manner. For the sake of simplicity, and to better illustrate the inventive features of the present application (please refer to the comparative illustration of an inventive embodiment below), the marks and symbols for specific elements may be generalized. For example, in FIG. 1 , an "external interface" 10 coupled to an "external memory" 12 is shown. The external interface 10 may be a memory controller, or other devices for interfacing with the aforementioned memory 12 or a specially designed circuit.

The system bus 20 can be used to connect many devices, including a plurality of master devices 22 , 24 and 26 . In this case, the master device generally refers to a device that can obtain the driving control right of the system bus 20 . That is, a device that can take "mastership" of communications on the system bus at any time. For example, system bus 20 can couple to a variety of devices, including multiple processors, stand-alone processors, direct memory access (DMA) controllers, printer servers, and other devices. Any of the aforementioned devices may be responsible for controlling information placed on system bus 20 at any time. Arbitration logic, not shown, arbitrates control of the bus 20 so that only one device has master or control of the system bus at any time. This concept and its operation are existing and need not be stated here.

Each of the main control devices 22 , 24 and 26 may contact the external memory 12 for information from time to time. The bus interface 30 implemented in the logic circuit type of circuit AND/OR gate is used to interface the system bus 20 and the external memory 12, or as shown in FIG. 1, interface the system bus 20 and the external interface 10 . Therefore, information transmitted from the main control device 26 to the external memory 12 first passes through the bus interface 30 and then reaches the external memory 12 through the external interface 10 which may be a memory controller.

The communication between the bus interface 30 and the external memory can be improved through the effects of the buffers 40 and 45, and the buffers 40 and 45 are inserted into the bus interface 30 and the external memory 12 (or as shown in the embodiment figure, inserted between the bus 30 and the external interface 10). In known systems some of the buffers 40 act as read buffers. When sending data from the external memory 12 to a requesting master, the data is placed in the read buffer 40 . Then, when a master sends a request to “read” data from the external memory, the data is transferred from the external memory 12 to the bus interface 30 through the read buffer 40 . Likewise, when a master device issues a “write” command to write data from the system bus 20 to the external memory 12 , the data is first transmitted through the write buffer 45 . When multiple data items need to be read or written continuously in real time, using the buffers 40 and 45 can improve the speed of the above operations and data flow.

For example, consider the situation where the master device 22 issues three consecutive write commands to write data to the external memory 12 . In the absence of a buffer, the first data item would be written to the external memory 12 via the bus 30 , the external interface 10 , and finally the external memory 12 . After the data is written into the external memory 12, an acknowledgment instruction is sent back to the master control device 22, and after receiving the acknowledgment instruction, the master control device then initiates writing of the next data item. In contrast to the system using the write buffer 45, the master control device 22 can write all three data items to the buffer 45 consecutively at one time almost in real time. Afterwards, the external interface 10 and memory 12 will receive the data item. Writing data in this manner can greatly expand the data flow and allow the master device 22 to surrender the system bus 20 early, making the system bus 20 more visible to other master devices 22 coupled to the system bus 20. accessibility and usability. The same efficiency can also be obtained by using the read buffer 40 . Since this kind of system is also existing, it will not be described in detail here.

While the aforementioned circuits offer some performance and operational improvements, there are still a number of disadvantages. For example, consider the situation where the host device 22 issues three consecutive write commands to write various data items to the external memory. After issuing the command, the master 22 surrenders the bus 20 . It is also assumed that the master device 24 issues a data read request, and the address of the requested data corresponds to the address of one of the three data items just written by the master device 22 . In particular, assume that the system determines that the data requested by the main control device 24 is currently placed in a write buffer 45 . The address check logic circuit 50 is used to make this judgment, and sends a signal through the bus 30, commanding the main control device 24 to wait for this data (because it is not ready yet). The main control device 24 must wait until the data is written into the external memory from the corresponding write buffer 45 through the external interface 10, that is, the main control device 24 must wait before the data can be "validly" read, so the access The efficiency is really bad.

The foregoing is only an example of a specific situation, and further improvement in performance is still required for the existing system. Accordingly, there is a need for the foregoing and other performance enhancements to this existing system.

Contents of the invention

Certain objects, advantages and novel features of the present invention will be presented in the following description, and the present invention will be clear to those skilled in the relevant arts after reviewing the following, and can also learn the implementation of the present invention. The objects and advantages of the invention may be realized and obtained by means of the means particularly pointed out in the appended claims and in combination.

In order to achieve predetermined benefits and novel features, the present invention mainly points to an interface circuit and method with high access efficiency. The interface circuit includes a plurality of bi-directional buffers and logic configured, in response to a read request from a system element, to confirm whether requested data is currently placed in the bi-directional buffers and designated from the bidirectional buffer writes to an external memory, wherein the logic circuit is further configured to provide the data from the bidirectional buffer to the requesting system component without waiting for the data to be written to the external memory, thereby improving Data access efficiency of memory.

In order to make the above-mentioned objects, features and advantages of the present invention more comprehensible, preferred embodiments will be described in detail below together with the accompanying drawings.

Description of drawings

Figure 1 shows a block diagram of some components of a conventional system.

FIG. 2 , comparable to the system of FIG. 1 , is a block diagram showing certain components of a system according to an embodiment of the present invention.

FIG. 3 shows a block diagram of some components of an embodiment of the present invention.

FIG. 4 shows a block diagram of some components of an embodiment of the present invention.

FIG. 5 shows a flowchart of high-level operations of an embodiment of the present invention.

Detailed ways

Having summarized the various features of the invention, reference is now made to the detailed description of the invention as illustrated in the illustrations. The present invention will be described with reference to the relevant figures, but it is not intended to limit the present invention to the embodiments disclosed in the description. On the contrary, modifications and equivalents are also covered by the present invention if they are included in the spirit and scope of the invention defined by the appended claims.

It should be noted that the drawings listed herein are used to illustrate certain features and aspects of the embodiments of the present invention. From the description provided herein it will be apparent that various alternative embodiments and implementations can be implemented which are within the scope and spirit of the invention.

Referring to FIG. 2 , it shows a block diagram of an embodiment of the present invention. FIG. 2 particularly illustrates the components of a system that can highlight the features and aspects of the embodiments of the present invention more than the system of FIG. 1 . Like the external interface 10 and the system bus 20 of FIG. 1 , the embodiment of FIG. 2 includes an external interface 110 and a system bus 120 . Various system components, such as host devices 122 , 124 and 126 , may be coupled to the system bus 120 . A bus interface 130 is also shown.

As can be seen from the foregoing discussion, according to the embodiment of the present invention, the high-level functional operation of the bus interface 130 is similar to that of the bus interface 30 in FIG. 1 , and the internal components and logic circuits of the bus interface 130 may include some additional or different features . The central idea of the embodiments of the present invention is to introduce a bidirectional buffer 160 . In this regard, the embodiment of FIG. 2 includes a plurality of bidirectional buffers 160 for accommodating bidirectional communication between the bus interface 130 and the external interface 110 .

From a high-level operational point of view, bi-directional buffer 160 adequately provides read and write operations in a manner similar to read buffer 40 and write buffer 45 of the embodiment of FIG. 1 . That is, when information is written from a master device to the external memory (via the external interface 110 ) via the bus interface 130 , the information is written (or registered) in the bi-directional buffer 160 . However, a significant improvement of the embodiment of FIG. 2 is that devices on the system bus 120 can read the data currently located in one of the buffers 160 in real time (that is, it can be read while writing to the external memory. ). In this regard, address checking logic 200 is coupled to bidirectional buffer 160 and bus interface 130 .

To illustrate this operation, consider the example where master control device 122 sends three consecutive data items to be written to external memory. The data items are written into three bi-directional buffers 160 through the bus interface 130 . Furthermore, after the main control device 122 hands over the system bus 122, the main control device 124 sends a request to read from a memory, and the read address corresponds to a first address, and the first address points to the memory written by the main control device 122. Enter one of the addresses to which three data items are to be written. The address check logic circuit 200 determines from the external memory address that the requested data is located in one of the buffers 160 . Different from the prior art, the present embodiment does not suspend (suspend) the read operation of the main control device 124 until the data is first written into the external memory, and the address check logic circuit 200 can configure the appropriate bidirectional buffer 160 to Allow data to be captured by the bus interface 130 in real time and forwarded to the requesting master control device 124 . This enables the bus interface 130 to satisfy the read request of the main control device 124 substantially in real time, and the main control device 124 can satisfy its read request without waiting for the data in the external memory to become valid. In addition to satisfying read requests in real-time (thus allowing the host device 124 to continue its processing operations), the present invention also eliminates the management operations and connections associated with the system bus 120 required to communicate with the host device 24 after the data has been written to the external memory. further arbitration.

The high-level structure and operation of an embodiment of the present invention have been described above, and more detailed implementation examples will be described here. As is known, most system synchronization is achieved using one or more clocks. Taking the system shown in FIG. 2 as an example, a system clock 172 is used to synchronize the communication on the system bus side, and a memory clock 174 is used to synchronize the communication with the external memory and the external interface 110 . Therefore, the bi-directional buffer 160 needs to be synchronized by an appropriate clock signal. In this embodiment, clock selection logic 180 is used to ensure that the proper clock signal is coupled to the proper bi-directional buffer 160 . Thus, in one embodiment, the clock selection logic 180 includes a system clock 172 and a memory clock 174 as inputs. The output of the clock selection logic circuit 180 is coupled to each buffer 160 . According to the consistent spirit of the embodiments of the present invention, the clock selection logic circuit 180 can be implemented in various ways.

In an embodiment as shown in FIG. 2 , the clock selection logic circuit 180 may be implemented using a plurality of multiplexers. In particular, multiplexers 182 in this embodiment are configured one-to-one with bidirectional buffer 160 such that the output of each multiplexer 182 is directly connected (or coupled) to A clock input of the bidirectional buffer 160 . The signals of system clock 172 and memory clock 174 may be directly connected (or coupled) to respective inputs of the multiplexer 182 . A multiplexer select input 184 is provided to control which clock signal (system clock 172 or memory clock 174 ) is selected by the multiplexer 182 . In the illustrated embodiment, a single multiplexer select input 184 is connected to the multiplexer select input of each of said multiplexers 182 .

In another embodiment (not specifically shown), the multiplexer select signal can be generated independently for each individual multiplexer. This embodiment allows simultaneous communication between certain buffers 160 and external interface 110 , and between other buffers 160 and bus interface 130 . Therefore, for communication between a buffer 160 and the external interface 110 , the multiplexer select signal line 184 is used to select the signal of the memory clock 174 as the synchronous clock for the associated buffer 160 . Likewise, the multiplex select signal 184 causes the associated multiplexer 182 to select the system clock 172 as the clock signal for the respective buffer 160 for communication between a buffer 160 and the bus interface 130 .

In the illustrated embodiment, buffer management logic 300 is shown as part of the bus interface 130 . Those skilled in the related art know that the buffer management logic circuit 300 can be separated from the buffer interface 130 . In terms of functionality broadly, the buffer management logic 300 is used to manage certain operational characteristics of the bi-directional buffer 160 . The operational features will be described in detail with reference to FIG. 4 . However, one of the operational features of the buffer management logic 300 includes the generation of the multiplexer select signal 184 used to control the multiplexing of the multiplexer 182. Multiplexer Select Input. Likewise, in embodiments including clock selection logic 180 (not combining multiplexer 182 ), buffer management logic 300 may include related logic to perform an operational function similarly. That is, the multiplexer selection signal is not generated in this embodiment, but other signals can be generated to control or cooperate with the clock selection logic circuit 180 to ensure the synchronization between the buffer 160 and the system and memory clocks.

After describing the high-level structure and functional operation of an embodiment of the present invention, please refer to FIG. 3 , which shows a block diagram of features of the address checking logic circuit 200 related to an embodiment of the present invention. As described with respect to FIG. 2, the address check logic 200 is configured to perform various operations, including checking data currently stored in the bidirectional buffer to determine whether data being read or written currently exists in the buffer 160. In the example shown in FIG. 2, a master device issues a read request, and the address check logic circuit 200 determines whether the buffer 160 contains data intended to be written to the requested memory location. In this case, address checking logic 200 operates in conjunction with buffer management logic 300 to immediately direct data from the appropriate data buffer 160 to bus interface 130 . Of course, the data will remain in the buffer 160 and eventually be written to the designated external memory location. Likewise, in addition to a read request, a master device issues a write request to an external memory location and one of the buffers 160 with data assigned to the memory address, then the address checking logic 200 , and cooperate with the buffer management logic circuit 300 to overwrite the existing value in the sending buffer 160 . This eliminates consecutive writes to the same external memory location.

Consistent with the description of FIG. 3 , address checking logic 200 may include logic 210 configured to communicate with or interface with buffer management logic 300 . The illustration of this type of communication or interface has already been described and will not be repeated here. In addition, based on the design goals and various implementations of the embodiments of the present invention, those skilled in the relevant art may recognize other features and aspects of this interface. Consistent with the previous examples, the address check logic 200 may also include a write management logic 220 to manage write operations (ie, operations in which a master device writes data to an external memory location). Likewise, the address check logic 200 may include a read management logic 230 to manage read operations (ie, data read from the external memory requested by the host device). In a write operation, the write management logic circuit 220 may have a second judgment logic circuit 222 for judging whether a buffer 160 currently contains data pointing to the memory address that was specified in the write command is confirmed. If not, the write management logic 220 may include a write logic 224 for writing the current data into an available buffer. Otherwise, if a buffer 160 currently has data assigned to an acknowledgment address, the write management logic 220 may have an overwrite logic 226 to overwrite the contents of the buffer with the current data, thereby enabling the desired The number of buffers and the communication between the buffer 160 and the external interface 110 are minimized.

Likewise, in a read operation, the address check logic circuit 200 may include a first decision logic circuit 232 , a read logic circuit 234 and a capture logic circuit 236 . The first determination logic circuit 232 determines whether a buffer 160 currently has data reserved for a memory address to be read. If so, the read logic 234 is used to configure the appropriate buffers to provide data directly to the bus interface 130 (effectively allowing data to be read directly from the outgoing buffer without first being written to external memory). Otherwise, the fetch logic 236 may be used to fetch data from the external memory 120 if no buffer currently has data reserved for the requested memory address, e.g. Multiple bi-directional buffers 160 for reading data.

After describing some high-level features of the address check logic circuit 200 , please refer to FIG. 4 , which shows a block diagram of some high-level features of the buffer management logic circuit 300 according to an embodiment of the present invention. As the address checking logic 200 includes logic in communication with the buffer management logic, the buffer management logic 300 likewise includes a second communication/interface logic 310 in communication with the address checking logic or interface (contact). Depending on the specific implementation, the logic circuit can be in the form of hardware or software, or a combination of both. Those skilled in the art will understand various suitable implementations, so details are not repeated here. In the illustrated embodiment, the buffer management logic circuit 300 may also include a detection logic circuit 320 for detecting when a master device issues a read request or a write request assigned to the external memory. Any operation to the external memory is either a read or a write, meaning that the buffer 160 will be used anyway, so the buffer management logic 300 and/or the address checking logic 200 can be used to speed up other operations. One of the operations is simply the synchronization of the buffer 160 to the appropriate system or signal clock. As described with respect to FIG. 2, the buffer management logic 300 may include a generation logic 330 for generating an appropriate control signal to the clock selection circuit. In one embodiment, this clock selection logic utilizes multiplexers, and the generation logic 330 can generate the appropriate multiplexer select signals.

Additionally, the buffer management logic 300 includes a management logic 340 configured to designate and delegate various buffers 160 . Regardless, the management described above includes delegating the direction of data for the respective buffer 160 as either outgoing or incoming (ie, to read or write the buffer as a given case). For example, when the bus interface 130 transfers data to one or more buffers 160 for writing to external memory, the buffers 160 are designated as "write buffers." Conversely, when data is returned from the external interface 110 and written into the buffer 160, the buffer 160 is assigned to be a "read buffer". It can be appreciated that there are many ways to implement this feature and operation within the buffer management logic 300 . Wherein, one way is through the implementation of the translation table 345. The items or information of the translation table 345 include a buffer number, a memory address or address range, and an indication of a current read or write operation for the memory address. indicators or markers. Regarding the number of buffers, in one embodiment, for example, eight buffers of 32 bytes are included, and the number of buffers can be from one to eight, so as to specify a specific buffer. It can be seen that the address checking buffer logic 200 can interface with the translation table 345 to determine whether the currently requested address is currently included in the configuration of the buffer. To further illustrate, consider the example of a device writing data from the system bus to an external memory. Before data is written into the external memory, it is assumed that data is written into the second buffer. Appropriate entries in the translation table 345 might include a line representing the number 2 with a second buffer, the associated external memory address corresponding to the second buffer, and an indication in the read/write column that the buffer is currently used as a write buffer An indication or marking of the device. If the bus interface 130 then initiates a read request to request information from a memory address, the address check logic circuit 200 can determine from the translation table 345 whether the requested memory address is included in the translation table. Based on the comparison, the address check logic circuit 200 can control the corresponding buffer representative number to immediately read data from the buffer to the bus interface 130, and then transmit the data to the requesting device.

It should be appreciated that what has been described above merely presents various embodiments for implementing the concepts and features of the present invention. Furthermore, a broad feature of the invention resides in the implementation of a bidirectional buffer (or a buffer that can be configured to operate in either the read or write direction), and its accompanying logic, that allows the specified Data of the external memory that is currently in a buffer is immediately read from the buffer to the bus interface 130 . This case also proposes a corresponding creative method.

In this regard, reference is made to FIG. 5, which shows a high-level operational flowchart of an embodiment of the present invention. According to this embodiment, a method for interfacing a system to a memory is provided. The method includes writing data to a bidirectional buffer disposed in an interface according to a command, the command instructs a device coupled to the system bus to write data to the memory (step 402). Thereafter, the method receives a request from a device coupled to the system bus to retrieve data from memory (step 404). The method then determines whether the requested data is currently stored or contained within the bi-directional buffer and awaits communication with the memory (step 406). Finally, the method retrieves the requested data from the bi-directional buffer to transmit the retrieved data to the requesting device without first waiting for the data to be written to the memory (step 408).

The foregoing is not intended to limit the invention exclusively to the stereotypes disclosed. Obvious modifications or variations of the present invention are possible in light of the above teachings. Furthermore, the disclosed embodiments were chosen or described in order to provide the best illustration of the principles of the invention, its practical application thereby enabling one skilled in the relevant art to utilize the invention in various embodiments and to perform various Vary to suit the particular use envisioned. All such modifications or changes are included in the scope defined by the scope of the patent application of the present invention, and shall prevail according to the breadth of the legally interpreted scope of the patent application.

Claims (10)

1. the interface circuit of a high access efficiency comprises:

A plurality of bidirectional buffers, each described bidirectional buffer have clock input;

A plurality of multiplexer circuits, wherein, described multiplexer circuit be provided as and described bidirectional buffer between man-to-man corresponding relation is arranged, make an output of each described multiplexer circuit be coupled to this clock input of this correspondence bidirectional buffer, one first input of each described multiplexer circuit is coupled to a memory clock signal, and one second input of each described multiplexer circuit is coupled to a clock signal of system; And

The buffer management logical circuit, be configured to give described multiplexer circuit in order to produce control signal, control signal is controlled each described multiplexer circuit independently and is exported the described bidirectional buffer of each correspondence to select this memory clock signal or this clock signal of system.

2. the interface circuit of high access efficiency as claimed in claim 1, wherein, this buffer management logical circuit is configured to give described multiplexer circuit in order to produce this control signal, make when described multiplexer circuit is configured to interface communication when a described bidirectional buffer and an external memory storage, select this memory clock signal, and described multiplexer circuit is configured to select this system's body clock signal in order to when described bidirectional buffer is communicated by letter with a system bus interface.

3. the interface circuit of high access efficiency as claimed in claim 1, more comprise the address check logical circuit, response is from the request of reading of a system element, this address check logical circuit is configured in order to confirm whether designated whether requested data be arranged in described bidirectional buffer at present and will be written into an external memory storage from described bidirectional buffer, wherein, this address check logical circuit comprises:

One first decision logic circuit, whether one of them has the data that are designated to a storage address at present and will be read to judge described bidirectional buffer;

Read logical circuit, be configured to one and match bidirectional buffer, allow these data directly to be read by this effectively, and need not to be write to earlier this external memory storage to provide these data directly to a bus interface; And

The acquisition logical circuit is when present no impact damper has the data that are assigned to the memory location of asking, in order to from this external memory storage acquisition data.

4. the interface circuit of high access efficiency as claimed in claim 3, wherein, this address check logical circuit more is configured in order to control described bidirectional buffer, to provide requested data to this system element that sends the request of reading, need not earlier these data to be write this external memory storage, wherein, this address check logical circuit comprise write the management logic circuit in order to the management write operation, wherein, in the write operation of this circuit, this system element writes data to this external memory storage, and this writes the management logic circuit and comprises:

One second decision logic circuit is judged whether described bidirectional buffer includes at present to be assigned to the data that write a storage address of confirming in the instruction;

Write logical circuit, when the present no datat of this second decision logic circuit judges includes at one of described bidirectional buffer, in order to write current data to an available buffer; And

Override logical circuit, when one of described bidirectional buffer has the data that are assigned to this affirmation address at present, override the content of described bidirectional buffer in order to use these current data.

5. the interface circuit of high access efficiency as claimed in claim 3, wherein, this buffer management logical circuit comprises:

One second communication logic glue connects this address check logical circuit in order to Jie;

Detect logical circuit, in order to detect the combination in any of the various information that following this system element sends:

This reads request; And

One is assigned to the instruction that writes of external memory storage;

Produce logical circuit, in order to produce described control signal; And

The management logic circuit, be configured to comprise a translation table, with the appointment of managing multiple impact damper and appoint, this translation table comprises buffering number, a storage address or an address realm, represents whether the current operation of this storage address is a sign of a read operation or a write operation

Wherein, this address check logical circuit is situated between and connects this translation table, judges whether a current address that is requested is included in described impact damper at present.

6. the interface circuit of a high access efficiency comprises:

A plurality of bidirectional buffers, each described bidirectional buffer have clock input;

One memory clock signal line carries a memory clock signal, with communicating by letter between synchronous described bidirectional buffer and the external memory interface;

One clock signal of system line carries a clock signal of system, with communicating by letter between synchronous described bidirectional buffer and the system bus interface; And

The clock selecting logical circuit, be configured to be coupled to described bidirectional buffer in order to control the described signal that will be equipped on this memory clock signal line and this clock signal of system line, make this clock selecting logical circuit when communicating by letter between described bidirectional buffer and this external memory interface, this memory clock signal that control is equipped on this memory clock signal line is coupled to described bidirectional buffer, and making this clock selecting logical circuit when communicating by letter between described bidirectional buffer and this system bus interface, this clock signal of system that control is equipped on the clock signal of system line is coupled to described bidirectional buffer.

7. the interface circuit of a high access efficiency comprises:

A plurality of bidirectional buffers are plugged between a system bus and the external memory storage;

The clock selecting logical circuit, be configured in order to the data communication of control by described bidirectional buffer, this logical circuit is configured in order to select a clock signal for each described bidirectional buffer, wherein, this selecteed clock signal be a system clock and a memory clock one of them; And

The address check logical circuit, response is read request from one of a system element, is configured to whether be arranged in described bidirectional buffer at present and designatedly be written into an external memory storage from described bidirectional buffer in order to confirm as requested data.

8. the interface circuit of a high access efficiency comprises:

A plurality of bidirectional buffers;

Logical circuit, response is read request from one of a system element, this logical circuit is configured in order to confirm whether designated whether requested data be arranged in described bidirectional buffer at present and write to an external memory storage from described bidirectional buffer, wherein this logical circuit more is configured to need not earlier these data to be write to this external memory storage in order to supply these data from described bidirectional buffer to this Request System element.

9. the interface circuit of high access efficiency as claimed in claim 8 more comprises:

One memory clock signal line is in order to carry a memory clock signal communicating by letter with synchronous described bidirectional buffer and an external memory interface;

One clock signal of system line is in order to carry a clock signal of system communicating by letter with synchronous described bidirectional buffer and a system bus interface; And

The clock selecting logical circuit, being configured in order to will be equipped on this memory clock signal line and this controlledly is that the described signal of clock cable is coupled to described bidirectional buffer, make this clock selecting logical circuit, when between described bidirectional buffer and this external memory interface, communicating by letter, this signal that will be equipped on this memory clock signal line is coupled to described bidirectional buffer controlledly, and make this clock selecting logical circuit, when communicating by letter between described bidirectional buffer and this system bus interface, this signal that will be equipped on the clock signal of system line is coupled to described bidirectional buffer controlledly.

10. the interface method of a high access efficiency is applicable to communicating by letter between a system bus and the storer, comprising:

Write data to a two-way impact damper that is located in the interface, from this system bus data are write the instruction of this storer with response;

Be received in the request that the device of one on this system bus is sent, with acquisition data from this storer;

Whether judgment data is stored in this bidirectional buffer at present, and waits for and the communicating by letter of this storer; And

From these these requested data of bidirectional buffer acquisition,, need not to wait for that earlier these data are written into this storer to communicate by letter with this request unit.

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