CN101060007B - Composite memory chip - Google Patents
Composite memory chip Download PDFInfo
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- CN101060007B CN101060007B CN2007100877117A CN200710087711A CN101060007B CN 101060007 B CN101060007 B CN 101060007B CN 2007100877117 A CN2007100877117 A CN 2007100877117A CN 200710087711 A CN200710087711 A CN 200710087711A CN 101060007 B CN101060007 B CN 101060007B
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Abstract
A composite memory chip is disclosed. The composite memory chip comprises a first voltage pin, a second voltage pin, a voltage generator, a flash memory and a static random access memory. The first voltage pin is used for providing a first voltage. The second voltage pin is used for providing a second voltage lower than the first voltage so as to define a working voltage together with the first voltage. The voltage generator generates a third voltage through the first voltage, wherein the third voltage is greater than the first voltage. The flash memory and the static random access memory both operate at the operating voltage. And the flash memory executes a data erasing action through the third voltage.
Description
Technical field
The relevant a kind of composite memory chip of the present invention; Specifically, be the composite memory chip that does not need the mode of operation output connecting pin of high voltage input pin and special use about a kind of.
Background technology
In recent years, along with flash memory (flash memory) and static RAM (static random access memory; The augmentation of application SRAM) and the increase of demand, existing increasing manufacturer is packaged together flash memory and static RAM, and then forms a composite memory chip, to satisfy the demand of using manufacturer once.
Yet, because flash memory and static RAM all have its signal output connecting pin and signal input pin separately, if therefore these pins are not integrated, and flash memory and static RAM directly are packaged together, will make the signal output/input pin of composite memory chip seem various and complicated, and therefore improve the degree of difficulty of manufacturer in wiring (layout).Therefore, each tame manufacturer racks one's brains invariably, integrates the output/input pin of these signals, to reduce the number of these pins.
It is that address pin and data pin with flash memory and static RAM combines that a kind of technology is arranged at present on the market, so can reduce the signal output/input pin of composite memory chip significantly, yet this kind composite memory chip is not attained ideal yet.Fig. 1 is the circuit diagram that illustrates the flash memory 1 of existing composite memory chip inside.The square frame of label 102 indications is one and draws the high voltage input pin Vpp that receives this composite memory chip outside, this high voltage input pin Vpp promptly provide this flash memory in the process of carrying out the data erasing move the high voltage that must use.Yet this kind way must additionally provide this high voltage, has increased the number and the kind of the pin of power supply.
In addition, also there is a kind of memory chip, also integrated the data pin and the address pin of two kinds of different memories, but additionally used the mode of operation output connecting pin of a special use, in order to the mode of operation signal of output storage.So use the manufacturer of this kind memory chip must develop the communications protocol of data transmission accordingly at this special-purpose mode of operation output connecting pin more again, also increased the pin number of composite memory chip, and caused sizable trouble.
Two kinds of above-mentioned memory chips, though all integrated signal input and output connecting pin significantly, yet but limit for fear of existing technical conditions, still high voltage can't be imported pin and the mode of operation output connecting pin is suitably integrated, caused use manufacturer must additionally remove to develop accordingly related hardware equipment, or even the relevant communications protocol of development, increase the restriction of cost and range of application on foot.
Summary of the invention
A purpose of the present invention is to provide a kind of composite memory chip that does not need the mode of operation output connecting pin of high voltage input pin and special use.
A kind of composite memory chip according to an aspect of the present invention, it comprises one first voltage pin, one second voltage pin, a voltage generator, a flash memory and a static RAM.This first voltage pin is in order to provide one first voltage.This second voltage pin is one second a low voltage in order to provide than this first voltage, to define an operating voltage jointly with this first voltage.This voltage generator produces a tertiary voltage by this first voltage, and wherein this tertiary voltage is greater than this first voltage.This flash memory and this static RAM all are to operate under this operating voltage.And this flash memory is carried out data erase action by this tertiary voltage.
A kind of composite memory chip according to a further aspect of the invention, it comprises one first voltage pin, one second voltage pin, a data pin, a flash memory and a static RAM.This first voltage pin is in order to provide one first voltage.This second voltage pin is one second a low voltage in order to provide than this first voltage, to define an operating voltage jointly with this first voltage.This flash memory and this static RAM all are to operate under this operating voltage, and transmit a data-signal via this data pin jointly.And this flash memory is to transmit a mode of operation signal via this data pin.
Composite memory chip of the present invention is to obtain flash memory necessary high voltages in the process of carrying out the data erasing move by promoting its operating voltage.So composite memory chip of the present invention does not need additionally to provide high voltage input pin to receive high voltage.Moreover the data manipulation status signal of composite memory chip of the present invention is outwards to transmit by general data pin, so do not need special-purpose mode of operation output connecting pin.In sum, composite memory chip of the present invention does not need to supply high-tension pin and special-purpose mode of operation output connecting pin, so reduced the number of pin.
Behind the embodiment of consulting accompanying drawing and describing subsequently, this technical field has knows that usually the knowledgeable just can understand other purposes of the present invention, and technological means of the present invention and enforcement aspect.
Description of drawings
Fig. 1 is the synoptic diagram of existing flash memory; And
Fig. 2 is the synoptic diagram of preferred embodiment of the present invention.
Embodiment
Preferred embodiment of the present invention as shown in Figure 2, it is a kind of composite memory chip 2.Composite memory chip 2 comprises one first voltage pin 201, one second voltage pin 203, a voltage generator 205, a flash memory 207, a static RAM 209, an address pin group 211, a data pin group 213 and a plurality of control signal pin 215.Flash memory 207 can be that any memory manufacturer is produced and in the flash memory of selling on the market, in the present embodiment, flash memory 207 is flash memories that US business Intel Company is produced.And static RAM 209 also can be the static RAM that any memory manufacturer is produced, and can also be a virtual static RAM (pseudo static random access memory; PSRAM).
The first voltage pin 201 provides one first voltage vcc, and the second voltage pin 203 provides one second voltage V
GND, the second voltage V wherein
GNDVoltage potential be lower than first voltage vcc, and first voltage vcc and the second voltage V
GNDDefine an operating voltage jointly.209 of flash memory 207 and static RAMs operating voltage according to this operate.In the present embodiment, the second voltage V
GNDVoltage potential be 0 volt, therefore, the voltage potential of first voltage vcc is operating voltage.
205 of voltage generators receive first voltage vcc, and produce a tertiary voltage V by the voltage potential that promotes first voltage vcc
DDWhen flash memory 207 desires to carry out the data erase action, promptly be wherein by tertiary voltage V
DD Drive flash memory 207 to carry out data erase.Thus, do not need the pin numbers that increase more, also can be with the data erase of flash memory 207.Be noted that, though the voltage generator 205 that Fig. 2 illustrated is to be positioned in the composite memory chip 2, but it also can be positioned in the flash memory 207, this technical field has knows that usually the knowledgeable can be by aforesaid explanation to understand not deboost generator 205 position of being put of the present invention, so repeat no more.
211 of address pin groups be as composite memory chip 2, can be used for transmitting the address signal of flash memory 207 or the address signal of static RAM 209.This technical field has knows that usually the knowledgeable can understand the principle of its transport address signal easily, so repeat no more.
And the present invention does not limit the number and the function thereof of control signal pin 215, and it can optionally increase the pin number in addition, to transmit multi-form control signal.This technical field has knows that usually the knowledgeable can understand operation principles of the present invention, so repeat no more by aforesaid explanation.
From the above, composite memory chip 2 of the present invention is first voltage vcc and the second voltage V that import from the outside of composite memory chip 2 by promoting
GND, and obtain flash memory 207 necessary high voltages in data erasing process, so not needing additionally to provide high voltage input pin to receive high voltage, do not use composite memory chip of the present invention 2 so that flash memory 207 to be provided.Simultaneously, because the data manipulation state of composite memory chip 2 employed flash memories 207 of the present invention is outwards to transmit by general data pin, therefore composite memory chip 2 of the present invention and composite memory chip 2 employed flash memories 207 more do not need the mode of operation signal output connecting pin of additional designs special use.
So adopt composite memory chip 2 of the present invention, not only can simplify the complicacy of pin, reduced and used the difficulty of manufacturer when wiring, and use manufacturer also needn't additionally provide high voltage, and increased the number and the kind of the pin of necessary power supply to the flash memory in the composite memory chip 2 207.Moreover, use manufacturer also needn't be again at the mode of operation signal output connecting pin of special use and the communications protocol of development dataset transmission has accordingly been save sizable trouble, and reached required technological breakthrough purpose.
The above embodiments only are used for exemplifying enforcement aspect of the present invention, and explain technical characterictic of the present invention, are not to be used for limiting category of the present invention.Any be familiar with this operator can unlabored change or the arrangement of the isotropism scope that all belongs to the present invention and advocated, the scope of the present invention should be as the criterion with the application's claim scope.
Claims (17)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2007100877117A CN101060007B (en) | 2006-04-17 | 2007-03-08 | Composite memory chip |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610066641.2 | 2006-04-17 | ||
| CN200610066641 | 2006-04-17 | ||
| CN2007100877117A CN101060007B (en) | 2006-04-17 | 2007-03-08 | Composite memory chip |
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| Publication Number | Publication Date |
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| CN101060007A CN101060007A (en) | 2007-10-24 |
| CN101060007B true CN101060007B (en) | 2010-10-06 |
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| CN2007100877117A Expired - Fee Related CN101060007B (en) | 2006-04-17 | 2007-03-08 | Composite memory chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE47308E1 (en) | 2008-03-19 | 2019-03-19 | Toshiba Memory Corporation | Memory device, host device, memory system, memory device control method, host device control method and memory system control method |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8406075B2 (en) * | 2009-04-03 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Ultra-low leakage memory architecture |
| CN102034524B (en) * | 2010-10-25 | 2015-09-16 | 上海华虹宏力半导体制造有限公司 | SOC (system on a chip) and method for designing thereof |
| CN102779550B (en) * | 2011-05-12 | 2015-06-10 | 中国科学院微电子研究所 | Multi-functional memory cell, array and method of manufacturing the same |
| WO2014134865A1 (en) * | 2013-03-06 | 2014-09-12 | Zhang Guobiao | Three-dimensional memory comprising independent intermediate circuit chip |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1156489A1 (en) * | 1999-10-04 | 2001-11-21 | Seiko Epson Corporation | Integrated circuit, ink cartridge, and ink-jet printer |
| CN1605972A (en) * | 2003-10-06 | 2005-04-13 | 华邦电子股份有限公司 | CPU supply voltage control circuit |
| CN1716595A (en) * | 2004-07-01 | 2006-01-04 | 富士通株式会社 | Semiconductor device and manufacture method thereof |
-
2007
- 2007-03-08 CN CN2007100877117A patent/CN101060007B/en not_active Expired - Fee Related
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1156489A1 (en) * | 1999-10-04 | 2001-11-21 | Seiko Epson Corporation | Integrated circuit, ink cartridge, and ink-jet printer |
| CN1605972A (en) * | 2003-10-06 | 2005-04-13 | 华邦电子股份有限公司 | CPU supply voltage control circuit |
| CN1716595A (en) * | 2004-07-01 | 2006-01-04 | 富士通株式会社 | Semiconductor device and manufacture method thereof |
Non-Patent Citations (1)
| Title |
|---|
| CN 1716595 A,说明书全文. |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| USRE47308E1 (en) | 2008-03-19 | 2019-03-19 | Toshiba Memory Corporation | Memory device, host device, memory system, memory device control method, host device control method and memory system control method |
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| CN101060007A (en) | 2007-10-24 |
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