CN101034373A - Controller of external storing device and address change method based on same - Google Patents
Controller of external storing device and address change method based on same Download PDFInfo
- Publication number
- CN101034373A CN101034373A CN 200710089533 CN200710089533A CN101034373A CN 101034373 A CN101034373 A CN 101034373A CN 200710089533 CN200710089533 CN 200710089533 CN 200710089533 A CN200710089533 A CN 200710089533A CN 101034373 A CN101034373 A CN 101034373A
- Authority
- CN
- China
- Prior art keywords
- address
- control signal
- data
- displacement control
- external memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims abstract description 13
- 238000006073 displacement reaction Methods 0.000 claims description 34
- 238000013507 mapping Methods 0.000 claims description 12
- 230000005055 memory storage Effects 0.000 claims description 3
- 230000001131 transforming effect Effects 0.000 abstract 2
- 230000005540 biological transmission Effects 0.000 description 11
- 238000010586 diagram Methods 0.000 description 4
- 230000008707 rearrangement Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000009131 signaling function Effects 0.000 description 1
Images
Landscapes
- Static Random-Access Memory (AREA)
Abstract
The invention provides an external memory controller and an address transforming method based on the external memory controller, according to the received shift control signal, making offset control on the input address and obtaining the output address aligned with the high level or low level of the current memory address line. And it avoids the possible link errors, improves address transforming flexibility and besides, improves the link flexibility of the corresponding devices and assures the alignment of the output address with the memory address line, and assures data access is right.
Description
Technical field
The present invention relates to chip field, relate in particular to a kind of external memory controller and based on the method for the address mapping of external memory controller.
Background technology
Memory Controller is as a kind of general memory interface, and it is applicable to the various types of read-write operation that is similar to the various memory devices of asynchronous memory (storer) interface of control.
When its read-write operation is controlled, because the data bit width difference of various memory devices, make that the bit wide of its corresponding address line is unascertainable, several external memory controllers that Fig. 1 provides for prior art and the connected mode synoptic diagram of storer, as shown in Figure 1, if data bit width is 8, the bit wide of corresponding address line is 32, if data bit width is 16, the bit wide of its corresponding address line should be 31, if data bit width is 32, the bit wide of its corresponding address line should be 30.
But for OPADD, if two devices of direct communication, because the difference of data bit width, when the bit wide of its corresponding address line is inconsistent, if it is improper to connect, may cause the invalid or actual minimum data bit width corresponding address position of differentiating of lowest order of address invalid.Such as data bit width is 16bits (16 s') device, and the address wire bit wide is 31, and may be the 0th address for the 31bits alignment this time, and also the 0th of possibility is invalid bit, and the 1st address for the 31bits alignment.
In the prior art, usually adopt the mode of determining vacant address bit in advance to solve the inconsistent problem of address wire bit wide, such as the solution in the part prior art scheme is being connected for all storeies and Memory Controller, suppose that all the address wire name is called A, width is 32, the storer fixed capacity is 4G, unified employing connected mode as shown in table 1, table 1 is the address connected mode of the storer of the different pieces of information bit wide of part prior art scheme regulation when being connected with Memory Controller, i.e. regulation: data bit width is that 8 storer is when being connected with Memory Controller, because the address wire bit wide of this storer is 32, so there is not vacant address wire; Data bit width is that 16 storer is when being connected with Memory Controller, because the address wire bit wide of this storer is 31, so the 0th of its address wire is vacant; Data bit width is 32 a storer when being connected with Memory Controller, because the address wire bit wide of this storer is 30, so the 0th of its address wire and the 1st are all vacant.
Table 1: the address connected mode the when storer of different pieces of information bit wide is connected with Memory Controller
| Memory width | The address connected mode | Vacant address wire |
| 8 | A[31:0] | Do not have |
| 16 | A[31:1] | A[0] |
| 32 | A[31:2] | A[1:0] |
As seen, when adopting this mode to solve the inconsistent problem of device address wire bit wide, must must guarantee to interconnect between the device, the problem of connection error does not take place in wiring, in case in wiring, connection error occurs, can directly cause OPADD not align, when reference-to storage, will make visit data mistake occur owing to the mistake of reference address.
It can be seen from the above, in the prior art, is to determine in advance when mistake appears in line, may bring hard error well to the inconsistent solution of address wire bit wide, causes visit to make mistakes.
Summary of the invention
Embodiments of the invention provide a kind of external memory controller and method of address mapping, and the dirigibility that has improved address mapping has also increased the dirigibility of corresponding device line simultaneously.
Embodiments of the invention are to be achieved through the following technical solutions:
A kind of external memory controller comprises:
The acquisition module of displacement control signal is used for obtaining the displacement control signal, and the control signal output that will be shifted;
Address changing module, described address changing module is connected with storer, is used for according to the displacement control signal that receives, and the initial address of input is carried out skew control, needed OPADD when obtaining being used for reference-to storage; Described OPADD is the physical address of current storage particular memory space, and described OPADD is alignd with a current storage address wire high position or low level.
A kind of method of the address mapping based on external memory controller comprises:
Obtain the displacement control signal;
According to described displacement control signal, initial address to input is offset control, needed OPADD when obtaining visiting current storage, described OPADD is the physical address of current storage particular memory space, and described OPADD is alignd with a current storage address wire high position or low level.
The technical scheme that is provided by the embodiment of the invention described above as can be seen, embodiments of the invention provide a kind of external memory controller and based on the method for the address mapping of external memory controller, the OPADD that needs during with the visit current storage is alignd with an address wire high position or the status of current storage, avoided the hardware Miswire that may exist because the address wire of OPADD that needs during the visit current storage and current storage does not line up, improved the dirigibility of address mapping, also increased simultaneously the dirigibility of corresponding device line, guarantee that OPADD aligns with the address wire of storer, guarantee that visit data do not make mistakes.
Description of drawings
Several external memory controllers that Fig. 1 provides for prior art and the connected mode synoptic diagram of storer;
The realization read operation that Fig. 2 provides for the embodiment of the invention and the structural representation of write operation;
Realize the combinational logic circuit synoptic diagram of displacement control in the address changing module that Fig. 3 provides for the embodiment of the invention;
The external memory controller behind address align that Fig. 4 provides for the embodiment of the invention and the connected mode synoptic diagram of storer.
Embodiment
Embodiments of the invention provide a kind of external memory controller, comprise the acquisition module and the address changing module of the control signal that is shifted;
The acquisition module of described displacement control signal is used for obtaining the displacement control signal, and with described displacement control signal output; The acquisition module of described displacement control signal can be realized by the configuration register module that links to each other with address changing module, also can realize by possessing the software module that obtains displacement control signal function; The configuration register module obtains described displacement control signal according to the data bit width of current storage, and with described mobile control signal output.
Described address changing module is used for according to the displacement control signal that receives the initial address of importing being offset control, obtains the OPADD of aliging with an address wire high position or the low level of the storer that is connected this external memory controller;
This address changing module can be passed through different combinational logics and realize, such as, this address changing module can realize the function of its address mapping by the combination of a plurality of alternative Port Multipliers;
In addition, it should be noted that after obtaining the address of aliging with the address wire of the storer that is connected this external memory controller, can be according to actual needs, a series of operation is carried out in this address, thereby obtain OPADD, guarantee normal reference-to storage.
Embodiments of the invention also provide a kind of method of the address mapping based on external memory controller, comprising:
Obtain the displacement control signal; Described displacement control signal is according to the data bit width decision of external memory storage;
According to described displacement control signal, initial address to input is offset control, needed OPADD when obtaining visiting current storage, described OPADD is the physical address of current storage particular memory space, and described OPADD is alignd with a current storage address wire high position or low level.
For the ease of understanding the technical scheme that embodiments of the invention provide, the technical scheme that embodiments of the invention provide is described below in conjunction with specific embodiments:
Being that to read 32 bit data in 16 the storer be example by ahb bus to a data bit wide, the technical scheme that embodiments of the invention provide is elaborated the realization read operation that Fig. 2 provides for the embodiment of the invention and the structural representation of write operation in conjunction with Fig. 2;
In this embodiment, ahb bus links to each other with external memory controller, storer connects external memory controller, the memory capacity of storer is fixed, the initial address of bringing on the bus corresponding with this 32 bit data is 0x080, that is to say if the data bit width of ahb bus is 32, and according to byte (byte, a byte has 8) storage format stores this 32 bit data, this 32 bit data should be corresponding to the position of the 0x080/0x81/0x82/0x83 in the storage space so, yet because the data bit width of the storer of this 32 bit data of current storage is 16, then this 32 bit data in fact the position in current storage be unknown, need obtain this position according to the initial address of this 32 bit data correspondence, the concrete operations step is:
Step 1 according to the data bit width of this 32 bit data and the data bit width of current storage, is determined the displacement control signal, and generally speaking, this displacement control signal is a bit, is 1 or 0, also can be the binary number more than;
In this step, also can be understood as according to the initial address corresponding and the address wire bit wide of current storage with this 32 bit data, determine the displacement control signal;
This is because the quantity of data bit width and the bit wide of its address wire are one to one, that is to say great data bit width, corresponding address line bit wide is with it just arranged, as the data bit wide 32 data, corresponding address line bit wide is 30, and data bit width is 16 data, and corresponding address line bit wide is 31, data bit width is 8 data, and corresponding address line bit wide is 32;
Because the data bit width of current storage is 16, the data of transmitting on the ahb bus are to store this 32 bit data according to the byte storage format, the data bit width that is its storage space correspondence is 8, so the data corresponding address line bit wide of transmitting on the ahb bus is 32; And the address wire bit wide of current storage is 31, and is different with the data corresponding address line bit wide of transmitting on the ahb bus, so need determine the displacement control signal according to the difference of address wire bit wide of the two;
Step 2, the displacement control signal of determining is transferred to address changing module, and this address changing module is offset control according to the displacement control signal to described initial address, promptly control the initial address unification to moving to left or unified moving right, obtain the address of aliging with the current storage address wire;
In this step, address changing module realizes that the operation of skew control realizes by combinational logic circuit, here said combinational logic circuit can be made up of more than one Port Multiplier, such as, the combinational logic circuit of forming by four alternative Port Multipliers as shown in Figure 3, just can realize the function of skew control to initial address, among Fig. 3, the gating signal of alternative Port Multiplier is the displacement control signal, initial address is made up of A0A1A2, and when the displacement control signal was 1, the output of four alternative Port Multipliers from top to bottom was respectively: a0=A0, a1=A1, a2=A2, a3=0, promptly initial address is to one of " left side " skew, when the displacement control signal is 0, the output of four alternative Port Multipliers from top to bottom is respectively: a0=0, a1=A0, a2=A1, a3=A2, promptly initial address is to one of " right side " skew;
In this embodiment, initial address is 0x080, its corresponding address line bit wide is 32, and the address wire bit wide of current storage is 31, if adopt the principle of low level alignment, then need 0x080 moved to right one and promptly obtain 0x40, this moment, this address was transformed into 31 address, with the address wire complete matching of current storage (data bit width is 16), like this in the output of address, just can not produce the problem that the address does not line up, just can not produce the problem that visit makes mistakes yet;
Several external memory controllers as shown in Figure 1 and the annexation of storer, behind address align, can obtain annexation as shown in Figure 4, as can be seen, if take place to connect dislocation (as with A[31:1] mistake be linked as A[30:0]), by the software setting relevant register, the address is offset, can evade mistake.
Because the process of this address offset can artificially be controlled, and can regulate at any time according to the connection situation of current storage address wire, therefore lower with respect to the requirement of prior art to the memory address line wiring, increased the dirigibility of placement-and-routing;
Step 3, after obtaining the address of aliging with the current storage address wire, can be according to the data bit width of current storage, whether decision needs the operation that adds up of described address, required OPADD when obtaining visiting current storage;
This is that promptly the data that will read are 32 because the data bit width of ahb bus is generally 32, and the data bit width of current storage is not necessarily consistent with the data bit width of bus.If the data bit width of current storage is littler than the data bit width of bus, the data that will read not only one of corresponding memory space in current storage so, this just need be after obtaining the address of aliging with the current storage address wire, according to described address, it is carried out the operation (needed address as can obtain carrying out read operation next time by the mode that increases progressively automatically the time) of appointment, thereby obtain visiting the needed OPADD of current storage;
As shown in Figure 2, in comparer, tag (sign) compares with transmission parameter, obtains the comparative result of tag and transmission parameter; Conversion is done according to this comparative result in described address of aliging with the current storage address wire, can obtain carrying out needed OPADD when reading this operation of 32 bit data; The concrete operations step is as follows:
At first, because the data bit width of storer is 16bits, the address of aliging with the current storage address wire that obtains through step 2 is 0x40,0x40 is the physical address of the 1st 16 bit data in storer in 32 bit data that will read, according to this physical address reference-to storage, the 1st 16 bit data in 32 bit data that can obtain reading;
Second, because the initial value of tag is 0000, and (data bit width that refers to current storage is 16 in this case, and the data of ahb bus transmission are to store according to the byte storage format, transmission for 32bits data, corresponding to 4 byte, the corresponding byte of in the transmission parameter each, so this moment transmission parameter should be 1111) transmission parameter be 1111 (transmission parameter remains unchanged in the transmission course of these data), in comparer, tag and transmission parameter are made comparisons, and obtain the 1st 16bits data and are read into after the read buffer (reading buffer memory), and the initial value 0000 of tag need be moved to the left 2bits, and (this is because read the data of a 16bits, the data of 2 byte just, so tag will mobile 2bits), right position fills out 11, becomes 0011;
The 3rd, after the tag value becomes 0011, in comparer, tag and transmission parameter are made comparisons once more, obtain continuing the indicator signal of read operation, promptly also needed to read again the indicator signal of the data of a 16bits, export this indicator signal to address changing module, address 0x40 increased progressively obtain the physical address of next 16bits data in storer and should be 0x41, according to the 0x41 reference-to storage, data that so just can read next 16bits, finishing by ahb bus to a data bit wide is the operation of reading one 32 bit data in 16 the storer;
Simultaneously, tag is once more to the 2bits that moves to left, and right position fills out 11, becomes 1111.
In the process of above-mentioned read data, variation has taken place in the ordering of the data of reading, therefore needs order rearrangement; Such as need being several 55AA that the storage space of 0x80 is read a 32bits from initial address when needing ahb bus, but the data bit width of current storage is 16bits, so need be by carrying out the operation of reading 16bits 2 times, soon the number of reading for this twice is stitched together.As reading AA according to address 0x40 for the first time, read 55 according to address 0x41 the 2nd time, the number of reading is AA55, the ordering of the number of reading with needs is different, needing read buffer like this is the output data that moves to right, promptly, with high position data AA output, realize order rearrangement at first with after low data 55 outputs.
For the operation by the ahb bus write data, above-mentioned steps stands good, and just repeats no more at this; But because in the operation of write data, the problem in the read data operation can not appear being similar in data sorting, so need not order rearrangement.
Comprehensively above-mentioned, embodiments of the invention provide a kind of external memory controller and based on the method for the address mapping of external memory controller, the OPADD that needs during with the visit current storage is alignd with an address wire high position or the status of current storage, avoided the hardware Miswire that may exist because the address wire of OPADD that needs during the visit current storage and current storage does not line up, improved the dirigibility of address mapping, also increased simultaneously the dirigibility of corresponding device line, guarantee that OPADD aligns with the address wire of storer, guarantee that visit data do not make mistakes.
So far; the present invention only is operating as the technical scheme that example has illustrated that the embodiment of the invention provides with reading and writing; but the present invention is not only limited to read-write operation; the displacement control signal that all receive based on basis; Input Address is offset control; obtain the technical scheme with the OPADD of memory address line complete matching, no matter which kind of form of employing, all within protection scope of the present invention.
The above; only for the preferable embodiment of the present invention, but protection scope of the present invention is not limited thereto, and anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; the conversion that can expect easily or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claims.
Claims (5)
1, a kind of external memory controller is characterized in that, comprising:
The acquisition module of displacement control signal is used for obtaining the displacement control signal, and the control signal output that will be shifted;
Address changing module, described address changing module is connected with storer, is used for according to the displacement control signal that receives, and the initial address of input is carried out skew control, needed OPADD when obtaining being used for reference-to storage; Described OPADD is the physical address of current storage particular memory space, and described OPADD is alignd with a current storage address wire high position or low level.
2, external memory controller according to claim 1, it is characterized in that, the acquisition module of described displacement control signal is the configuration register module that is connected with address changing module, described configuration register module is used for according to the external memory storage data bit width, obtain the displacement control signal, and with described mobile control signal output.
3, external memory controller according to claim 1 is characterized in that, described address changing module is made up of at least one MUX.
4, a kind of method of the address mapping based on external memory controller is characterized in that, comprising:
Obtain the displacement control signal;
According to described displacement control signal, initial address to input is offset control, needed OPADD when obtaining visiting current storage, described OPADD is the physical address of current storage particular memory space, and described OPADD is alignd with a current storage address wire high position or low level.
5, method according to claim 4 is characterized in that, described displacement control signal is according to the data bit width decision of external memory storage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100895331A CN100461134C (en) | 2007-03-27 | 2007-03-27 | Controller of external storing device and address change method based on same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100895331A CN100461134C (en) | 2007-03-27 | 2007-03-27 | Controller of external storing device and address change method based on same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101034373A true CN101034373A (en) | 2007-09-12 |
| CN100461134C CN100461134C (en) | 2009-02-11 |
Family
ID=38730939
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100895331A Active CN100461134C (en) | 2007-03-27 | 2007-03-27 | Controller of external storing device and address change method based on same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100461134C (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944385A (en) * | 2010-06-24 | 2011-01-12 | 新邮通信设备有限公司 | Memorizer |
| CN106201905A (en) * | 2016-07-11 | 2016-12-07 | 浪潮(北京)电子信息产业有限公司 | A kind of internal memory addressing method |
| CN104112102B (en) * | 2014-06-30 | 2017-08-04 | 中国人民解放军国防科学技术大学 | Multi-DDR access control method and device supporting address cross scheme configuration |
| CN111338997A (en) * | 2020-03-05 | 2020-06-26 | 苏州浪潮智能科技有限公司 | A method, apparatus, device and medium for ARM server BIOS to support TCM communication |
| CN113434545A (en) * | 2021-06-02 | 2021-09-24 | 中科驭数（北京）科技有限公司 | Data caching device and data providing method |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6226561A (en) * | 1985-07-26 | 1987-02-04 | Toshiba Corp | Personal computer |
| US5404485A (en) * | 1993-03-08 | 1995-04-04 | M-Systems Flash Disk Pioneers Ltd. | Flash file system |
| JP3913413B2 (en) * | 1999-08-25 | 2007-05-09 | 富士通株式会社 | Semiconductor device |
| JP2008511896A (en) * | 2004-09-03 | 2008-04-17 | コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ | MEMORY INTERFACE, MEMORY CONFIGURATION, AND MEMORY ACCESS CONTROL METHOD |
-
2007
- 2007-03-27 CN CNB2007100895331A patent/CN100461134C/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101944385A (en) * | 2010-06-24 | 2011-01-12 | 新邮通信设备有限公司 | Memorizer |
| CN101944385B (en) * | 2010-06-24 | 2013-02-06 | 新邮通信设备有限公司 | Memorizer |
| CN104112102B (en) * | 2014-06-30 | 2017-08-04 | 中国人民解放军国防科学技术大学 | Multi-DDR access control method and device supporting address cross scheme configuration |
| CN106201905A (en) * | 2016-07-11 | 2016-12-07 | 浪潮(北京)电子信息产业有限公司 | A kind of internal memory addressing method |
| CN106201905B (en) * | 2016-07-11 | 2019-09-24 | 浪潮(北京)电子信息产业有限公司 | A kind of memory addressing method |
| CN111338997A (en) * | 2020-03-05 | 2020-06-26 | 苏州浪潮智能科技有限公司 | A method, apparatus, device and medium for ARM server BIOS to support TCM communication |
| CN111338997B (en) * | 2020-03-05 | 2021-07-20 | 苏州浪潮智能科技有限公司 | A method, apparatus, device and medium for ARM server BIOS to support TCM communication |
| US11669477B2 (en) | 2020-03-05 | 2023-06-06 | Inspur Suzhou Intelligent Technology Co., Ltd. | Method and apparatus for supporting TCM communication by BIOS of ARM server, device, and medium |
| CN113434545A (en) * | 2021-06-02 | 2021-09-24 | 中科驭数（北京）科技有限公司 | Data caching device and data providing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100461134C (en) | 2009-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN112463714B (en) | Remote direct memory access method, heterogeneous computing system and electronic equipment | |
| US20090228637A1 (en) | High-speed solid state storage system having a hierarchy of different control units that process data in a corresponding memory area and method of controlling the same | |
| CN101034373A (en) | Controller of external storing device and address change method based on same | |
| US20070133311A1 (en) | Memory with flexible serial interfaces and method for accessing memory thereof | |
| US10698851B1 (en) | Data bit width converter and system on chip thereof | |
| CN101853694A (en) | Memory storage | |
| CN1819554B (en) | Data processing system and data interfacing method thereof | |
| CN1694252A (en) | Defect Tolerant Redundancy | |
| CN1783330A (en) | Memory device | |
| CN101075213A (en) | ROM data patch circuit, embedded system including the same and method of patching rom data | |
| CN105206307A (en) | Chip restoration method and device | |
| CN106708422A (en) | Data storage device and data maintenance method thereof | |
| CN101110259A (en) | FIFO memory | |
| CN202003346U (en) | Multi-channel not-and (NAND) flash controller | |
| CN116050344B (en) | Car gauge chip | |
| CN1991811A (en) | Master module, function module, electronic device and identification data setting method thereof | |
| CN111600731A (en) | System and method for rapidly processing futures market gears | |
| CN1871592A (en) | Method and system for enhancing the endurance of memory cells | |
| CN106371773A (en) | SSD unit, SSD device and data processing method based on SSD device | |
| CN115185584A (en) | Configurable storage interface system based on DSP | |
| JPH06242925A (en) | Sort processor | |
| CN1820241A (en) | Device identification | |
| CN1619517A (en) | Multichannel internal integrated circuit | |
| CN1610896A (en) | Communication system | |
| CN101069165A (en) | Computer system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |