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CN101032004A - 用于形成薄的完整高介电常数介电层的方法 - Google Patents

用于形成薄的完整高介电常数介电层的方法 Download PDF

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Publication number
CN101032004A
CN101032004A CNA2005800329588A CN200580032958A CN101032004A CN 101032004 A CN101032004 A CN 101032004A CN A2005800329588 A CNA2005800329588 A CN A2005800329588A CN 200580032958 A CN200580032958 A CN 200580032958A CN 101032004 A CN101032004 A CN 101032004A
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layer
substrate
thin
complete
thick
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考利·瓦吉达
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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Abstract

本发明公开了一种用于在半导体应用中形成薄的完整高k层(106、207)的方法。该方法包括在处理室(10、402)中提供衬底(25、102、202、406)，在衬底(25、102、202、406)上沉积厚的完整高k层(206)，并使所沉积的厚的高k层(206)变薄以在衬底(25、102、202、406)上形成薄的完整高k层(106、207)。或者，衬底(25、102、202、406)可以在衬底(25、102、202、406)与高k层(106、207)之间含有界面层(104、204)。变薄可以通过将厚的高k层(206)暴露于反应等离子刻蚀处理来进行，或者也可以通过等离子处理来进行，该等离子处理能够对一部分厚的高k层(206)进行改性并随后用湿法处理除去厚的高k层(206)中经过改性的部分(206a)。

Description

用于形成薄的完整高介电常数介电层的方法
技术领域
本发明涉及半导体处理，更具体的说，涉及形成用于半导体应用的薄的完整高介电常数介电层的方法。
背景技术
在半导体工业中，微电子器件的最小特征尺寸正在接近深亚微米区，以满足更快、更低功率的微处理器和数字电路的需求。互补金属氧化物半导体(CMOS)器件的尺度减小在栅层叠方面给介电材料施加了尺度限制，其中标准SiO2栅极氧化介电层的厚度正在接近极限(-10，埃(A))，此时隧道电流显著影响了晶体管性能。
为了提高器件的可靠性并降低从栅极到晶体管沟道的电子泄漏，半导体晶体管技术正在栅层叠中使用高介电常数介电材料(这里也称为“高k”材料)，它使得可以在栅极介电层物理厚度增大的同时将等效栅极氧化物厚度(EOT)维持在小于约15A。EOT是栅极介电材料与作为栅极介电材料的、具有相同电容值的SiO2层实际物理厚度的相对量度。由于电容与介电常数成正比，而与层厚成反比，所以增大介电常数可以允许厚度增大以保持同样的电容。
具有比SiO2(k～3.9)更大的介电常数的介电材料通常称为高k材料。另外，高k材料还可以指沉积到衬底上的介电材料(例如HlO2、ZrO2)而不是在衬底表面上生长的材料(例如SiO2、SiOxNy)。高k材料可以含有金属硅酸盐或氧化物，包括Ta2O5(k～26)、TiO2(k～80)、ZrO2(k～25)、Al2O3(k～9)、HfSiOx(k～4-25)和HfO2(k～25)。制造具有亚微米区尺寸的特征可能需要形成非常薄的高k层(即厚度小于约100A)，且使所述高k层的间隙或厚度变动最小。
发明内容
本发明提供了一种用于在衬底上形成薄的完整高k层的方法。该方法提供了用于形成间隙极少并具有良好厚度均匀性的、薄的完整高k层的工艺。该方法包括，在处理室中提供衬底，在衬底上沉积厚的完整高k层，并使所沉积的高k层变薄以在衬底上形成薄的完整高k层。变薄可以包括以反应等离子刻蚀工艺来除去一部分所沉积的高k层，或者包括等离子处理来使所沉积的高k层改性/变薄并用湿法处理除去经过改性的部分高k层。
在本发明的一种实施例中，厚的完整高k层可以具有约30A到约200A之间的厚度。或者，厚的完整高k层的厚度可以在约50A到约100A之间。可以理解，形成完整的层所需的最小厚度对于不同的高k材料可能是不同的。但是，最小厚度通常大于栅层叠中该高k材料的期望厚度。因此，在获得完整的高k层之后，将该层的一部分除去，即变薄，留下具有较薄的期望厚度的完整高k层。在本发明的一种实施例中，薄的完整高k层可以具有约5A到约50A之间的厚度。或者，薄的完整高k层厚度可以在约30A到约40A之间。
附图说明
在附图中：
图1A-图1B示出了栅层叠的示意性剖视图，该栅层叠含有根据本发明实施例制成的高k层；
图2A-图2D示意性示出了根据本发明的一种实施例，在衬底上形成薄的完整高k层；
图2E-图2F示意性示出了根据本发明的另一实施例，在衬底上形成薄的完整高k层；
图3的流程图图示了根据本发明的一种实施例的形成薄的完整高k层的方法；
图4示意性示出了根据本发明的一种实施例的配置来沉积高k层的处理系统；
图5示意性示出了根据本发明的一种实施例的配置来处理高k层的等离子处理系统；
图6示意性示出了根据本发明的另一实施例的配置来处理高k层的等离子处理系统；
图7示意性示出了根据本发明的另一实施例的配置来处理高k层的等离子处理系统；
图8示意性示出了根据本发明的另一实施例的配置来处理高k层的等离子处理系统。
具体实施方式
图1A-图1B示出了栅层叠的示意性剖视图，该栅层叠含有根据本发明实施例制成的高k层。图1A示出了在用以形成所示刻蚀特征的各向异性等离子刻蚀处理之后，部分完成的栅层叠100。示例栅层叠100包括具有源区113和漏区114的衬底102、以及介电界面104、高k层106、栅极层108、抗反射涂层(ARC)/硬掩膜层110、光刻胶层112。衬底102可以例如含有Si、Ge、Si/Ge或GaAs。在本发明的一种实施例中，衬底102可以是含有外延Si或多晶硅的Si衬底。取决于正在形成的器件类型，Si衬底可以是n型或p型。衬底102可以是任何尺寸，例如200mm衬底、300mm衬底，或者更大的衬底。
介电界面层104可以是例如氧化物层(例如SiO2)、氮化物层(例如SiNx)、氧氮化物层(例如SiOxNy)或者它们的组合。衬底表面处的介电界面层104可以维持界面状态特性，并在高k层106与衬底102之间形成具有良好电特性的界面。但是，界面层104的存在降低了栅层叠100的整体介电常数，因此在与薄的高k层106结合时，界面层104可能需要非常薄。含有Si衬底的集成电路通常采用SiO2和/或SiOxNy界面层，这样的界面层可以具有优异的电特性，包括高的电子迁移率和低的电子陷阱密度。目前，含有形成于SiO2和/或SiOxNy界面层上的高k层的栅层叠可能需要仅有约5-10A的界面层厚度。
高k层是如下文中更详细说明的那样，根据本发明的方法形成的。例如，高k层106可以含有金属氧化物或金属硅酸盐，包括Ta2O5、TiO2、ZrO2、Al2O3、Y2O3、HfSiOx、HfO2、ZrSiOx、TaSiOx、SrOx、SrSiOx、LaOx、LaSiOx、YOx、YSiOx或它们中两种或更多种的组合。高k层106的厚度可以例如在约5A到约50A之间，可以是约30-40A。图1A中的栅极层108可以是例如掺杂多晶硅。对于光刻和等离子刻蚀领域的技术人员，选择合适的ARC/硬掩膜层110和光刻胶层112使得能够形成具有期望尺寸的刻蚀特征是公知的。
图1B示出了在用以形成所示刻蚀特征的各向异性等离子刻蚀处理之后，另一种部分完成的栅层叠101。除了图1A所示材料层之外，栅层叠101还含有金属栅极层107。例如，金属栅极层107可以约为100A厚，并可以含有W、WN、Al、TaN、TaSiN、HfN、HfSiN、TiN、TiSiN、Re、Ru或SiGe。引入金属栅极来代替传统的多晶硅栅极层或与之结合可以带来多种优点，包括消除多晶硅栅极的耗尽效应(depletion effect)、减小薄层电阻、使先前高k层有更好的可靠性并可能有更好的热稳定性。
图2A-图2D示意性示出了根据本发明的一种实施例，在衬底上形成薄的完整高k层。图2A示出了包括衬底202的衬底结构200，其中衬底202上形成有介电界面层204。如上所述，界面层204可以是例如氧化物层、氮化物层、氧氮化物层或它们的组合。用于形成氧化物层、氮化物层和氧氮化物层的工艺是半导体处理领域技术人员公知的。或者，也可以没有界面层204。
通常，在衬底上沉积薄膜时可能发生不同的膜生长模式。Frank-Vander Merwe薄膜生长的特征是衬底上理想的外延逐层生长，而Volmer-Weber薄膜生长的特征是衬底上的岛状生长。Stranski-Krastanov薄膜生长的特征是衬底上岛状生长与逐层生长相结合。在高k材料情况下，经常观察到的是Volmer-Weber和/或Stranski-Krastanov生长模式。
图2B示出了界面层204上形成的高k材料203的岛。如上所述，高k材料203可以含有金属氧化物或金属硅酸盐，或者它们的组合。图2B图示了在界面层204上沉积高k材料203时的Volmer-Weber生长。图2B图示的沉积处理并不是形成无间隙的、具有良好的厚度均匀性的、薄的完整高k层(Frank-Van der Merwe生长模式)，而是形成了所沉积高k材料203的岛，这些高k岛之间具有暴露出界面层204的间隙。在图2B中，岛具有厚度D203，该厚度例如可以在约5A到约50A之间，或者更大。岛的厚度D203和横向尺寸可以根据高k材料203的类型以及界面层204的类型而变化。此外，岛的厚度D203和横向尺寸还可能取决于高k材料203和界面层204的沉积条件和退火条件。
例如，高k材料203可以用各种沉积工艺沉积到界面层204上，所述沉积工艺是薄膜沉积领域技术人员公知的，包括但不限于热化学气相沉积(TCVD)、等离子增强化学气相沉积(PECVD)、原子层沉积(ALD)和物理气相沉积(PVD)。图4中示出并描述了为通过TCVD工艺在衬底上沉积高k层而配置的一种示例性处理系统。
将高k材料结合到衬底结构200中的一个要求是高k材料203在界面层204上(或者，在没有界面层的情况下，在衬底202上)形成完整的层，并且此完整的层具有良好的厚度均匀性。为了提高器件可靠性并减小从覆盖高k材料203的栅极到衬底202的电子泄漏，需要具有良好厚度均匀性的完整高k层。
如图2C所示，进一步将高k材料沉积到图2B中的衬底结构200上，得到界面层204上厚的完整高k层206。这里，完整高k层指没有间隙地完全覆盖了下方的界面层204或衬底202(例如连续地位于它们之上)的高k层。厚的完整高k层206的厚度D206例如可以在约30A到约200A之间，并具有良好的厚度均匀性。如上所述，在获得完整的高k层之前所必须沉积到的最小厚度可以随着高k材料而变化，但一般大于50A。不过，对于例如需要厚度D206在约10A到约40A之间的许多半导体器件而言，上述厚度D206可能太大。厚度小于D206的薄的完整高k层不能容易地沉积到界面层204上。因此，通过本发明的方法，首先形成厚度为D206的完整高k层，然后使之变薄以获得小于D206的期望厚度。
图2D示出了根据本发明的实施例来形成薄的完整高k层207。薄的完整高k层207是这样形成的：首先沉积图2C所示厚的完整高k层206，然后使层206变薄以形成厚度为D207的、薄的完整高k层207，其中厚度D207小于D206。根据本发明的一种实施例，厚度D206可以在约30A到约200A之间。或者，厚度D206可以在约50A到约100A之间。根据本发明的一种实施例，厚度D207可以在约5A到约50A之间。或者，厚度D207可以在约30A到约40A之间。
根据本发明的实施例，将厚的完整高k层206变薄可以在等离子处理系统中进行。根据本发明的实施例，变薄可以通过用能跟高k层206发生反应的侵蚀性含卤素气体对高k层206进行反应等离子刻蚀来进行，所述反应形成可从等离子处理系统除去的含卤素刻蚀产物。可以使用通式为HX、X2、CxX2或CxHyXz的含卤素气体，其中X为卤素。
图2E-图2F示意性示出了根据本发明的另一实施例，在衬底上形成薄的完整高k层。将图2C中厚的完整高k层206变薄可以通过与湿法处理相结合的等离子改性/变薄处理来进行。可以采用离子轰击来部分地除去图2F中的高k层206和/或对其进行改性，而不将其完全除去。
图2E示意性示出了对高k层206进行等离子改性/变薄处理后的改性部分206a。在一种示例中，等离子体可以含有反应性气体(例如HBr或HCl)以及惰性气体。在另一种示例中，等离子体可以只含有在等离子环境中不与高k层206反应的化学惰性气体物质，但是其中离子具有的能量足以有效地使高k层206瓦解和/或变薄，使得随后的湿法处理能够有效地从未改性部分206b除去被瓦解(改性)的部分206a。惰性气体例如可以含有稀有气体He、Ne、Ar、Kr和Xe。等离子改性/变薄处理的实际效果可能取决于等离子处理中所用的气体。可以认为，等离子处理可以增加高k层206中的无定型含量，并可能破坏在部分206a中造成原子碎片的化学键。这里提出的在等离子处理过程中使部分206a的分子结构瓦解，使得湿法刻蚀化学物质有更多选择，其中，与未改性的部分206b、界面层204和衬底202相比，所述湿法刻蚀化学物质对于改性部分206a有较高的刻蚀选择性。例如，随后的湿法刻蚀处理可以使用热硫酸(H2SO4)或氢氟酸(HF(aq))从未改性部分206b除去改性部分206a，从而形成具有厚度D207的薄的完整高k层207。由于在等离子改性/变薄处理过程中并未跨越高k层206b，所以降低了下方的界面层204和衬底202发生损坏的可能性。用于从衬底除去薄层的湿法处理是半导体处理领域技术人员公知的。
对高k层206的等离子处理可能造成界面层204的厚度增大。与本申请同日提交的、题为“A METHOD AND SYSTEM FOR FORMING AFEATURE IN A HIGH-K LAYER”的美国专利申请No.＿＿＿＿＿＿＿中描述了一种方法，用于在对高k层206的等离子处理过程中使界面层204的厚度增加减至最小，该申请的全部内容通过引用而结合于此。
图3的流程图图示了根据本发明的实施例的形成薄的完整高k层的方法。工艺300包括，在步骤302，在设置为在衬底上沉积高k层的处理室中提供衬底。在本发明的一种实施例中，衬底还可以含有形成于衬底上的界面层。在步骤304，在衬底上沉积高k层。使沉积处理执行期望的时间量，以在衬底上形成厚的完整高k层。在步骤306，使厚的完整高k层变薄以形成薄的完整高k层。在本发明的一种实施例中，变薄可以用反应等离子刻蚀来进行。在本发明的另一实施例中，等离子处理可以包括等离子改性/变薄处理，随后通过湿法处理从高k层的未改性部分除去改性部分。本领域技术人员可以理解，图3的流程图中每个步骤或阶段还可以涵盖一个或多个分离的步骤和/或处理。因此，不应将仅由302、304、306标记的三个步骤理解为将本发明的方法限制于仅有三个步骤或阶段。此外，也不应将每个代表性的步骤或阶段302、304、306理解为限制于仅仅单个工艺。
图4示意性示出了根据本发明的实施例的配置来在衬底上沉积高k层的等离子处理系统。具体地说，处理系统400配置来以TCVD工艺在衬底406上沉积高k层。处理系统400包括处理室402、气体注入系统408、泵系统412、处理监视系统438和控制器436。处理室402包括衬底支架404，待处理衬底406固定在该支架上。可以通过自动衬底传送系统经槽阀(slot valve，未示出)和室馈送机构(未示出)将衬底406传入传出处理室402，其中衬底406由位于衬底支架404内的衬底升降销(未示出)接收并由位于其中的装置进行机械传送。一旦从衬底传送系统接收到衬底406，即可将其降低到衬底支架404的上表面。衬底406可以是例如Si衬底，并且取决于正在形成的器件类型，可以例如由任何直径的衬底组成，例如200mm衬底、300mm衬底或更大的衬底。
可以通过静电夹具(未示出)将衬底406固定到衬底支架404。此外，衬底支架404还包括冷却系统(未示出)，所述冷却系统包括再循环冷却剂流，其从衬底支架404接收热量并将热量传送到热交换系统(未示出)，或者在加热时传送来自热交换系统的热量。此外，可以将气体输送到衬底406背面以提高衬底406与衬底支架404之间的气体一间隙导热性。在升高或降低温度的情况下需要对衬底406进行温度控制时，采用这样的系统。
气体注入系统408将处理气体410引入处理室402。气体注入系统408包括液体输送系统(LDS)420，液体输送系统包括至少一个含有高k前体材料的前体源422。可以用液体质量流控制器(LMFC)424对将前体材料引入汽化器426进行控制。可以将来自汽化器426的经过汽化的前体材料与从气体箱428经由气体管线430输送的载气混合，可以经由气体管线434将混合物输送到处理室402。可以用另外的气体管线432将吹扫气体(例如Ar)和其他气体(例如O2、N2和H2O)从气体箱428直接输送到处理室402。气体注入系统408允许对处理气体410从外部气源到处理室402的输送进行独立控制。气体注入系统408可以采用喷出式气体分配源，例如处理室402中的喷头。在本发明的一种可替换实施例中，气体注入系统408可以设置为使固体前体材料汽化，并将经过汽化的前体材料经由气体管线434输送到处理室402。
真空泵系统412包括真空泵418、阱416和自动压力控制器(APC)414。真空泵419可以包括能够以高达5000升/秒(及更高)的速度进行泵吸的涡轮分子真空泵(TMP)以及用于对室压力进行节流调整的闸门阀。或者，真空泵418可以包括干式泵。在处理过程中，可以经由气体注入系统408将处理气体410引入处理室402，并通过APC 414调节处理压力。阱416可以收集来自处理室402的未反应的前体材料和副产品。
控制器436包括微处理器、存储器和能够产生控制电压的数字I/O端口，它们足以与处理系统400进行通信并激活到处理系统400的输出，以及对来自处理系统400的输出进行监视。此外，控制器436耦合到处理室402、处理监视系统438、气体注入系统408和真空泵系统412，并与它们交换信息。采用储存在存储器中的程序根据所储存的工艺方案对处理系统400的上述部件进行控制。控制器436的一种示例是可以从DellCorporation，Dallas，Texas买到的DELL PRECISION WORKSTATION610TM。
例如，处理监视系统438可以测量气体种类，例如前体、反应副产品和处理环境中的其他气体。图4中的处理监视系统438部件连接到处理室402。在一种可替换实施例中，处理监视系统438的某些部件位于处理室402的下游。处理监视系统438可以由控制器436用来确定沉积处理的状态并提供反馈以确保处理符合要求。
衬底406被暴露于处理气体一段时间，这段时间可以造成期望的高k层沉积。可以通过直接实验法和/或设计实验来确定工艺条件，使得能够对高k层进行期望的沉积。例如，可以调整的工艺参数可以包括时间、温度(例如衬底温度)、处理压力、处理气体以及处理气体的相对气体流率等参数。用于沉积处理的工艺参数空间可以使用例如低于约10Torr的室压力、小于2000seem的处理气体流率、小于1000seem的前体气体流率以及高于约200℃的衬底温度。
在用TCVD沉积金属氧化物高k介电层时，将处理气体引入处理室，其中处理气体包括含有金属的前体，处理室包括待处理的受热衬底。将衬底暴露于处理气体一段时间，这段时间可以造成期望的金属氧化物高k层沉积。可以由金属氧化物化学气相沉积(MOCVD)前体来沉积金属氧化物高k材料。在使用Hf和Zr(M＝Hf、Zr)的示例情况下，MOCVD前体可以包括能够在约300℃以上的衬底温度下沉积金属氧化物层的金属醇盐(例如M(OR)n)和金属烷基胺化物(例如M(NR)4)。金属醇盐前体例如可以选自四配位络合物，例如M(OMe)4、M(OEt)4、M(OPr)4和M(OBut)4，其中Me为甲基，Et为乙基，Pr为丙基，But为叔丁基。金属烷基胺化物前体例如可以选自M(NMe2)4、M(NEt2)4和M(NPr2)4。MOCVD前体也可以选自六配位络合物，例如M(OBut)2(MMP)2和M(MMP)4，其中MMP＝OCMe2CH2OMe。本领域技术人员可以理解，在不脱离本发明范围的情况下，也可以采用其他的含金属前体。
Hf(OBut)4是含铪的MOCVD前体，能够沉积器件制造所用的HfO2高k层。Hf(OBut)4具有较高的蒸汽压(65℃下Pvap～1Torr)，因此为将前体输送到处理室所需对前体和前体输送管线进行的加热很少。另外，Hf(OBut)4在约200℃以下的温度不分解，这大大减少了由于与室壁发生的相互作用以及气相反应造成的前体分解。例如，可以用包括汽化器的液体注入系统将Hf(OBut)4前体输送到处理室，所述汽化器被维持在50℃或更高温度。可以将惰性载气(例如He、N2)与经过汽化的前体混合，以帮助将前体输送到处理室。
Hf(OBut)4含有在适当处理条件下生长化学计量的HfO2层所需的Hf金属和氧，因此工艺的复杂度降低了。或者，含有MOCVD前体的处理气体还可以含有第二含氧气体作为第二氧源。
与之类似，可以由MOCVD前体和含硅气体来沉积金属硅酸盐高k材料。例如，可以用Hf(OBut)4前体和含硅气体在衬底上沉积HfSiOx高k层。含硅气体可以含有例如硅烷(SiH4)、乙硅烷(Si2H6)、二氯甲硅烷(SiH2Cl2)、六氯乙硅烷(Si2Cl6)、二(叔丁氨)甲硅烷(SiH2(NBut)2)或四(二甲氨)甲硅烷(Si(NMe2)4)、原硅酸四乙酯(TEOS，Si(OEt)4)、或者它们中两种或更多种的组合。
处理气体还可以包括载气(例如惰性气体)和氧化气体。惰性气体可以包括Ar、He、Ne、Kr、Xe和N2中的至少一项。添加惰性气体可以例如稀释处理气体或调节处理气体的(多个)分压。氧化气体可以含有例如含氧气体，所述含氧气体包括O2、O3、H2O、H2O2、NO、NO2和N2O中的至少一项。在沉积处理中，含氧气体的作用可以是填充金属氧化物或金属硅酸盐高k层中的任何氧空缺，或者对金属氧化物前体进行化学改性。改性可以包括含氧气体与金属氧化物前体在气相下或在沉积表面上的相互作用。
图5-图8示意性示出了等离子处理系统，其可以根据本发明的实施例用来对厚的完整高k层进行等离子处理以形成薄的完整高k层。图5示意性示出了一种等离子处理系统，它被配置来根据本发明的一种实施例对高k层进行处理。图5所示等离子处理系统1能够维持等离子体，并包括等离子处理室10，等离子处理室10设置为便于在处理区域45中产生等离子体。等离子处理系统1还包括衬底支架20(待处理的衬底25固定于其上)、用于将处理气体42引入等离子处理室10的气体注入系统40、RF发生器30和用于将RF功率输送到衬底支架20的阻抗匹配网络32、真空泵系统50、等离子体监视系统57和控制器55。
气体注入系统40允许对从外部气源到处理室的处理气体输送进行独立控制。可离子化的气体或气体混合物经由气体注入系统40引入，并调节处理压力。例如，用控制器55来控制真空泵系统50和气体注入系统40。
可以通过自动衬底传送系统经槽阀(未示出)和室馈送机构(未示出)将衬底25传入传出处理室10，其中衬底25由位于衬底支架20内的衬底升降销(未示出)接收并由位于其中的装置进行机械传送。一旦从衬底传送系统接收到衬底25，即可将其降低到衬底支架20的上表面。
在一种可替换实施例中，通过静电夹具(未示出)将衬底25固定到衬底支架20。此外，衬底支架20还包括冷却系统(未示出)，所述冷却系统包括再循环冷却剂流，从衬底支架20接收热量并将热量传送到热交换系统(未示出)，或者在加热时传送来自热交换系统的热量。此外，可以将气体输送到衬底25背面以提高衬底25与衬底支架20之间的气体-间隙导热性。在升高或降低温度的情况下需要对衬底进行温度控制时，采用这样的系统。例如，在超过稳态温度的温度下对衬底进行温度控制可能是有利的，所述稳态温度是从等离子体输送到衬底25的热流与由于传导到衬底支架20而从衬底25失去的热流之间的平衡获得的。在其他实施例中，包括加热元件，例如电阻加热元件或热电加热器/冷却器。
在图5所示实施例中，衬底支架20还可以用作电极，射频(RF)功率通过该电极耦合到处理区域45中的等离子体。例如，可以通过将RF功率经过阻抗匹配网络32从RF发生器30传输到衬底支架20而使衬底支架20电偏压到RF电压。RF偏压用于加热电子并从而形成和维持等离子体。在这种配置下，系统作为RIE反应器工作，其中室和上部气体注入电极作为接地面。RF偏压的典型频率范围从1MHz到100MHz，优选为13.56MHz。
在一种可替换实施例中，可以以多个频率向衬底支架电极施加RF功率。此外，阻抗匹配网络32用于通过使反射功率减至最小而使RF功率向处理室10中等离子体的传送尽可能大。匹配网络拓扑(例如L型、π型、T型)以及自动控制方法是本领域公知的。
继续参考图5，通过气体注入系统40将处理气体42引入处理区域45。气体注入系统40可以包括喷头，其中，处理气体42通过气体注入增压室(plenum)、一系列挡板(未示出)以及多孔喷头气体注入板(未示出)，从气体输送系统(未示出)供给到处理区域45。
真空泵系统50可以包括能够以高达5000升/秒(及更高)的速度进行泵吸的涡轮分子真空泵(TMP)以及用于对室压力进行节流调整的闸门阀。在使用干法等离子刻蚀的传统等离子处理设备中，使用1000到3000升/秒的TMP。TMP有利于低压处理，所述低压通常低于50mTorr。对于高压处理(即高于100mTorr)，使用机械助力泵和干式低真空泵。
控制器55包括微处理器、存储器和能够产生控制电压的数字I/O端口，它们足以与等离子处理系统1进行通信并激活到等离子处理系统1的输入，以及对来自处理系统1的输出进行监视。此外，控制器55耦合到RF发生器30、阻抗匹配网络32、气体注入系统40、等离子体监视系统57以及真空泵系统50，并与它们交换信息。采用储存在存储器中的程序根据所储存的工艺方案对等离子处理系统1的上述部件进行控制。控制器55的一种示例是可以从Dell Corporation，Dallas，Texas买到的TMS320型数字信号处理器(DSP)。
等离子体监视系统57可以包括，例如，用于对等离子环境中激发的微粒进行测量的光学发射谱(OES)系统和/或用于测量等离子体密度的等离子诊断系统(例如朗缪尔探头)。等离子体监视系统57可以由控制器55用来确定刻蚀处理的状态并提供反馈以确保处理符合要求。或者，等离子体监视系统57可以包括微波和/或RF诊断系统。
图6示意性示出了根据本发明的另一实施例的配置来对高k层进行处理的等离子处理系统。图6的等离子处理系统2包括了图5中所示并参考图5进行了说明的系统1的那些部件，还包括以机械方式或电方式旋转的DC磁场系统60，以便能够增大等离子体密度和/或提高等离子处理的均匀性。此外，控制器55耦合到旋转磁场系统60以调整旋转速度和场强。
图7示意性示出了根据本发明的另一实施例的配置来对高k层进行处理的等离子处理系统。图7的等离子处理系统3包括了图5中所示并参考图5进行了说明的系统1的那些部件，还包括上部板电极70，RF功率通过阻抗匹配网络74从RF发生器72耦合到所述上部板电极70。将RF功率施加到上部板电极所用的典型频率范围从10MHz到200MHz，例如60MHz。另外，将功率施加到衬底支架20所用的典型频率范围从0.1MHz到30MHz，例如2MHz。此外，控制器55耦合到RF发生器72和阻抗匹配网络74，以控制RF功率施加到上部电极70。
图8示意性示出了根据本发明的另一实施例的配置来对高k层进行处理的等离子处理系统。图8的等离子处理系统4包括了图5中所示并参考图5进行了说明的系统1的那些部件，还包括电感线圈80，RF功率经由RF发生器82通过阻抗匹配网络84耦合到所述电感线圈80。RF功率从电感线圈80经过介电窗(未示出)感应耦合到等离子处理区域45。将RF功率施加到电感线圈80所用的典型频率范围从10MHz到100MHz，例如13.56MHz。类似地，将功率施加到衬底支架20所用的典型频率范围从0.1MHz到30MHz，例如13.56MHz。另外，可以用开槽的法拉第屏蔽(未示出)来减小电感线圈80与等离子体之间的电容耦合。此外，控制器55耦合到RF发生器82和阻抗匹配网络84，以控制RF功率施加到电感线圈80。
在一种可替换实施例中，使用电子回旋共振(ECR)来形成等离子体。在另一种实施例中，通过发射螺旋波来形成等离子体。在另一种实施例中，通过传播平面波来形成等离子体。
根据上述教导可以对本发明进行多种改动和变更。因此应当明白，在所附权利要求的范围内，可以采用与此处的具体说明不同的其他方式来实施本发明。

Claims (21)

1.一种用于在衬底上形成薄的高k层的方法，所述方法包括：
在处理室中提供衬底；
使高k材料至少沉积到最小厚度，从而在所述衬底上形成厚的完整高k层；以及
使所述厚的完整高k层变薄到小于所述最小厚度的期望厚度，从而形成薄的完整高k层。
2.根据权利要求1所述的方法，其中，所述高k材料包括Ta2O5、TiO2、ZrO2、Al2O3、Y2O3、HfSiOx、HfO2、ZrSiOx、TaSiOx、SrOx、SrSiOx、LaOx、LaSiOx、YOx或YSiOx，或者它们中两项或更多项的组合。
3.根据权利要求1所述的方法，其中，所述厚的完整高k层的最小厚度在约30A到约200A之间。
4.根据权利要求1所述的方法，其中，所述厚的完整高k层的最小厚度在约50A到约100A之间。
5.根据权利要求1所述的方法，其中，所述沉积包括热化学气相沉积、等离子体增强化学气相沉积、原子层沉积或物理气相沉积。
6.根据权利要求1所述的方法，其中，所述薄的完整高k层的期望厚度在约5A到约50A之间。
7.根据权利要求1所述的方法，其中，所述薄的完整高k层的期望厚度在约10A到约30A之间。
8.根据权利要求1所述的方法，其中，所述的提供包括提供衬底上形成有界面层的衬底，所述的沉积包括在所述界面层上沉积所述高k材料。
9.根据权利要求8所述的方法，其中，所述界面层包括氧化物层、氮化物层、或氧氮化物层，或者它们中两项或更多项的组合。
10.根据权利要求1所述的方法，其中，所述的变薄包括将所沉积的高k层暴露于等离子处理。
11.根据权利要求10所述的方法，其中，所述等离子处理包括含有惰性气体的处理气体。
12.根据权利要求11所述的方法，其中，所述惰性气体包括He、Ne、Ar、Kr、或Xe，或者它们中两项或更多项的组合。
13.根据权利要求11所述的方法，其中，所述处理气体还包括反应性气体。
14.根据权利要求13所述的方法，其中，所述反应性气体包括HCl、HBr、Cl2、Br2、CxHyXz、或CxHyXz，或者它们中两项或更多项的组合。
15.根据权利要求10所述的方法，其中，其中，所述等离子处理包括以反应刻蚀工艺刻蚀所述厚的完整高k层。
16.根据权利要求10所述的方法，其中，所述等离子处理包括对部分所述厚的完整高k层进行改性并用湿法处理除去被改性的部分。
17.一种用于在衬底上形成薄的含铪高k层的方法，所述方法包括：
在处理室中提供衬底，所述衬底具有形成于其上的界面层；
以TCVD工艺使含铪高k材料至少沉积到在所述界面层上形成厚的完整含铪高k层所必需的最小厚度；以及
使所述厚的完整含铪高k层变薄到小于所述最小厚度的期望厚度，从而形成薄的完整含铪高k层。
18.根据权利要求17所述的方法，其中，所述厚的完整含铪高k层的最小厚度在约30A到约200A之间。
19.根据权利要求17所述的方法，其中，所述薄的完整含铪高k层的期望厚度在约5A到约50A之间。
20.根据权利要求17所述的方法，其中，其中，所述的变薄包括以反应刻蚀工艺刻蚀所沉积的含铪高k层。
21.根据权利要求17所述的方法，其中，所述的变薄包括在等离子处理中对部分所述厚的完整含铪高k层进行改性并用湿法处理除去被改性的部分。
CNA2005800329588A 2004-09-30 2005-08-31 用于形成薄的完整高介电常数介电层的方法 Pending CN101032004A (zh)

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