CN101021821A - Advanced high-performance system bus connector device and advanced high-performance system bus device - Google Patents
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Abstract
本发明公开了一种先进高性能系统总线连接装置及先进高性能系统总线，其中该先进高性能系统总线连接装置包括先进高性能系统总线AHB主器件控制模块、AHB请求仲裁模块和AHB从器件控制模块，其种：所述AHB主器件控制模块包括至少2组前后设置的第一寄存器，每组第一寄存器用于接收并锁存输入信号；所述AHB从器件控制模块包括至少一组第二寄存器，第二寄存器用于锁存输入及输出信号；所述AHB主器件控制模块、AHB请求仲裁模块和所述AHB从器件控制模块之间通过第一寄存器和第二寄存器实现交互。本发明通过采用流水线方式(寄存器实现)，使得系统总线频率得以提升的同时，提高了数据写操作的处理效率。
The invention discloses an advanced high-performance system bus connection device and an advanced high-performance system bus, wherein the advanced high-performance system bus connection device includes an advanced high-performance system bus AHB master device control module, an AHB request arbitration module and an AHB slave device control module Module, its kind: the AHB master device control module includes at least 2 groups of first registers set before and after, each group of first registers is used to receive and latch input signals; the AHB slave device control module includes at least one group of second registers registers, and the second register is used to latch input and output signals; the AHB master device control module, the AHB request arbitration module and the AHB slave device control module realize interaction through the first register and the second register. The invention improves the processing efficiency of the data write operation while improving the frequency of the system bus by adopting the pipeline mode (realized by the register).
Description
Technical field
The present invention relates to the AHB (advanced high-performance system bus) of a kind of AMBA (advanced microcontroller bus architecture) agreement, particularly a kind of advanced high-performance system bus coupling arrangement and advanced high-performance system bus device.
Background technology
In the computer system of complexity, a plurality of processors and various peripherals can be used at swap data between the integrated chip or between integrated chip and external unit.Some computer systems uses are various, independently bus transmits data.
Standard A MBA interface can comprise two main buses, promptly advanced high-performance system bus AHB and advanced peripheral bus APB.In AMBA bus specification, defined bus as different topology such as advanced high-performance system bus, AS bus, advanced peripheral buses by the research and development of ARM company.Wherein, advanced high-performance system bus AHB is widely used in the bus topology that needs high performance embedding microprocessor system.
As shown in Figure 1, the structural representation of the AHB coupling arrangement that proposes for ARM company, though this AHB coupling arrangement efficient shown in Figure 1 is very high, but because AHB main device (Master) and AHB directly transmit from the signal between the device (Slave), cause AHB main device (Master) and AHB to have relevance from sequential (timing) relation of device (Slave), influenced bus frequency, the bus frequency of realization is not high.
Summary of the invention
The purpose of this invention is to provide a kind of advanced high-performance system bus coupling arrangement and advanced high-performance system bus device, improve advanced high-performance system bus frequency.
To achieve these goals, the invention provides a kind of advanced high-performance system bus coupling arrangement, comprise that advanced high-performance system bus AHB main device control module, AHB request arbitration modules and AHB are from the device control module, wherein:
Described AHB main device control module comprises first register that is provided with before and after at least 2 groups, and every group first register is used for receiving and latch input signal;
Described AHB comprises at least one group second register from the device control module, and second register is used to latch input and output signal;
Described AHB main device control module, AHB request arbitration modules and described AHB are from realizing mutual by first register and second register between the device control module.
Above-mentioned advanced high-performance system bus coupling arrangement, wherein, described first register is 2 groups or 3 groups.
Above-mentioned advanced high-performance system bus coupling arrangement, wherein, described AHB request moderator module can be arbitrated according to configuration, or arbitrates according to the time order of occurrence of request.
Above-mentioned advanced high-performance system bus coupling arrangement, wherein, described AHB main device control module is write at described first register controls drop-down main device echo-plex ready signal when full.
Above-mentioned advanced high-performance system bus coupling arrangement, wherein, described AHB main device control module also is used for the transmission ready signal drop-down, will transmit on the ready signal after data manipulation is really finished and draw.
Above-mentioned advanced high-performance system bus coupling arrangement, wherein, described AHB main device control module will transmit ready signal when burst type signals is single-mode SINGLE drop-down, will transmit on the ready signal after data manipulation is really finished and draw.
In order better to realize above-mentioned purpose, the present invention also provides a kind of advanced high-performance system bus device, comprise advanced high-performance system bus coupling arrangement, described advanced high-performance system bus coupling arrangement comprises that advanced high-performance system bus AHB main device control module, AHB request arbitration modules and AHB are from the device control module, wherein:
Described AHB main device control module comprises first register that is provided with before and after at least 2 groups, and every group first register is used for receiving and latch input signal;
Described AHB comprises at least one group second register from the device control module, and second register is used to latch input and output signal;
Described AHB main device control module, AHB request arbitration modules and described AHB are from realizing mutual by first register and second register between the device control module.
Above-mentioned advanced high-performance system bus device, wherein, described first register is 2 groups or 3 groups.
Above-mentioned advanced high-performance system bus device, wherein, described AHB request moderator module can be arbitrated according to configuration, or arbitrates according to the time order of occurrence of request.
Above-mentioned advanced high-performance system bus device, wherein, described AHB main device control module is write at described first register controls drop-down main device echo-plex ready signal when full.
Above-mentioned advanced high-performance system bus device, wherein, described AHB main device control module also is used for the transmission ready signal drop-down, will transmit on the ready signal after data manipulation is really finished and draw.
Above-mentioned advanced high-performance system bus device, wherein, described AHB main device control module will transmit ready signal when burst type signals is single-mode SINGLE drop-down, will transmit on the ready signal after data manipulation is really finished and draw.
The present invention has following beneficial effect:
By adopting pipeline system (register realization), all signals of cut-out AHB main device and AHB contact directly from device, make that sequential (timing) relation on both sides is relatively independent, and system bus frequency is promoted;
Owing to adopt pipeline system, AHB main device control module also not with AHB when the device control module is docked, all AHB main devices can begin the operation of write data, even can finish whole data manipulation, have effectively improved treatment effeciency.
Description of drawings
Fig. 1 is the structural representation of the AHB coupling arrangement of ARM company proposition;
Fig. 2 is the structural representation of advanced high-performance system bus coupling arrangement of the present invention;
Fig. 3 is the AHB main device control module of the first embodiment of the present invention and from the structural representation of device control module;
Signal Processing sequential synoptic diagram when Fig. 4 is two-level pipeline;
Signal Processing sequential synoptic diagram when Fig. 5 is three class pipeline;
The signal operation sequential synoptic diagram of enable write buffer control not when Fig. 6 is Hburst=SINGLE;
Fig. 7 is the not signal operation sequential synoptic diagram of enable write buffer control of all types.
Embodiment
For a better understanding of the present invention, this earlier to the present invention in involved signal describe.
Write data HWDATA will be stored in the data from device by the main device appointment;
Read data HRDATA is from the data of reading from device by the main device appointment;
System clock HCLK, system clock;
Bus takies enabling signal HMASTER, bus is taken permission authorize one of them main device;
Address bus signal HADDR, representative is by the address from the memory location of device of main device appointment;
Transmission type signal HTRANS, the type of the data that representative will be transmitted;
Direction of transfer signal HWRITE has second logic state when data are written into from device, and when data ingeniously from when device is read, having first logic state;
Transmit high low signal HSIZE, the size of the data that just are being transmitted;
Burst type signals HBURST, the current signal that is transmitted is a burst;
Protection control signal HPROT, representative is as additional informations such as the taking-up of operation code or data accesses;
Transmit ready signal HREADY, when having finished the transmission of data, have second logic state, and when data are transmitted, have first logic state;
Transmit response signal HRESP, the additional information on the representative data delivery status can be categorized as OK, mistake, retry and division etc.
Main device echo-plex ready signal hready resp, main device is according to hready signal and main device busy-idle condition at that time, and the echo-plex ready signal must be the foundation of data manipulation with this signal from device.
Advanced high-performance system bus coupling arrangement of the present invention and advanced high-performance system bus device, adopt pipeline system (register latchs), cut off all signals and AHB the contacting directly of AHB main device from device, wherein signal comprises signal above-mentioned, make that sequential (timing) relation on both sides is relatively independent, system bus frequency is promoted.
As shown in Figure 2, advanced high-performance system bus coupling arrangement of the present invention comprises that interconnected a plurality of AHB main device control module, AHB request arbitration modules and AHB are from the device control module, wherein:
AHB main device control module, be used for receiving and latch the order that the AHB main device sends with pipeline system (utilizing register), and mutual with AHB request arbitration modules, with AHB from the device control module dock back by signal realization data alternately, when write operation, write data is existed among the FIFO, when read operation, data are taken out in FIFO;
AHB asks arbitration modules, is used to write down the application that each AHB main device control module is sent, and after arbitrating by configuration requirement arbitration result is sent to AHB from the device control module;
AHB docks with corresponding AHB main device control module according to arbitration result from the device control module, realizes the mutual of data by signal, and use register latch output signal, when write operation, write data is read from FIFO, when read operation, data are write among the FIFO.
Because control of AHB main device and AHB do not have direct sequential relationship between device control, the operation of AHB main device control section is to decide according to the state of its FIFO that sees and streamline.
The running of AHB request moderator module is under two kinds of patterns:
The configuration mode of no time consistency, the user can dispose the right of priority of each AHB main device control module, and AHB request moderator module can be arbitrated according to configuration;
The configuration mode of time consistency, AHB asks the time order of occurrence of each request of moderator module records, and arbitrates according to time sequencing.
AHB is exactly the hready resp of the input from AHB from device from the hready signal of device control module output, but does not have directly linking to each other on the combinational logic from the device hready resp and the hready of main device, therefore can the processing speed height.
Further the present invention is described in more detail below with different examples.
＜the first embodiment 〉
In the first embodiment of the present invention, be two level production lines.
As shown in Figure 3, for the AHB main device control module of the first embodiment of the present invention with from the structural representation of device control module, wherein:
Two groups of registers that are provided with before and after AHB main device control module comprises, be used for receiving and latch the order that the AHB main device sends with pipeline system (utilizing register), and when two-stage flowing water has all been expired, can control drop-down hready resp (this also can be reflected on the hready), as shown in Figure 4, wherein supposition AHB is the peripheral hardware of a low-response from device among Fig. 4, and supposes the AHB signal band prefix m0 that sees at the AHB main device, and the signal of seeing from device at AHB does not have prefix.
Above-mentioned design can AHB main device control module also not with AHB when the device control module is docked, all AHB main devices can begin the operation of write data, even can finish whole data manipulation.
＜the second embodiment 〉
In the second embodiment of the present invention, be three class pipeline.
Three groups of registers that are provided with before and after AHB main device control module comprises, be used for receiving and latch the order that the AHB main device sends with pipeline system (utilizing register), and when two-stage flowing water has all been expired, can control drop-down hready_resp (this also can be reflected on the hready), as shown in Figure 5, wherein supposition AHB is the peripheral hardware of a low-response from device among Fig. 4, and supposes the AHB signal band prefix m0 that sees at the AHB main device, and the signal of seeing from device at AHB does not have prefix.
Because be three class pipeline, so AHB is from the bus operation of the device late clock period than two-level pipeline.
Above-mentioned design can AHB main device control module also not with AHB when the device control module is docked, all AHB main devices can begin the operation of write data, even can finish whole data manipulation.
Second embodiment is for first embodiment, and for each AHB main device, three grades of flowing water can allow to finish more write operation continuously, can be so that higher in the write operation efficient of AHB main device.
＜the three embodiment 〉
Therefore, the present invention adds streamline (passing through register) on AHB coupling arrangement shown in Figure 1, make the AHB coupling arrangement speed and the efficient of whole pipeline system all be improved, but after increasing streamline, pipeline system AHB coupling arrangement has also brought new problem: because the AHB coupling arrangement of pipeline system also is stream line operation to data, be that data have cushioning effect on this matrix, this cushioning effect is for non-pure memory system, deal with improperly and can produce some problems, below this problem is illustrated.
If (AHB is from device at a peripheral system, or advanced peripheral bus APB device) in, if peripheral hardware is initiated a DMA (direct memory visit) write operation application, DMA obtains data from other zone, be written to then in this peripheral system, and this write operation is through the AHB coupling arrangement of pipeline system, this AHB coupling arrangement is that cushioning effect is arranged, so the AHB coupling arrangement thinks that still have data space to use this moment, so put height transmitting ready signal HREADY, data are accepted in expression, and following situation will appear in this moment:
Possible AHB coupling arrangement is still being handled other data, has no idea to handle to rigidly connect the data that are subjected to;
And DMA thinks that data have write (because HREADY has put height) in the peripheral hardware, ask signal so DMA (non-ahb bus signal) sends in the removing.
Above-mentioned phenomenon is with regard to causing a problem, that is: for peripheral hardware, it does not receive this write data, and DMA thinks that data have been written in the peripheral hardware, and this will cause follow-up operating mistake, is that institute of system is unacceptable.
For fear of the erroneous effects of bringing because of the cushioning effect of streamline, write buffering by setting in the third embodiment of the present invention and enable to control this problem that solves.
Be provided with one and write buffering and make energy control module, the opening and closing that buffering enables are write in control.
Writing under the situation that buffering do not enable, in the third embodiment of the present invention, AHB main device control module can be drop-down hready in advance, only after data manipulation is really finished, just drawing on the hready.
In the third embodiment of the present invention, write the buffering realization that enables to control and include dual mode:
Directly support the control (hport has the control of buffering on the agreement) of the hport that each AHB main device sends;
Yet because the AHB main device of the overwhelming majority is not all done the control about buffering on the hport, therefore another mode is: write buffering and enable control for each AHB main device is provided with respectively, and each AHB main device control module is write buffering and enabled control and be divided into and enable entirely to enable with window.
Simultaneously, in the third embodiment of the present invention, can support following situation:
Write buffering when only supporting hburst=SINGLE and enable control, because actual this generic operation can be considered as the I/O operation, and most of AHB main device is operated as I/O with hburst=SINGLE all, its time sequential routine synoptic diagram as shown in Figure 6;
Support the buffering of writing of all types to enable control, though the AHB agreement has all defined the length of various operations, agreement is to allow end operation midway, and therefore the signal of monitoring htrans changes in real time, and the sequential of this implementation as shown in Figure 7.
Should be noted that at last, above embodiment is only unrestricted in order to technical scheme of the present invention to be described, although the present invention is had been described in detail with reference to preferred embodiment, those of ordinary skill in the art is to be understood that, can make amendment or be equal to replacement technical scheme of the present invention, and not breaking away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (12)
1. advanced high-performance system bus coupling arrangement comprises that advanced high-performance system bus AHB main device control module, AHB request arbitration modules and AHB from the device control module, is characterized in that:
Described AHB main device control module comprises first register that is provided with before and after at least 2 groups, and every group first register is used for receiving and latch input signal;
Described AHB comprises at least one group second register from the device control module, and second register is used to latch input and output signal;
Described AHB main device control module, AHB request arbitration modules and described AHB are from realizing mutual by first register and second register between the device control module.
2. advanced high-performance system bus coupling arrangement according to claim 1 is characterized in that, described first register is 2 groups or 3 groups.
3. advanced high-performance system bus coupling arrangement according to claim 1 is characterized in that, described AHB request moderator module can be arbitrated according to configuration, or arbitrates according to the time order of occurrence of request.
4. advanced high-performance system bus coupling arrangement according to claim 1 is characterized in that, described AHB main device control module is write at described first register controls drop-down main device echo-plex ready signal when full.
5. advanced high-performance system bus coupling arrangement according to claim 1 is characterized in that, described AHB main device control module also is used for the transmission ready signal drop-down, will transmit on the ready signal after data manipulation is really finished and draw.
6. advanced high-performance system bus coupling arrangement according to claim 5, it is characterized in that, described AHB main device control module will transmit ready signal when burst type signals is single-mode SINGLE drop-down, will transmit on the ready signal after data manipulation is really finished and draw.
7. advanced high-performance system bus device, comprise advanced high-performance system bus coupling arrangement, described advanced high-performance system bus coupling arrangement comprises that advanced high-performance system bus AHB main device control module, AHB request arbitration modules and AHB from the device control module, is characterized in that:
Described AHB main device control module comprises first register that is provided with before and after at least 2 groups, and every group first register is used for receiving and latch input signal;
Described AHB comprises at least one group second register from the device control module, and second register is used to latch input and output signal;
Described AHB main device control module, AHB request arbitration modules and described AHB are from realizing mutual by first register and second register between the device control module.
8. advanced high-performance system bus device according to claim 7 is characterized in that, described first register is 2 groups or 3 groups.
9. advanced high-performance system bus device according to claim 7 is characterized in that, described AHB request moderator module can be arbitrated according to configuration, or arbitrates according to the time order of occurrence of request.
10. advanced high-performance system bus device according to claim 7 is characterized in that, described AHB main device control module is write at described first register controls drop-down main device echo-plex ready signal when full.
11. advanced high-performance system bus device according to claim 7 is characterized in that, described AHB main device control module also is used for the transmission ready signal drop-down, will transmit on the ready signal after data manipulation is really finished and draw.
12. advanced high-performance system bus device according to claim 11, it is characterized in that, described AHB main device control module will transmit ready signal when burst type signals is single-mode SINGLE drop-down, will transmit on the ready signal after data manipulation is really finished and draw.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854541B (en) * | 2009-04-03 | 2012-04-18 | 广达电脑股份有限公司 | Video compression circuit and method thereof |
| CN102710890A (en) * | 2012-04-06 | 2012-10-03 | 东莞中山大学研究院 | Video Processing System-on-Chip with Dual AHB Bus |
| CN105403769A (en) * | 2015-09-30 | 2016-03-16 | 中国农业大学 | Circuit structure based on FFT short-time Fourier analysis and control method thereof |
| CN107423249A (en) * | 2017-02-28 | 2017-12-01 | 广东工业大学 | It is a kind of based on AHB lite bus protocols from end bus control unit design method |
| CN112612500A (en) * | 2020-12-30 | 2021-04-06 | 锐捷网络股份有限公司 | Method and device for upgrading BMC, electronic equipment and storage medium |
| CN113590200A (en) * | 2021-08-03 | 2021-11-02 | 北京中科芯蕊科技有限公司 | Asynchronous miniflow line controller based on SR latch |
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2007
- 2007-03-20 CN CNB2007100891580A patent/CN100517283C/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101854541B (en) * | 2009-04-03 | 2012-04-18 | 广达电脑股份有限公司 | Video compression circuit and method thereof |
| CN102710890A (en) * | 2012-04-06 | 2012-10-03 | 东莞中山大学研究院 | Video Processing System-on-Chip with Dual AHB Bus |
| CN102710890B (en) * | 2012-04-06 | 2014-11-05 | 东莞中山大学研究院 | Video processing system-on-chip with double AHB buses |
| CN105403769A (en) * | 2015-09-30 | 2016-03-16 | 中国农业大学 | Circuit structure based on FFT short-time Fourier analysis and control method thereof |
| CN105403769B (en) * | 2015-09-30 | 2018-05-11 | 中国农业大学 | A kind of circuit structure and its control method based on FFT Short Time Fourier Analysis |
| CN107423249A (en) * | 2017-02-28 | 2017-12-01 | 广东工业大学 | It is a kind of based on AHB lite bus protocols from end bus control unit design method |
| CN112612500A (en) * | 2020-12-30 | 2021-04-06 | 锐捷网络股份有限公司 | Method and device for upgrading BMC, electronic equipment and storage medium |
| CN113590200A (en) * | 2021-08-03 | 2021-11-02 | 北京中科芯蕊科技有限公司 | Asynchronous miniflow line controller based on SR latch |
| CN113590200B (en) * | 2021-08-03 | 2024-01-30 | 北京中科芯蕊科技有限公司 | Asynchronous micro-pipeline controller based on SR latch |
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Effective date of registration: 20221130 Address after: 518055 Zhongxing Industrial Park, Liuxian Avenue, Xili street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 Ministry of justice, Zhongxing building, South Science and technology road, Nanshan District hi tech Industrial Park, Shenzhen, Guangdong Patentee before: ZTE Corp. Patentee before: SANECHIPS TECHNOLOGY Co.,Ltd. |